Texas Instruments SimpleLink CC2620 Technical Reference Manual page 78

Cortex-M3 Processor Registers
2.7.2.1 CTRL Register (Offset = 0h) [reset = 260h]
CTRL is shown in
Control
This register is used to enable the flash patch block.
31 30
23 22
15 14
RESERVED
R-0h
7 6
NUM_CODE1
Bit Field
31-14 RESERVED
13-12 NUM_CODE2
11-8 NUM_LIT
7-4 NUM_CODE1
3-2 RESERVED
1 KEY
0 ENABLE
78
Figure 2-24 and described in
Figure 2-24. CTRL Register
29 28
21 20
13 12
NUM_CODE2
R-0h
5 4
R-6h
Table 2-48. CTRL Register Field Descriptions
Type Reset
R 0h
R 0h
R 2h
R 6h
R 0h
W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-48.
27
RESERVED
R-0h
19
RESERVED
R-0h
11
3
RESERVED
R-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Number of full banks of code comparators, sixteen comparators per
bank. Where less than sixteen code comparators are provided, the
bank count is zero, and the number present indicated by
NUM_CODE1. This read only field contains 3'b000 to indicate 0
banks for Cortex-M processor.
Number of literal slots field.
0x0: No literal slots
0x2: Two literal slots
Number of code slots field.
0x0: No code slots
0x2: Two code slots
0x6: Six code slots
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Key field. In order to write to this register, this bit-field must be
written to '1'. This bit always reads 0.
Flash patch unit enable bit
0x0: Flash patch unit disabled
0x1: Flash patch unit enabled
SWCU117C – February 2015 – Revised September 2015
26 25
18 17
10 9
NUM_LIT
R-2h
2 1
KEY
W-0h
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24
16
8
0
ENABLE
R/W-0h