Top Level Debug System - Texas Instruments SimpleLink CC2620 Technical Reference Manual

Top Level Debug System

ID
[1]
[2]
5.1 Top Level Debug System
The debug subsystem in the CC26xx and CC13xx devices implements two IEEE standards for debug and
test purposes:
• IEEE standard 1149.1: Standard Test Access Port and Boundary Scan Architecture Test Access Port
(TAP) [1]. This standard is known by the acronym JTAG.
• Class 4 IEEE 1149.7: Standard for Reduced-pin and Enhanced-functionality Test Access Port and
Boundary-scan Architecture [2]. This is known by acronym cJTAG (compact JTAG). This standard
serializes the IEEE 1149.1 transactions using a variety of compression formats to reduce the number
of pins needed to implement a JTAG debug port.
The debug subsystem also implements a firewall for unauthorized access to debug/test ports.
shows a block diagram of debug subsystem.
390
JTAG Interface
Table 5-1. References
Description
IEEE Standard Test Access Port and Boundary Scan Architecture, IEEE Std 1149.1a
1993 and Supplement Std. 1149.1b 1994, The Institute of Electrical and Electronics
Engineers, Inc.
IEEE 1149.7 Standard for Reduced-Pin and Enhanced-Functionality Test Access Port
and Boundary-Scan Architecture
Copyright © 2015, Texas Instruments Incorporated
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
www.ti.com
Figure 5-1