Texas Instruments SimpleLink CC2620 Technical Reference Manual page 176

Cortex-M3 Processor Registers
2.7.4.35 SHCSR Register (Offset = D24h) [reset = 0h]
SHCSR is shown in
System Handler Control and State
This register is used to enable or disable the system handlers, determine the pending status of bus fault,
mem manage fault, and SVC, determine the active status of the system handlers. If a fault condition
occurs while its fault handler is disabled, the fault escalates to a Hard Fault.
31 30
23 22
15 14
SVCALLPEND BUSFAULTPE
ED NDED
R-0h R-0h
7 6
SVCALLACT
R-0h
Bit Field
31-19 RESERVED
18 USGFAULTENA
17 BUSFAULTENA
16 MEMFAULTENA
15 SVCALLPENDED
14 BUSFAULTPENDED
13 MEMFAULTPENDED
12 USGFAULTPENDED
176
Figure 2-105 and described in
Figure 2-105. SHCSR Register
29 28
RESERVED
21 20
RESERVED
R/W-0h
13 12
MEMFAULTPE USGFAULTPE
NDED NDED
R-0h R-0h
5 4
RESERVED
R-0h
Table 2-131. SHCSR Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R 0h
R 0h
R 0h
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-131.
27 26
R/W-0h
19 18
USGFAULTEN
A
R/W-0h
11 10
SYSTICKACT PENDSVACT
R-0h R-0h
3 2
USGFAULTAC RESERVED
T
R-0h R-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Usage fault system handler enable
0h = Exception disabled
1h = Exception enabled
Bus fault system handler enable
0h = Exception disabled
1h = Exception enabled
MemManage fault system handler enable
0h = Exception disabled
1h = Exception enabled
SVCall pending
0h = Exception is not active
1h = Exception is pending.
BusFault pending
0h = Exception is not active
1h = Exception is pending.
MemManage exception pending
0h = Exception is not active
1h = Exception is pending.
Usage fault pending
0h = Exception is not active
1h = Exception is pending.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
17 16
BUSFAULTEN MEMFAULTEN
A A
R/W-0h R/W-0h
9 8
RESERVED MONITORACT
R-0h R-0h
1 0
BUSFAULTAC MEMFAULTAC
T T
R-0h R-0h
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