Texas Instruments SimpleLink CC2620 Technical Reference Manual page 202

Cortex-M3 Processor Registers
2.7.4.57 DCRSR Register (Offset = DF4h) [reset = X]
DCRSR is shown in
Deubg Core Register Selector
The purpose of this register is to select the processor register to transfer data to or from. This write-only
register generates a handshake to the core to transfer data to or from Debug Core Register Data Register
and the selected register. Until this core transaction is complete, DHCSR.S_REGRDY is 0. Note that
writes to this register in any size but word are Unpredictable.
Note that PSR registers are fully accessible this way, whereas some read as 0 when using MRS
instructions. Note that all bits can be written, but some combinations cause a fault when execution is
resumed.
31 30
23 22
15 14
7 6
RESERVED
W-X
Bit Field
31-17 RESERVED
16 REGWNR
15-5 RESERVED
4-0 REGSEL
202
Figure 2-127 and described in
Figure 2-127. DCRSR Register
29 28
RESERVED
21 20
RESERVED
W-X
13 12
RESERVED
5 4
Table 2-153. DCRSR Register Field Descriptions
Type Reset
W X
W X
W X
W X
Copyright © 2015, Texas Instruments Incorporated
Table 2-153.
27 26
W-X
19 18
11 10
W-X
3 2
REGSEL
W-X
Description
Software must not rely on the value of a reserved. Write 0.
1: Write
0: Read
Software must not rely on the value of a reserved. Write 0.
Register select
0x00: R0
0x01: R1
0x02: R2
0x03: R3
0x04: R4
0x05: R5
0x06: R6
0x07: R7
0x08: R8
0x09: R9
0x0A: R10
0x0B: R11
0x0C: R12
0x0D: Current SP
0x0E: LR
0x0F: DebugReturnAddress
0x10: XPSR/flags, execution state information, and exception
number
0x11: MSP (Main SP)
0x12: PSP (Process SP)
0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 |
PRIMASK
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
17 16
REGWNR
W-X
9 8
1 0
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