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7.8.1.29 FEDACCTL1 Register (Offset = 2008h) [reset = 0h]
FEDACCTL1 is shown in
Internal. Only to be used through TI provided API.
31
30
23
22
15
14
7
6
Bit
Field
31-25
RESERVED
24
SUSP_IGNR
23-0
EDACEN
SWCU117C – February 2015 – Revised September 2015
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Figure 7-38
and described in
Figure 7-38. FEDACCTL1 Register
29
28
RESERVED
R-0h
21
20
EDACEN
R-0h
13
12
EDACEN
R-0h
5
4
EDACEN
R-0h
Table 7-32. FEDACCTL1 Register Field Descriptions
Type
Reset
R
0h
R/W
0h
R
0h
Copyright © 2015, Texas Instruments Incorporated
Table
7-32.
27
26
19
18
11
10
3
2
Description
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Versatile Instruction Memory System (VIMS)
VIMS Registers
25
24
SUSP_IGNR
R/W-0h
17
16
9
8
1
0
575