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ESAI Programming Model
11
23
The ESAI SAISR register is located at x:$FFFFB3. The ESAI_1 SAISR register is located at y:$FFFF93.
8.3.6.1
SAISR Serial Input Flag 0 (IF0) - Bit 0
The IF0 bit is enabled only when the SCKR pin is defined as ESAI in the Port Control Register, SYN=1 and RCKD=0, indicating that SCKR
is an input flag and the synchronous mode is selected. Data present on the SCKR pin is latched during reception of the first received data bit
after frame sync is detected. The IF0 bit is updated with this data when the receiver shift registers are transferred into the receiver data
registers. IF0 reads as a zero when it is not enabled. Hardware, software, ESAI individual and STOP reset clear IF0.
8.3.6.2
SAISR Serial Input Flag 1 (IF1) - Bit 1
The IF1 bit is enabled only when the FSR pin is defined as ESAI in the Port Control Register, SYN =1, RFSD=0 and TEBE=0, indicating that
FSR is an input flag and the synchronous mode is selected. Data present on the FSR pin is latched during reception of the first received data
bit after frame sync is detected. The IF1 bit is updated with this data when the receiver shift registers are transferred into the receiver data
registers. IF1 reads as a zero when it is not enabled. Hardware, software, ESAI individual and STOP reset clear IF1.
8.3.6.3
SAISR Serial Input Flag 2 (IF2) - Bit 2
The IF2 bit is enabled only when the HCKR pin is defined as ESAI in the Port Control Register, SYN=1 and RHCKD=0, indicating that
HCKR is an input flag and the synchronous mode is selected. Data present on the HCKR pin is latched during reception of the first received
data bit after frame sync is detected. The IF2 bit is updated with this data when the receive shift registers are transferred into the receiver data
registers. IF2 reads as a zero when it is not enabled. Hardware, software, ESAI individual and STOP reset clear IF2.
8.3.6.4
SAISR Reserved Bits - Bits 5-3, 12-11, 23-18
These bits are reserved for future use. They read as zero.
8.3.6.5
SAISR Receive Frame Sync Flag (RFS) - Bit 6
When set, RFS indicates that a receive frame sync occurred during reception of the words in the receiver data registers. This indicates that the
data words are from the first slot in the frame. When RFS is clear and a word is received, it indicates (only in the network mode) that the frame
sync did not occur during reception of that word. RFS is cleared by hardware, software, ESAI individual, or STOP reset. RFS is valid only if
at least one of the receivers is enabled (REx=1).
In normal mode, RFS always reads as a one when reading data because there is only one time slot per
frame – the "frame sync" time slot.
8.3.6.6
SAISR Receiver Overrun Error Flag (ROE) - Bit 7
The ROE flag is set when the serial receive shift register of an enabled receiver is full and ready to transfer to its receiver data register (RXx)
and the register is already full (RDF=1). If REIE is set, an ESAI receive data with exception (overrun error) interrupt request is issued when
ROE is set. Hardware, software, ESAI individual and STOP reset clear ROE. ROE is also cleared by reading the SAISR with ROE set,
followed by reading all the enabled receive data registers.
8-26
10
9
8
7
RODF
REDF
RDF
ROE
22
21
20
19
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-12. SAISR Register
NOTE
DSP56374 Users Guide, Rev. 1.2
6
5
4
3
RFS
18
17
16
15
TODE
TEDE
TDE
2
1
0
IF2
IF1
IF0
14
13
12
TUE
TFS
Freescale Semiconductor
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