Comm Timer External Clock[7:0]; Memory Map/Register Definition; Timer Module Register Map - Freescale Semiconductor MCF5480 Reference Manual

The fixed timer channel provides the user with two modes, a programmable baud clock generator mode or
a fixed period task initiator mode.
• In baud clock generator mode the fixed timer channel outputs a cInitiator signal that is free
running.
• In fixed period task initiator mode the fixed timer channel outputs a cInitiator signal in response
to a cAcknowledge input from the multichannel DMA's PTD (priority task decode). It also outputs
a timerInterrupt signal to the processor if there is an error in the channel. In the current
implementation there are four fixed timer channels available.
The variable timer channel provides the user with the programmable baud clock generator mode or a
variable period task initiator mode.
• In baud clock generator mode the cInitiator output is free running.
• In variable period task initiator mode, the cInitiator output is influenced by the cAcknowledge
signal. Unlike the fixed timer channel, the variable timer channel does not have a timerInterrupt
output signal due to the variability of the period. In the current implementation there are four
variable channels available.
25.1.3

Comm Timer External Clock[7:0]

The comm timer external clock is the alternate clock signal and is provided by the user. The user must write
a 1 to CTCR[S] in the variable channel and write a 1001 to CTCR[S] within the fixed channel to select
this signal. If this signal is selected, all timing will be with respect to this clock signal. This signal is
restricted to being half the frequency or less of the system bus clock.
25.2

Memory Map/Register Definition

Section 25.2.2.1, "Comm Timer Configuration Register (CTCRn)—Fixed Timer Channel,"
Section 25.2.2.2, "Comm Timer Configuration Register (CTCRn)—Variable Timer Channel,"
registers contained within the timer module. Details are given regarding register mapping, programming
notes, bit definitions, and operating modes.
25.2.1

Timer Module Register Map

Table 25-2 shows the register mapping of the timer module.
Freescale Semiconductor
Table 25-1. Comm Timers External Clock
Timer Channel External Signal
0
1
2
3
4
5
6
7
MCF548x Reference Manual, Rev. 3
TIN0
TIN1
TIN2
TIN3
PSC3BCLK
PSC2BCLK
PSC1BCLK
PSC0BCLK
Memory Map/Register Definition
and
explain the
25-3