Floating-Point Assist Exception; Software Emulation Exception (0X01000); Instruction Tlb Miss Exception (0X01100) - Freescale Semiconductor MPC850 User Manual

Exceptions

6.1.2.11 Floating-Point Assist Exception

The floating-point assist exception is not generated by the MPC850. Attempting to execute
a floating-point causes an instruction implementation-specific software emulation
exception.
6.1.3 Implementation-Specific Exceptions
The following sections describe the MPC850's implementation-specific exceptions.

6.1.3.1 Software Emulation Exception (0x01000)

An software emulation exception occurs as a result of one of the following conditions:
• When executing any unimplemented instruction, including all illegal and
unimplemented optional and floating-point instructions.
• When executing a mtspr or mfspr that specifies an on-core unimplemented register,
regardless of SPR[0].
• When executing a mtspr or mfspr that specifies an off-core unimplemented register
and SPR[0] = 0 or MSR[PR] = 0 (no program exception condition).
In addition, the following registers are set:
Table 6-12. Register Settings after a Software Emulation Exception
Register
SRR0 Set to the EA of the instruction that caused the exception.
SRR1 1–40
10–150
OthersLoaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR IP No change
MENo change
LECopied from the ILE setting of the interrupted process
Others0
Execution resumes at offset 0x01000 from the base address indicated by MSR[IP].

6.1.3.2 Instruction TLB Miss Exception (0x01100)

This type of exception occurs if MSR[IR] = 1 and an attempt is made to fetch an instruction
from a page whose effective page number cannot be translated by TLB. The following
registers are set:
Setting
MPC850 Family User's Manual