Freescale Semiconductor MCF5482 Manuals

Manuals and User Guides for Freescale Semiconductor MCF5482. We have 1 Freescale Semiconductor MCF5482 manual available for free PDF download: Reference Manual

Freescale Semiconductor MCF5482 Reference Manual (1032 pages)

Freescale Semiconductor Circuit Board Reference Manual

Brand: Freescale Semiconductor | Category: Computer Hardware | Size: 8 MB

Mcf548X Reference Manual
1
Table of Contents
5
Mcf548X Reference Manual
41
- General Information
  44
- Acronyms and Abbreviations
  45
- Register Conventions
  45
Chapter 1 Overview

59
- Mcf548X Family Overview
  59
- Mcf548X Block Diagram
  60
- Mcf548X Family Products
  61
- Mcf548X Family Features
  61
- Coldfire V4E Core Overview
  63
- Debug Module (BDM)
  64
- Jtag
  64
- On-Chip Memories
  65
- Caches
  65
- System SRAM
  65
- PLL and Chip Clocking Options
  65
- Communications I/O Subsystem
  66
- DMA Controller
  66
- 10/100 Fast Ethernet Controller (FEC)
  66
- USB 2.0 Device (Universal Serial Bus)
  66
- Programmable Serial Controllers (Pscs)
  67
- I2C (Inter-Integrated Circuit)
  67
- DMA Serial Peripheral Interface (DSPI)
  67
- Controller Area Network (CAN)
  68
- DDR SDRAM Memory Controller
  68
- Peripheral Component Interconnect (PCI)
  68
- Flexible Local Bus (Flexbus)
  68
- Security Encryption Controller (SEC)
  69
- System Integration Unit (SIU)
  69
- Timers
  69
- Interrupt Controller
  70
- General Purpose I/O
  70
Chapter 2 Signal Descriptions

71
Chapter 3

105
- Core Overview
  105
- Features
  105
- Enhanced Pipelines
  106
- Instruction Fetch Pipeline (IFP)
  107
- Operand Execution Pipeline (OEP)
  108
- Harvard Memory Architecture
  110
- Debug Module Enhancements
  110
- Programming Model
  111
- User Programming Model
  113
- Data Registers (D0-D7)
  113
- Address Registers (A0-A6)
  113
- User Stack Pointer (A7)
  113
- Program Counter (PC)
  113
- Condition Code Register (CCR)
  113
- EMAC Programming Model
  114
- FPU Programming Model
  114
- Supervisor Programming Model
  115
- Status Register (SR)
  116
- Vector Base Register (VBR)
  116
- Cache Control Register (CACR)
  117
- Access Control Registers (ACR0-ACR3)
  117
- RAM Base Address Registers (RAMBAR0 and RAMBAR1)
  117
- Module Base Address Register (MBAR)
  117
- Programming Model Table
  117
- Data Format Summary
  119
- Data Organization in Registers
  119
- Integer Data Format Organization in Registers
  119
- Integer Data Format Organization in Memory
  120
- EMAC Data Representation
  121
  - Floating-Point Data Formats and Types
    121
- Addressing Mode Summary
  122
- Instruction Set Summary
  123
- Additions to the Instruction Set Architecture
  123
- Instruction Set Summary
  126
- Instruction Execution Timing
  131
- MOVE Instruction Execution Timing
  132
- One-Operand Instruction Execution Timing
  134
- Two-Operand Instruction Execution Timing
  135
- Miscellaneous Instruction Execution Timing
  136
- Branch Instruction Execution Timing
  137
- EMAC Instruction Execution Times
  138
- FPU Instruction Execution Times
  139
- Exception Processing Overview
  140
- Exception Stack Frame Definition
  142
- Processor Exceptions
  143
- Precise Faults
  146
Chapter 4 Enhanced Multiply-Accumulate Unit (EMAC)

149
- Introduction
  149
- MAC Overview
  150
- General Operation
  150
- Memory Map/Register Definition
  153
- MAC Status Register (MACSR)
  153
- Fractional Operation Mode
  156
- Mask Register (MASK)
  158
- EMAC Instruction Set Summary
  159
- EMAC Instruction Execution Timing
  159
- Data Representation
  160
- EMAC Opcodes
  161
Chapter 5 Memory Management Unit (MMU)

167
- Features
  167
- Virtual Memory Management Architecture
  167
- MMU Architecture Features
  167
- MMU Architecture Location
  168
- MMU Architecture Implementation
  169
- Precise Faults
  170
- MMU Access
  170
- Virtual Mode
  170
- Virtual Memory References
  170
- Instruction and Data Cache Addresses
  170
- Supervisor/User Stack Pointers
  171
- Access Error Stack Frame
  171
- Expanded Control Register Space
  171
- Changes to Acrs and CACR
  171
- ACR Address Improvements
  172
- Supervisor Protection
  173
- Debugging in a Virtual Environment
  173
- Virtual Memory Architecture Processor Support
  173
- Precise Faults
  173
- Supervisor/User Stack Pointers
  173
- Access Error Stack Frame Additions
  174
- MMU Definition
  175
- Effective Address Attribute Determination
  175
- MMU Functionality
  176
- MMU Organization
  176
- MMU Base Address Register (MMUBAR)
  176
- MMU Memory Map
  177
- MMU Control Register (MMUCR)
  177
- MMU Operation Register (MMUOR)
  178
- MMU Status Register (MMUSR)
  180
- MMU Fault, Test, or TLB Address Register (MMUAR)
  181
- MMU Read/Write Tag and Data Entry Registers (MMUTR and MMUDR)
  182
- Mmu Tlb
  184
- MMU Operation
  185
- MMU Implementation
  186
- TLB Address Fields
  186
- TLB Replacement Algorithm
  187
- TLB Locked Entries
  188
- MMU Instructions
  189
Chapter 6 Floating-Point Unit (FPU)

191
- Introduction
  191
- Overview
  191
- Notational Conventions
  191
- Operand Data Formats and Types
  193
- Signed-Integer Data Formats
  193
- Floating-Point Data Formats
  193
- Floating-Point Data Types
  194
- Normalized Numbers
  194
- Zeros
  194
- Infinities
  194
- Not-A-Number
  195
- Denormalized Numbers
  195
- Register Definition
  197
- Floating-Point Data Registers (FP0-FP7)
  197
- Floating-Point Control Register (FPCR)
  197
- Floating-Point Status Register (FPSR)
  199
- Floating-Point Instruction Address Register (FPIAR)
  200
- Floating-Point Computational Accuracy
  201
- Intermediate Result
  201
- Rounding the Result
  202
- Floating-Point Post-Processing
  204
- Underflow, Round, and Overflow
  204
- Conditional Testing
  205
- Floating-Point Exceptions
  207
- Floating-Point Arithmetic Exceptions
  208
- Branch/Set on Unordered (BSUN)
  209
- Input Not-A-Number (INAN)
  210
- Input Denormalized Number (IDE)
  210
- Operand Error (OPERR)
  211
- Overflow (OVFL)
  211
- Underflow (UNFL)
  212
- Divide-By-Zero (DZ)
  212
- Inexact Result (INEX)
  213
- Floating-Point State Frames
  213
- Instructions
  215
- Floating-Point Instruction Overview
  215
- Floating-Point Instruction Execution Timing
  217
- Key Differences between Coldfire and M68000 FPU Programming Models
  218
Chapter 7 Local Memory

221
- Interactions between Local Memory Modules
  221
- SRAM Overview
  221
- SRAM Operation
  222
- SRAM Register Definition
  222
- SRAM Base Address Registers (RAMBAR0/RAMBAR1)
  222
- SRAM Initialization
  224
- SRAM Initialization Code
  225
- Power Management
  226
- Cache Overview
  226
- Cache Organization
  227
- Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified
  228
- The Cache at Start-Up
  228
- Cache Operation
  230
- Caching Modes
  232
- Cacheable Accesses
  232
- Cache-Inhibited Accesses
  233
- Cache Protocol
  234
- Read Miss
  234
- Write Miss (Data Cache Only)
  234
- Read Hit
  235
- Write Hit (Data Cache Only)
  235
- Cache Coherency (Data Cache Only)
  235
- Memory Accesses for Cache Maintenance
  235
- Cache Filling
  235
- Cache Pushes
  236
- Cache Locking
  237
- Cache Register Definition
  239
- Cache Control Register (CACR)
  239
- Access Control Registers (ACR0-ACR3)
  242
- Cache Management
  243
- Cache Operation Summary
  246
- Instruction Cache State Transitions
  246
- Data Cache State Transitions
  247
- Cache Initialization Code
  250
Chapter 8 Debug Support

251
- Introduction
  251
- Overview
  251
- Signal Descriptions
  252
- Processor Status/Debug Data (PSTDDATA[7:0])
  253
- Real-Time Trace Support
  255
- Begin Execution of Taken Branch (PST = 0X5)
  256
- Processor Stopped or Breakpoint State Change (PST = 0Xe)
  257
- Processor Halted (PST = 0Xf)
  258
- Memory Map/Register Definition
  259
- Revision a Shared Debug Resources
  261
- Configuration/Status Register (CSR)
  261
- PC Breakpoint ASID Control Register (PBAC)
  264
- BDM Address Attribute Register (BAAR)
  265
- Address Attribute Trigger Registers (AATR, AATR1)
  266
- Trigger Definition Register (TDR)
  267
- Program Counter Breakpoint and Mask Registers (Pbrn, PBMR)
  270
- Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1)
  271
- Data Breakpoint and Mask Registers (DBR/DBR1, DBMR/DBMR1)
  272
- PC Breakpoint ASID Register (PBASID)
  274
- Extended Trigger Definition Register (XTDR)
  275
- Resulting Set of Possible Trigger Combinations
  277
- Background Debug Mode (BDM)
  278
- CPU Halt
  278
- BDM Serial Interface
  280
- Receive Packet Format
  280
- Transmit Packet Format
  281
- BDM Command Set
  281
- Coldfire BDM Command Format
  283
- Command Sequence Diagrams
  283
- Command Set Descriptions
  285
- Real-Time Debug Support
  301
- Theory of Operation
  301
- Emulator Mode
  303
- Concurrent BDM and Processor Operation
  303
- Debug C Definition of PSTDDATA Outputs
  304
- User Instruction Set
  304
- Supervisor Instruction Set
  310
- Coldfire Debug History
  311
- Coldfire Debug Classic: the Original Definition
  311
- Coldfire Debug Revision B
  312
- Coldfire Debug Revision C
  312
- Debug Interrupts and Interrupt Requests (Emulator Mode)
  312
- Freescale-Recommended BDM Pinout
  313
- System Integration Unit
  315
Chapter 9 System Integration Unit (SIU)

317
- Introduction
  317
- Features
  317
- Memory Map/Register Definition
  317
- Module Base Address Register (MBAR)
  318
- System Breakpoint Control Register (SBCR)
  319
- SEC Sequential Access Control Register (SECSACR)
  320
- Reset Status Register (RSR)
  321
- JTAG Device Identification Number (JTAGID)
  321
Chapter 10 Internal Clocks and Bus Architecture

323
- Block Diagram
  323
- Introduction
  323
- Clocking Overview
  324
- Internal Bus Overview
  324
- XL Bus Features
  325
- Internal Bus Transaction Summaries
  325
- XL Bus Interface Operations
  325
- Basic Transfer Protocol
  325
- Address Pipelines
  326
- Pll
  327
- PLL Memory Map/Register Descriptions
  327
- System PLL Control Register (SPCR)
  327
- XL Bus Arbiter
  328
- Features
  328
- Arbiter Functional Description
  328
- Prioritization
  328
- Bus Grant Mechanism
  329
- Watchdog Functions
  330
- XLB Arbiter Register Descriptions
  330
- Arbiter Configuration Register (XARB_CFG)
  331
- Arbiter Version Register (XARB_VER)
  332
- Arbiter Status Register (XARB_SR)
  334
- Arbiter Address Capture Register (XARB_ADRCAP)
  335
- Arbiter Bus Signal Capture Register (XARB_SIGCAP)
  335
- Arbiter Address Tenure Time out Register (XARB_ADRTO)
  336
- Arbiter Data Tenure Time out Register (XARB_DATTO)
  337
- Arbiter Bus Activity Time out Register (XARB_BUSTO)
  338
- Arbiter Master Priority Enable Register (XARB_PRIEN)
  338
- Arbiter Master Priority Register (XARB_PRI)
  339
Chapter 11 General Purpose Timers (GPT)

341
- Introduction
  341
- Overview
  341
- Modes of Operation
  341
  - External Signals
    342
  - Memory Map/Register Definition
    342
- GPT Enable and Mode Select Register (Gmsn)
  343
- GPT Counter Input Register (Gcirn)
  345
- GPT PWM Configuration Register (Gpwmn)
  346
- GPT Status Register (Gsrn)
  347
- Functional Description
  348
- Timer Configuration Method
  348
- Programming Notes
  348
Chapter 12 Slice Timers (SLT)

349
- Introduction
  349
- Overview
  349
- Memory Map/Register Definition
  349
- SLT Terminal Count Register (Stcntn)
  350
- SLT Control Register (Scrn)
  350
- SLT Timer Count Register (Scntn)
  351
- SLT Status Register (Ssrn)
  352
Chapter 13 Interrupt Controller

353
Chapter 14

367
- Introduction
  367
- Interrupt/General-Purpose I/O Pin Descriptions
  367
- Memory Map/Register Definition
  368
- Memory Map
  368
- Register Descriptions
  368
- EPORT Pin Assignment Register (EPPAR)
  369
- EPORT Data Direction Register (EPDDR)
  369
- Edge Port Interrupt Enable Register (EPIER)
  370
- Edge Port Data Register (EPDR)
  370
- Edge Port Pin Data Register (EPPDR)
  371
- Edge Port Flag Register (EPFR)
  371
Chapter 15

373
Chapter 16 32-Kbyte System SRAM

409
- Introduction
  409
- Block Diagram
  409
- Features
  410
- Overview
  410
- Memory Map/Register Definition
  410
- System SRAM Configuration Register (SSCR)
  411
- Transfer Count Configuration Register (TCCR)
  412
- Transfer Count Configuration Register-DMA Read Channel (TCCRDR)
  413
- Transfer Count Configuration Register-DMA Write Channel (TCCRDW)
  414
- Transfer Count Configuration Register-SEC (TCCRSEC)
  415
- Functional Description
  416
- Introduction
  417
- Overview
  417
- Features
  417
- Modes of Operation
  417
Chapter 17 Byte Lanes

418
- Address Latch
  419
- External Signals
  419
- Chip-Select (FBCS[5:0])
  420
- Address/Data Bus (AD[31:0])
  420
- Address Latch Enable (ALE)
  420
- Read/Write (R/W)
  420
- Transfer Burst (TBST)
  420
- Transfer Size (TSIZ[1:0])
  420
- Byte Selects (BE/BWE[3:0])
  421
- Output Enable (OE)
  421
- Transfer Acknowledge (TA)
  421
- Chip-Select Operation
  422
- General Chip-Select Operation
  422
- 16-, and 32-Bit Port Sizing
  422
- Global Chip-Select Operation
  422
- Chip-Select Registers
  423
- Chip-Select Address Registers (CSAR0-CSAR5)
  424
- Chip-Select Mask Registers (CSMR0-CSMR5)
  425
- Chip-Select Control Registers (CSCR0-CSCR5)
  426
- Functional Description
  428
- Data Transfer Operation
  428
- Data Byte Alignment and Physical Connections
  428
- Address/Data Bus Multiplexing
  429
- Bus Cycle Execution
  429
- Data Transfer Cycle States
  430
- Flexbus Timing Examples
  431
- Basic Read Bus Cycle
  431
- Basic Write Bus Cycle
  432
- Bus Cycle Multiplexing
  433
- Timing Variations
  437
- Burst Cycles
  442
- Misaligned Operands
  447
- Bus Errors
  448
Chapter 18 SDRAM Controller (SDRAMC)

449
- Introduction
  449
- Overview
  449
- Features
  449
- Terminology
  449
- Block Diagram
  450
- External Signal Description
  450
- SDRAM Data Bus (SDDATA[31:0])
  450
- SDRAM Address Bus (SDADDR[12:0])
  450
- SDRAM Bank Addresses (SDBA[1:0])
  450
- SDRAM Row Address Strobe (RAS)
  451
- SDRAM Column Address Strobe (CAS)
  451
- SDRAM Chip Selects (SDCS[3:0])
  451
- SDRAM Write Data Byte Mask (SDDM[3:0])
  451
- SDRAM Data Strobe (SDDQS[3:0])
  451
- SDRAM Clock (SDCLK[1:0])
  451
- Inverted SDRAM Clock (SDCLK[1:0])
  451
- SDRAM Write Enable (SDWE)
  451
- SDRAM Clock Enable (SDCKE)
  452
- SDR SDRAM Data Strobe (SDRDQS)
  452
- SDRAM Memory Supply (SDVDD)
  452
- SDRAM Reference Voltage (VREF)
  452
- Interface Recommendations
  452
- Supported Memory Configurations
  452
- SDRAM SDR Connections
  454
- SDRAM DDR Component Connections
  454
- SDRAM DDR DIMM Connections
  455
- DDR SDRAM Layout Considerations
  456
  - Termination Example
    457
  - SDRAM Overview
    457
    
    SDRAM Commands
    457
- Row and Bank Active Command (ACTV)
  458
- Read Command (READ)
  458
- Write Command (WRITE)
  458
- Precharge All Banks Command (PALL)
  459
- Load Mode/Extended Mode Register Command (LMR, LEMR)
  459
- Auto Refresh Command (REF)
  461
- Self-Refresh (SREF) and Power-Down (PDWN) Commands
  461
- Power-Up Initialization
  461
- SDR Initialization
  462
- DDR Initialization
  462
- Functional Overview
  463
- Page Management
  463
- Transfer Size
  463
- Memory Map/Register Definition
  464
  - SDRAM Drive Strength Register (SDRAMDS)
    465
- SDRAM Chip Select Configuration Registers (Csncfg)
  466
- SDRAM Mode/Extended Mode Register (SDMR)
  467
- SDRAM Control Register (SDCR)
  468
- SDRAM Configuration Register 1 (SDCFG1)
  469
- SDRAM Configuration Register 2 (SDCFG2)
  471
- SDRAM Example
  472
- SDRAM Signal Drive Strength Settings
  473
- SDRAM Chip Select Settings
  473
- Set the Extended Mode Register
  477
- Set the Mode Register and Reset DLL
  477
- Issue a PALL Command
  478
- Perform Two Refresh Cycles
  479
- Clear the Reset DLL Bit in the Mode Register
  480
- Enable Automatic Refresh and Lock Mode Register
  481
- Initialization Code
  482
Chapter 19 PCI Bus Controller

485
- Introduction
  485
- Block Diagram
  485
- Overview
  485
- Features
  485
- External Signal Description
  486
- Address/Data Bus (PCIAD[31:0])
  486
- Command/Byte Enables (PCICXBE[3:0])
  486
- Device Select (PCIDEVSEL)
  487
- Frame (PCIFRAME)
  487
- Initialization Device Select (PCIIDSEL)
  487
- Initiator Ready (PCIIRDY)
  487
- Parity (PCIPAR)
  487
- PCI Clock (CLKIN)
  487
- Parity Error (PCIPERR)
  487
- Reset (PCIRESET)
  487
- System Error (PCISERR)
  487
- Stop (PCISTOP)
  487
  - Target Ready (PCITRDY)
    488
  - Memory Map/Register Definition
    488
- PCI Type 0 Configuration Registers
  490
- Device ID/Vendor ID Register (PCIIDR)-PCI Dword Addr 0
  491
- PCI Status/Command Register (PCISCR)-PCI Dword Addr 1
  491
- Revision ID/Class Code Register (PCICCRIR)-PCI Dword 3
  493
- Configuration 1 Register (PCICR1)-PCI Dword 3
  494
- Base Address Register 0 (PCIBAR0)-PCI Dword 4
  495
- Base Address Register 1 (PCIBAR1)—PCI Dword 5
  496
- Cardbus CIS Pointer Register PCICCPR-PCI Dword a
  496
- Subsystem ID/Subsystem Vendor ID Registers PCISID-PCI Dword B
  496
- Expansion ROM Base Address PCIERBAR-PCI Dword C
  497
- Capabilities Pointer (Cap_Ptr) PCICPR-PCI Dword D
  497
- Configuration 2 Register (PCICR2)-PCI Dword F
  497
- General Control/Status Registers
  497
- Global Status/Control Register (PCIGSCR)
  498
- Target Base Address Translation Register 0 (PCITBATR0)
  499
- Target Base Address Translation Register 1 (PCITBATR1)
  500
- Target Control Register (PCITCR)
  500
- Initiator Window 0 Base/Translation Address Register (PCIIW0BTAR)
  501
- Initiator Window 1 Base/Translation Address Register (PCIIW1BTAR)
  502
- Initiator Window 2 Base/Translation Address Register (PCIIW2BTAR)
  503
- Initiator Window Configuration Register (PCIIWCR)
  503
- Initiator Control Register (PCIICR)
  504
- Initiator Status Register (PCIISR)
  505
- Configuration Address Register (PCICAR)
  506
- Communication Subsystem Interface Registers
  507
- Comm Bus FIFO Transmit Interface
  507
- Comm Bus FIFO Receive Interface
  519
- Functional Description
  532
- PCI Bus Protocol
  532
- PCI Bus Background
  532
- Basic Transfer Control
  533
- PCI Transactions
  533
- PCI Bus Commands
  535
- Addressing
  536
- Initiator Arbitration
  539
- Priority Scheme
  540
- Configuration Interface
  540
- XL Bus Initiator Interface
  540
  - Endian Translation
    542
- Configuration Mechanism
  544
- Interrupt Acknowledge Transactions
  546
- Special Cycle Transactions
  546
- Transaction Termination
  547
- XL Bus Target Interface
  547
- Reads from Local Memory
  548
- Local Memory Writes
  548
- Data Translation
  548
- Target Abort
  550
- Latrule Disable
  550
- Communication Subsystem Initiator Interface
  550
- Access Width
  551
- Addressing
  551
- Data Translation
  552
- Initialization
  552
- Restart and Reset
  552
- PCI Commands
  553
- FIFO Considerations
  553
- Alarms
  553
- Bus Errors
  554
- PCI Clock Scheme
  554
- Interrupts
  554
- PCI Bus Interrupts
  554
- Internal Interrupt
  554
- Application Information
  554
- XL Bus-Initiated Transaction Mapping
  554
- Address Maps
  555
- Address Translation
  556
- Base Address Register Overview
  558
- XL Bus Arbitration Priority
  559
Chapter 20 PCI Bus Arbiter Module

561
- Introduction
  561
- Block Diagram
  561
- Overview
  561
- Features
  562
- External Signal Description
  562
- Frame (PCIFRM)
  562
- Initiator Ready (PCIIRDY)
  562
- PCI Clock (CLKIN)
  562
- External Bus Grant (PCIBG[4:1])
  562
- External Bus Grant/Request Output (PCIBG0/PCIREQOUT)
  563
- External Bus Request (PCIBR[4:1])
  563
- External Request/Grant Input (PCIBR0/PCIGNTIN)
  563
- Register Definition
  563
- PCI Arbiter Control Register (PACR)
  563
- PCI Arbiter Status Register (PASR)
  565
- Functional Description
  565
- External PCI Requests
  565
- Arbitration
  566
- Hidden Bus Arbitration
  566
- Arbitration Scheme
  566
- Arbitration Latency
  567
- Arbitration Examples
  567
- Master Time-Out
  569
- Reset
  570
- Interrupts
  570
Chapter 21

571
- Introduction
  571
- Block Diagram
  571
- The CAN System
  572
- Features
  573
- Modes of Operation
  573
- Normal Mode
  573
- Freeze Mode
  573
- Module Disabled Mode
  574
- Loop-Back Mode
  574
- Listen-Only Mode
  574
- External Signals
  575
- Cantx[1:0]
  575
- Canrx[1:0]
  575
- Memory Map/Register Definition
  575
- Flexcan Memory Map
  575
- Register Descriptions
  576
- Flexcan Module Configuration Register (CANMCR)
  576
- Flexcan Control Register (CANCTRL)
  578
- Flexcan Timer Register (TIMER)
  580
- Rx Mask Registers
  581
- Flexcan Error Counter Register (ERRCNT)
  584
- Flexcan Error and Status Register (ERRSTAT)
  585
- Interrupt Mask Register (IMASK)
  587
- Interrupt Flag Register (IFLAG)
  588
- Functional Overview
  589
- Message Buffer Structure
  589
- Message Buffer Memory Map
  592
- Transmit Process
  593
- Arbitration Process
  594
- Receive Process
  594
- Self-Received Frames
  595
- Message Buffer Handling
  595
- Serial Message Buffers (Smbs)
  596
- Transmit Message Buffer Deactivation
  596
- Receive Message Buffer Deactivation
  596
- Locking and Releasing Message Buffers
  597
- CAN Protocol Related Frames
  597
- Remote Frames
  597
- Overload Frames
  598
- Time Stamp
  598
- Bit Timing
  598
- Configuring the Flexcan Bit Timing
  599
- Flexcan Error Counters
  600
- Flexcan Initialization Sequence
  601
- Interrupts
  601
Chapter 22 Integrated Security Engine (SEC)

603
- Features
  603
- Coldfire Security Architecture
  603
- Block Diagram
  604
- Overview
  604
- Bus Interface
  604
- SEC Controller Unit
  605
- Static EU Access
  605
- Dynamic EU Access
  605
- Crypto-Channels
  605
- Execution Units (Eus)
  606
- Data Encryption Standard Execution Unit (DEU)
  606
- Arc Four Execution Unit (AFEU)
  607
- Advanced Encryption Standard Execution Unit (AESU)
  608
- Message Digest Execution Unit (MDEU)
  608
- Random Number Generator (RNG)
  610
- Memory Map/Register Definition
  610
- Controller
  610
- EU Access
  613
- Multiple EU Assignment
  613
- Multiple Channels
  613
- Controller Registers
  613
- EU Assignment Control Registers (EUACRH and EUACRL)
  613
- EU Assignment Status Registers (EUASRH and EUASRL)
  615
- SEC Interrupt Mask Registers (SIMRH and SIMRL)
  616
- SEC Interrupt Status Registers (SISRH and SISRL)
  616
- SEC Interrupt Control Registers (SICRH and SICRL)
  616
- SEC ID Register (SIDR)
  618
- SEC Master Control Register (SMCR)
  619
- Master Error Address Register (MEAR)
  620
- Channels
  620
- Crypto-Channel Registers
  621
- Crypto-Channel Configuration Registers (Cccrn)
  621
- Crypto-Channel Pointer Status Registers (Ccpsrhn and Ccpsrln)
  623
- Crypto-Channel Current Descriptor Pointer Register (Cdprn)
  629
- Fetch Register (Frn)
  629
- Data Packet Descriptor Buffer (Cdbufn)
  630
- ARC Four Execution Unit (AFEU)
  630
- AFEU Register Map
  630
- AFEU Reset Control Register (AFRCR)
  630
- AFEU Status Register (AFSR)
  631
- AFEU Interrupt Status Register (AFISR)
  633
- AFEU Interrupt Mask Register (AFIMR)
  634
- Data Encryption Standard Execution Units (DEU)
  636
- DEU Register Map
  636
- DEU Reset Control Register (DRCR)
  636
- DEU Status Register (DSR)
  637
- DEU Interrupt Status Register (DISR)
  639
- DEU Interrupt Mask Register (DIMR)
  641
- Message Digest Execution Unit (MDEU)
  642
- MDEU Register Map
  642
- MDEU Reset Control Register (MDRCR)
  643
- MDEU Status Register (MDSR)
  643
- MDEU Interrupt Status Register (MDISR)
  645
- MDEU Interrupt Mask Register (MDIMR)
  646
- RNG Execution Unit (RNG)
  648
- RNG Register Map
  648
- RNG Reset Control Register (RNGRCR)
  648
- RNG Status Register (RNGSR)
  649
- RNG Interrupt Status Register (RNGISR)
  650
- RNG Interrupt Mask Register (RNGIMR)
  651
- Advanced Encryption Standard Execution Units (AESU)
  652
- AESU Register Map
  652
- AESU Reset Control Register (AESRCR)
  652
- AESU Status Register (AESSR)
  653
- AESU Interrupt Status Register (AESISR)
  655
- AESU Interrupt Mask Register (AESIMR)
  656
- Descriptors
  658
- Descriptor Structure
  658
- Descriptor Header
  659
  - Descriptor Length and Pointer Fields
    662
  - Null Fields
    663
  - Next Descriptor Pointer
    663
  - Descriptor Chaining
    663
  - Descriptor Type Formats
    664
  - Descriptor Classes
    666
    
    Dynamic Descriptors
    666
    
    Static Descriptors
    667
  - EU Specific Data Packet Descriptors
    669
  - AFEU Mode Options and Data Packet Descriptors
    669
    
    Dynamically Assigned AFEU
    670
    
    Statically Assigned AFEU
    671
  - DEU Mode Options and Data Packet Descriptors
    674
    
    Dynamically Assigned DEU
    675
    
    Statically Assigned DEU
    676
  - MDEU Mode Options and Data Packet Descriptors
    679
    
    Recommended Settings for MDEU Mode Register
    680
    
    Dynamically Assigned MDEU
    680
    
    Statically Assigned MDEU
    681
  - RNG Data Packet Descriptors
    684
  - AESU Mode Options and Data Packet Descriptors
    685
    
    Dynamically Assigned AESU
    686
    
    Statically Assigned AESU
    687
    
    AESU-CCM Mode Descriptor
    690
  - Multi-Function Data Packet Descriptors
    692
    
    Snooping
    693
    
    Dynamic Multi-Function Descriptor Formats
    693
    
    Static Multi-Function Descriptor Formats
    697
    
    Sslv3.1/Tls 1.0 Processing Descriptors
    704
Chapter 23 IEEE 1149.1 Test Access Port (JTAG)

709
- Introduction
  709
  - Block Diagram
    709
  - Features
    710
  - Modes of Operation
    710
- External Signal Description
  710
  - Detailed Signal Description
    710
    
    Test Mode 0 (MTMOD0)
    710
    
    Test Clock Input (TCK)
    711
- Test Mode Select/Breakpoint (TMS/BKPT)
  711
- Test Data Input/Development Serial Input (TDI/DSI)
  711
- Test Reset/Development Serial Clock (TRST/DSCLK)
  712
- Test Data Output/Development Serial Output (TDO/DSO)
  712
- Memory Map/Register Definition
  712
- Memory Map
  712
- Register Descriptions
  712
- Instruction Shift Register (IR)
  712
- IDCODE Register
  712
- Bypass Register
  713
- JTAG_CFM_CLKDIV Register
  713
- TEST_CTRL Register
  713
- Boundary Scan Register
  714
- Functional Description
  714
- JTAG Module
  714
- TAP Controller
  714
- JTAG Instructions
  715
- External Test Instruction (EXTEST)
  716
- IDCODE Instruction
  716
- SAMPLE/PRELOAD Instruction
  716
- ENABLE_TEST_CTRL Instruction
  717
- HIGHZ Instruction
  717
- CLAMP Instruction
  717
- BYPASS Instruction
  717
- Initialization/Application Information
  717
- Restrictions
  717
- Nonscan Chain Operation
  717
Chapter 24 Multichannel DMA

721
- Introduction
  721
- Block Diagram
  721
- Overview
  722
- Master DMA Engine (MDE)
  722
- Address and Data Sequencer (ADS)
  722
- Priority-Task Decoder (PTD)
  722
- Logic Unit with Redundancy Check (LURC)
  722
- Debug Unit
  722
- Features
  722
- External Signals
  723
- Dreq[1:0]
  723
- Dack[1:0]
  723
- Memory Map/Register Definitions
  723
- DMA Task Memory
  723
- Task Table
  723
- Task Descriptor Table
  723
- Variable Table
  724
- Function Descriptor Table
  724
- Context Save Space
  724
- Memory Structure
  724
- DMA Registers
  725
- DMA Register Map
  725
- Task Base Address Register (Taskbar)
  726
- Current Pointer (CP)
  727
- End Pointer (EP)
  728
- Variable Pointer (VP)
  728
- PTD Control (PTD)
  729
- DMA Interrupt Pending (DIPR)
  730
- DMA Interrupt Mask Register (DIMR)
  730
- Task Control Registers (Tcrn)
  731
- Priority Registers (Priorn)
  732
- Initiator Mux Control Register (IMCR)
  733
- Task Size Registers (TSKSZ[0:1])
  734
- Debug Comparator Registers (Dbgcompn)
  736
- Debug Control (DBGCTL)
  736
- Debug Status (DBGSTAT)
  738
- PTD Debug Registers
  739
- External Request Module Registers
  740
- External Request Module Register Map
  740
- External Request Base Address Register (EREQBAR)
  740
- External Request Address Mask Register (EREQMASK)
  741
- External Request Control Register (EREQCTRL)
  741
- Functional Description
  742
- Tasks
  742
- Descriptors
  743
- Task Initialization
  743
- Initiators
  743
- Prioritization
  744
- Context Switch
  744
- Data Movement
  744
- Data Manipulation
  744
- LURC Features
  745
- Line Buffers
  746
- Combine Write Enable
  746
- Read Line Enable
  746
- Speculative Prefetch
  746
- Termination of Loop
  747
- Interrupts
  747
- Debug Unit
  747
- Programming Model
  747
- Register Initialization
  747
- Task Memory
  748
- Task Table
  748
- Timing Diagrams
  750
- Level-Triggered Requests
  750
- Edge-Triggered Requests
  750
- Pipelined Requests
  751
Chapter 25 Comm Timer Module (CTM)

753
- Introduction
  753
- Block Diagrams
  753
- Overview
  754
- Comm Timer External Clock[7:0]
  755
- Memory Map/Register Definition
  755
- Timer Module Register Map
  755
- Register Descriptions
  756
- Comm Timer Configuration Register (Ctcrn)-Fixed Timer Channel
  756
- Comm Timer Configuration Register (Ctcrn)-Variable Timer Channel
  757
- Functional Description
  759
- Variable Timer in Baud Clock Generator Mode
  759
- Fixed Timer in Initiator Mode
  759
- Fixed Timer in Initiator Mode Example
  759
- Variable Timer in Initiator Mode
  760
- Variable Timer in Initiator Mode Example
  760
Chapter 26 Programmable Serial Controller (PSC)

763
- Introduction
  763
- Block Diagram
  763
- Overview
  763
- Features
  763
- Modes of Operation
  763
- Signal Description
  764
- Pscncts/Pscbclk
  764
- Pscnrts/Pscfsync
  764
- Pscnrxd
  764
- Pscntxd
  765
- Signal Properties in each Mode
  765
- Memory Map/Register Definition
  765
- Overview
  765
- Module Memory Map
  765
- Register Descriptions
  767
- Mode Register 1(Pscmr1N)
  767
- Mode Register 2 (Pscmr2N)
  768
- Status Register (Pscsrn)
  770
- Clock Select Register (Psccsrn)
  772
- Command Register (Psccrn)
  773
- Receiver Buffer (Pscrbn) and Transmitter Buffer (Psctbn)
  776
- Input Port Change Register (Pscipcrn)
  779
- Auxiliary Control Register (Pscacrn)
  780
- Interrupt Status Register (Pscisrn)
  780
- Interrupt Mask Register (Pscimrn)
  781
- Counter Timer Registers (Psccturn, Pscctlrn)
  783
- Input Port (Pscipn)
  783
- Output Port Bit Set (Pscopsetn)
  784
- Output Port Bit Reset (Pscopresetn)
  784
- Psc/Irda Control Register (Pscsicrn)
  785
- Infrared Control Register 1 (Pscircr1N)
  786
- Infrared Control Register 2 (Pscircr2N)
  786
- Infrared SIR Divide Register (Pscirsdrn)
  787
- Infrared mir Divide Register (Pscirmdrn)
  787
- Infrared FIR Divide Register (Pscirfdrn)
  788
- Rx and Tx FIFO Counter Register (Pscrfcntn, Psctfcntn)
  789
- Rx and Tx FIFO Data Register (Pscrfdrn, Psctfdrn)
  789
- Rx and Tx FIFO Status Register (Pscrfsrn, Psctfsrn)
  790
- Rx and Tx FIFO Control Register (Pscrfcrn, Psctfcrn)
  792
- Rx and Tx FIFO Alarm Register (Pscrfarn, Psctfarn)
  794
- Rx and Tx FIFO Read Pointer (Pscrfrpn, Psctfrpn)
  794
- Rx and Tx FIFO Write Pointer (Pscrfwpn, Psctfwpn)
  795
- Rx and Tx FIFO Last Read Frame Pointer (Pscrlrfpn, Psctlrfpn)
  795
- Rx and Tx FIFO Last Write Frame Pointer (Pscrlwfpn, Psctlwfpn)
  796
- Functional Description
  797
- UART Mode
  797
- Multidrop Mode
  798
- Modem8 Mode
  799
- Modem16 Mode
  800
- AC97 Mode
  801
- Transmitter
  802
  - Receiver
    802
- Low Power Mode
  802
- SIR Mode
  803
- MIR Mode
  803
- Data Format
  803
- Serial Interaction Pulse (SIP)
  804
- FIR Mode
  804
- Data Format
  804
- PSC FIFO System
  805
- Rx Fifo
  806
  - Tx Fifo
    807
- Looping Modes
  808
- Automatic Echo Mode
  808
- Local Loopback Mode
  808
- Remote Loopback Mode
  809
- Resets
  809
- General
  809
- Description of Reset Operation
  809
- Reset
  809
  - Crsrx
    809
  - Crstx
    809
- Crses
  809
- Interrupts
  810
- Description of Interrupt Operation
  810
- Processor Interrupt
  810
- Software Environment
  810
- Configuration
  811
- UART Mode
  811
- Modem8 Mode
  812
- Modem16 Mode
  813
- AC97 Mode
  813
- SIR Mode
  814
- MIR Mode
  815
- FIR Mode
  816
- Programming
  817
- MIR Mode
  817
- FIR Mode
  818
Chapter 27 DMA Serial Peripheral Interface (DSPI)

819
- Overview
  819
- Features
  819
- Block Diagram
  820
- Modes of Operation
  820
- Master Mode
  820
- Slave Mode
  820
- Signal Description
  821
- Overview
  821
- Detailed Signal Descriptions
  821
- DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS)
  821
- DSPI Peripheral Chip Selects 2-3 (DSPICS[2:3])
  821
- DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe (DSPICS5/PCSS)
  821
- DSPI Serial Input (DSPISIN)
  822
- DSPI Serial Output (DSPISOUT)
  822
- DSPI Serial Clock (DSPISCK)
  822
- Memory Map and Registers
  822
- DSPI Module Configuration Register (DMCR)
  823
- DSPI Transfer Count Register (DTCR)
  825
- DSPI Clock and Transfer Attributes Registers 0-7 (Dctarn)
  825
- DSPI Status Register (DSR)
  829
- DSPI Dma/Interrupt Request Select Register (DIRSR)
  831
- DSPI Tx FIFO Register (DTFR)
  833
- DSPI Rx FIFO Register (DRFR)
  834
- DSPI Tx FIFO Debug Registers 0-3 (Dtfdrn)
  835
- DSPI Rx FIFO Debug Registers 0-3 (Drfdrn)
  835
- Functional Description
  836
- Functional Description
  837
- Start and Stop of DSPI Transfers
  837
- Serial Peripheral Interface (SPI)
  838
- Master Mode
  838
- Slave Mode
  838
- FIFO Disable Operation
  839
- Tx FIFO Buffering Mechanism
  839
- Rx FIFO Buffering Mechanism
  840
- DSPI Baud Rate and Clock Delay Generation
  840
- Baud Rate Generator
  841
- CS to SCK Delay (Tcsc)
  841
- After DSPISCK Delay (Tasc)
  841
  - Delay after Transfer (T Peripheral Chip Select Strobe Enable (PCSS)
    841
- Transfer Formats
  843
- Classic SPI Transfer Format (CPHA = 0)
  843
- Classic SPI Transfer Format (CPHA = 1)
  844
- Modified SPI Transfer Format (MTFE = 1, CPHA = 0)
  845
- Modified SPI Transfer Format (MTFE = 1, CPHA = 1)
  846
- Continuous Selection Format
  847
- Continuous Serial Communications Clock
  848
- Interrupts/Dma Requests
  849
- End of Queue Interrupt Request
  850
- Transmit FIFO Fill Interrupt or DMA Request
  850
- Transfer Complete Interrupt Request
  850
- Transmit FIFO Underflow Interrupt Request
  850
- Receive FIFO Drain Interrupt or DMA Request
  850
- Receive FIFO Overflow Interrupt Request
  850
- Initialization and Application Information
  851
- How to Change Queues
  851
- Baud Rate Settings
  851
- Delay Settings
  852
- Calculation of FIFO Pointer Addresses
  853
- Address Calculation for the First-In Entry and Last-In Entry in the Tx FIFO
  854
- Address Calculation for the First-In Entry and Last-In Entry in the Rx FIFO
  854
Chapter 28

855
- Introduction
  855
- Block Diagram
  855
- I2C Overview
  856
- Features
  856
- External Signals
  856
- Memory Map/Register Definition
  857
- I2C Register Map
  857
- Register Descriptions
  857
  - C Address Register (I2ADR)
    857
  - C Frequency Divider Register (I2FDR)
    858
  - C Control Register (I2CR)
    859
  - C Status Register (I2SR)
    859
  - C Data I/O Register (I2DR)
    861
  - C Interrupt Control Register (I2ICR)
    861
  - Functional Description
    862
- Functional Description
  863
- START Signal
  863
- Slave Address Transmission
  863
- STOP Signal
  863
- Data Transfer
  863
- Acknowledge
  864
- Repeated Start
  865
- Clock Synchronization and Arbitration
  865
- Handshaking and Clock Stretching
  866
- Initialization Sequence
  866
- Transfer Initiation and Interrupt
  867
- Post-Transfer Software Response
  868
- Generation of STOP
  869
- Generation of Repeated START
  870
- Slave Mode
  870
- Arbitration Lost
  872
- Flow Control
  872
Chapter 29 USB 2.0 Device Controller

875
- Introduction
  875
- Overview
  875
- Features
  875
- Block Diagram
  876
- Controller and Synchronization
  876
- Descriptor RAM
  876
- FIFO Controller
  877
- FIFO RAM Manager
  877
- Integrated USB 2.0 Transceiver
  877
- Memory Map/Register Definition
  878
- USB Memory Map
  878
- USB Request, Control, and Status Registers
  883
- USB Status Register (USBSR)
  883
- USB Control Register (USBCR)
  884
- USB Descriptor RAM Control Register (DRAMCR)
  886
- USB Descriptor RAM Data Register (DRAMDR)
  887
- USB Interrupt Status Register (USBISR)
  888
- USB Interrupt Mask Register (USBIMR)
  889
- USB Application Interrupt Status Register (USBAISR)
  890
- USB Application Interrupt Mask Register (USBAIMR)
  891
- Endpoint Info Register (EPINFO)
  892
- USB Configuration Value Register (CFGR)
  893
- USB Configuration Attribute Register (CFGAR)
  893
- USB Device Speed Register (SPEEDR)
  894
- USB Frame Number Register (FRMNUMR)
  895
- USB Endpoint Transaction Number Register (EPTNR)
  895
- USB Application Interface Update Register (IFUR)
  896
- USB Configuration Interface Register (Ifrn)
  896
- USB Counter Registers
  897
- USB Packet Passed Count Register (PPCNT)
  897
- USB Dropped Packet Counter Register (DPCNT)
  898
- USB CRC Error Counter Register (CRCECNT)
  898
- USB Bitstuffing Error Counter Register (BSECNT)
  898
- USB PID Error Counter Register (PIDECNT)
  899
- USB Framing Error Counter Register (FRMECNT)
  899
- USB Transmitted Packet Counter Register (TXPCNT)
  900
- USB Counter Overflow Register (CNTOVR)
  900
- Endpoint Context Registers
  901
- Endpoint N Attribute Control Register (EP0ACR, Epnoutacr, Epninacr)
  901
- Endpoint N Max Packet Size Register (EP0MPSR, Epnoutmpsr, Epninmpsr)
  902
- Endpoint N Interface Number Register (EP0IFR, Epnoutifr, Epninifr)
  903
- Endpoint N Status Register (EP0SR, Epnoutsr, Epninsr)
  904
- Bmrequest Type Register (BMRTR)
  905
- Brequest Type Register (BRTR)
  906
- Wvalue Register (WVALUER)
  906
- Windex Register (WINDEXR)
  907
- Wlength Register (WLENGTHR)
  907
- Endpoint N Sync Frame Register (Epnoutsfr, Epninsfr)
  907
- USB Endpoint FIFO Registers
  908
- USB Endpoint N Status and Control Register (Epnstat)
  908
- USB Endpoint N Interrupt Status Register (Epnisr)
  909
- USB Endpoint N Interrupt Mask Register (Epnimr)
  911
- USB Endpoint N FIFO RAM Configuration Register (Epnfrcfgr)
  912
- USB Endpoint N FIFO Data Register (Epnfdr)
  913
- USB Endpoint N FIFO Status Register (Epnfsr)
  914
- USB Endpoint N FIFO Control Register (Epnfcr)
  916
- USB Endpoint N FIFO Alarm Register (Epnfar)
  918
- USB Endpoint N FIFO Read Pointer (Epnfrp)
  919
- USB Endpoint N FIFO Write Pointer (Epnfwp)
  919
- USB Endpoint N Last Read Frame Pointer (Epnlrfp)
  920
- USB Endpoint N Last Write Frame Pointer (Epnlwfp)
  921
- Functional Description
  921
- Interrupts
  921
- Software Interface
  921
- Device Initialization
  921
- USB Descriptor Download
  922
- USB Interrupt Register
  923
- Endpoint Registers
  923
- FIFO Sizes
  924
- Enable the Device
  924
- Exception Handling
  924
- Unable to Fill or Empty FIFO Due to Temporary Problem
  924
- Catastrophic Error
  924
- Data Transfer Operations
  924
- USB Packets
  925
- Sending Packets
  925
- Receiving Packets
  925
- USB Transfers
  926
- Control Transfers
  927
- Bulk Traffic
  928
- Interrupt Traffic
  928
- Isochronous Operations
  929
Chapter 30 Fast Ethernet Controller (FEC)

931
- Introduction
  931
- Mcf548X Family Products
  931
- Block Diagram
  931
- Overview
  932
- Features
  933
- Modes of Operation
  933
- Full and Half Duplex Operation
  933
- Interface Options
  933
- Address Recognition Options
  934
- Internal Loopback
  934
- External Signals
  934
- Transmit Clock (Entxclk)
  934
- Receive Clock (Enrxclk)
  934
- Transmit Enable (Entxen)
  934
- Transmit Data[3:0] (Entxd[3:0])
  934
- Transmit Error (Entxer)
  935
- Receive Data Valid (Enrxdv)
  935
- Receive Data[3:0] (Enrxd[3:0])
  935
- Receive Error (Enrxer)
  935
- Carrier Sense (Encrs)
  935
- Collision (Encol)
  935
- Management Data Clock (Enmdc)
  935
- Management Data (Enmdio)
  935
- Memory Map/Register Definition
  936
- Top Level Module Memory Map
  936
- Detailed Memory Map (Control/Status Registers)
  937
- MIB Block Counters Memory Map
  938
- Ethernet Interrupt Event Register (EIR)
  940
- Interrupt Mask Register (EIMR)
  942
- Ethernet Control Register (ECR)
  943
- MII Management Frame Register (MMFR)
  944
- MII Speed Control Register (MSCR)
  945
- MIB Control Register (MIBC)
  947
- Receive Control Register (RCR)
  947
- Receive Hash Register (RHR)
  948
- Transmit Control Register (TCR)
  949
- Physical Address Low Register (PALR)
  950
- Physical Address High Register (PAHR)
  951
- Opcode/Pause Duration Register (OPD)
  952
- Individual Address Upper Register (IAUR)
  952
- Individual Address Lower Register (IALR)
  953
- Group Address Upper Register (GAUR)
  954
- Group Address Lower Register (GALR)
  954
- FEC Transmit FIFO Watermark Register (FECTFWR)
  955
- FEC Receive FIFO Data Register (FECRFDR)
  956
- FEC Receive FIFO Status Register (FECRFSR)
  956
- FEC Receive FIFO Control Register (FECRFCR)
  958
- FEC Receive FIFO Last Read Frame Pointer Register (FECRLRFP)
  960
- FEC Receive FIFO Last Write Frame Pointer Register (FECRLWFP)
  960
- FEC Receive FIFO Alarm Register (FECRFAR)
  961
- FEC Receive FIFO Read Pointer Register (FECRFRP)
  962
- FEC Receive FIFO Write Pointer Register (FECRFWP)
  963
- FEC Transmit FIFO Data Register (FECTFDR)
  963
- FEC Transmit FIFO Status Register (FECTFSR)
  964
- FEC Transmit FIFO Control Register (FECTFCR)
  966
- FEC Transmit FIFO Last Read Frame Pointer Register (FECTLRFP)
  967
- FEC Transmit FIFO Last Write Frame Pointer Register (FECTLWFP)
  968
- FEC Transmit FIFO Alarm Register (FECTFAR)
  969
- FEC Transmit FIFO Read Pointer Register (FECTFRP)
  970
- FEC Transmit FIFO Write Pointer Register (FECTFWP)
  970
- FEC FIFO Reset Register (FECFRST)
  971
- FEC CRC and Transmit Frame Control Word Register (FECCTCWR)
  972
- Functional Description
  973
- Initialization Sequence
  973
- Hardware Controlled Initialization
  973
- User Initialization (Prior to Asserting ECR[ETHER_EN])
  973
- Frame Control/Status Words
  974
- Receive Frame Status Word (RFSW)
  974
- Transmit Frame Control Word (TFCW)
  975
- Network Interface Options
  976
- FEC Frame Transmission
  976
- FEC Frame Reception
  977
- Ethernet Address Recognition
  978
- Hash Algorithm
  979
- Full Duplex Flow Control
  982
- Inter-Packet Gap (IPG) Time
  983
- Collision Handling
  983
- Internal and External Loopback
  983
- Ethernet Error-Handling Procedure
  984
- Transmission Errors
  984
- Reception Errors
  985
- MII Data Frame
  985
- MII Management Frame Structure
  986
Chapter 31 Mechanical Data

991
- Package
  991
- Pinout
  991
- Mechanical Diagrams
  998
- MCF5485/5484 Mechanical Diagram
  998
- MCF5483/5482 Mechanical Diagram
  1002
- MCF5481/5480 Mechanical Diagram
  1006
- Mechanicals 388-Pin PBGA Package Outline
  1010
- Case Drawing
  1010

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Freescale Semiconductor MCF5482 Manuals

Freescale Semiconductor MCF5482 Reference Manual (1032 pages)

Table of Contents

Chapter 1 Overview

Chapter 2 Signal Descriptions

Chapter 3

Chapter 4 Enhanced Multiply-Accumulate Unit (EMAC)

Chapter 5 Memory Management Unit (MMU)

Chapter 6 Floating-Point Unit (FPU)

Chapter 7 Local Memory

Chapter 8 Debug Support

Chapter 9 System Integration Unit (SIU)

Chapter 10 Internal Clocks and Bus Architecture

Chapter 11 General Purpose Timers (GPT)

Chapter 12 Slice Timers (SLT)

Chapter 13 Interrupt Controller

Chapter 14

Chapter 15

Chapter 16 32-Kbyte System SRAM

Chapter 17 Byte Lanes

Chapter 18 SDRAM Controller (SDRAMC)

Chapter 19 PCI Bus Controller

Chapter 20 PCI Bus Arbiter Module

Chapter 21

Chapter 22 Integrated Security Engine (SEC)

Chapter 23 IEEE 1149.1 Test Access Port (JTAG)

Chapter 24 Multichannel DMA

Chapter 25 Comm Timer Module (CTM)

Chapter 26 Programmable Serial Controller (PSC)

Chapter 27 DMA Serial Peripheral Interface (DSPI)

Chapter 28

Chapter 29 USB 2.0 Device Controller

Chapter 30 Fast Ethernet Controller (FEC)

Chapter 31 Mechanical Data

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