Shared Debug Resources - Freescale Semiconductor MCF5329 Reference Manual

Debug Module
DRc[4–0]
0x00 Configuration/status register (CSR)
0x05 BDM address attribute register (BAAR)
0x06 Address attribute trigger register (AATR)
0x07 Trigger definition register (TDR)
0x08 PC breakpoint register 0 (PBR0)
0x09 PC breakpoint mask register (PBMR)
0x0C Address breakpoint high register (ABHR)
0x0D Address breakpoint low register (ABLR)
0x0E Data breakpoint register (DBR)
0x0F Data breakpoint mask register (DBMR)
0x18 PC breakpoint register 1 (PBR1)
0x1A PC breakpoint register 2 (PBR2)
0x1B PC breakpoint register 3 (PBR3)
1
Each debug register is accessed as a 32-bit register; reserved fields are not used (don't care).
Debug control registers can be written by the external development system
or the CPU through the WDEBUG instruction. These control registers are
write-only from the programming model and they can be written through the
BDM port using the
configuration/status register (CSR) can be read through the BDM port using
the
RDMREG
The ColdFire debug architecture supports a number of hardware breakpoint registers, that can be
configured into single- or double-level triggers based on the PC or operand address ranges with an optional
inclusion of specific data values.
36.3.1

Shared Debug Resources

The debug module revision A implementation provides a common hardware structure for BDM and
breakpoint functionality. Certain hardware structures are used for BDM and breakpoint purposes as shown
in Table 36-4.
36-4
Table 36-3. Debug Module Memory Map
Register Name
NOTE
command. In addition, the
WDMREG
command.
MCF5329 Reference Manual, Rev 3
Width
Access Reset Value
(bits)
32 R/W 0x0098_0000
See Note
1
32 W 0x05
1
32 W 0x0005
32 W 0x0000_0000
32 W Undefined
32 W Undefined
32 W Undefined
32 W Undefined
32 W Undefined
32 W Undefined
32 W See Section
32 W See Section
32 W See Section
Freescale Semiconductor
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