Options For Embedded Floating-Point Apu Implementations; Unimplemented Sprs And Read-Only Sprs - Freescale Semiconductor e200z3 Reference Manual

Instruction Model
Table 3-8. Vector and Scalar SPFP APU Floating-Point Instructions (continued)
Floating-Point Negate
Floating-Point Negative Absolute Value
Floating-Point Subtract
Floating-Point Test Equal
Floating-Point Test Greater Than
Floating-Point Test Less Than
3.10.6.1

Options for Embedded Floating-Point APU Implementations

Table 3-9 lists implementation options allowed by the embedded floating-point architecture and describes
how the e200z3 handles those options.
Overflow and underflow conditions may be signaled by doing exponent evaluation of the operation.
If an examining of the exponents determines that an overflow or underflow could occur, the
implementation may choose to signal an overflow or underflow.
If an operand for a calculation or conversion is denormalized, the implementation may choose to
use a same-signed zero value in place of the denormalized operand.
+Infinity and -Infinity rounding modes are not required to be handled by an implementation. If an
implementation does not support ±Infinity rounding modes and the rounding mode is set to be
+Infinity or -Infinity, an embedded floating-point round interrupt occurs after every floating-point
instruction for which rounding may occur, regardless of the value of FINXE, unless an embedded
floating-point data interrupt also occurs and is taken.
For absolute value, negate, and negative absolute value operations, an implementation may
choose either to simply perform the sign bit operation recognizing interrupts or to compute the
operation and handle exceptions and saturation where appropriate.
SPEFSCR FGH and FXH bits are undefined upon the completion of a scalar floating-point
operation. An implementation may choose to clear them or leave them unchanged.
An implementation may choose to only implement sticky bit setting by hardware for FDBZS and
FINXS, allowing software to manage the other sticky bits. It is recommended that all future
implementations implement all sticky bit settings in hardware.
3.11

Unimplemented SPRs and Read-Only SPRs

The e200z3 fully decodes the SPR field of mfspr and mtspr instructions. If the SPR specified is undefined
and not privileged, an illegal instruction exception is generated. If the SPR specified is undefined and
privileged and the CPU is in user mode (MSR[PR] = 1), a privileged instruction exception is generated. If
3-16
Instruction
Table 3-9. Embedded Floating-Point APU Options
Option
e200z3 Power Architecture Core Reference Manual, Rev. 2
Mnemonic
Syntax
Scalar Vector
efsneg evfsneg rD,rA
efsnabs evfsnabs rD,rA
efssub evfssub rD,rA,rB
efststeq evfststeq crD,rA,rB
efststgt evfststgt crD,rA,rB
efststlt evfststlt crD,rA,rB
e200z3 Implementation
Follows the
recommendation; does not
use the estimation.
Uses a same-signed zero
value in place of the
denormalized operand.
Supports rounding to
±Infinity.
A sign bit operation is
performed; interrupts are
taken.
Always clears these bits for
such operations.
Implements all sticky bit
settings in hardware.
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