Freescale Semiconductor PowerPC MPC823 Reference Manual

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Freescale Semiconductor, Inc.

PowerPC

MPC823

™

Reference Manual

The Microprocessor for Mobile Computing

Revision 1

For More Information On This Product,

Go to: www.freescale.com

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Page 1 Freescale Semiconductor, Inc. PowerPC MPC823 ™ Reference Manual The Microprocessor for Mobile Computing © 2000 Motorola, Inc. All Rights Reserved. Revision 1 For More Information On This Product, Go to: www.freescale.com...
Page 2 Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer...
Page 3: Table Of Contents
Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Page Number Title Number Section 1 Introduction Features ....................1-1 Architecture ...................1-6 1.2.1 The Embedded PowerPC Core ..........1-8 1.2.2 The System Interface Unit ............1-8 1.2.3 The Communication Processor Module ........1-9 1.2.4 The Video/LCD Controller ............1-10 1.2.4.1...
Page 4 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 4.1.4 External Soft Reset ..............4-4 4.1.5 Internal Soft Reset ..............4-4 4.1.5.1 Debug Port Soft Reset ............ 4-4 Reset Status Register ................4-5 How to Configure Reset ................ 4-7 4.3.1...
Page 5 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 6.2.2 Basic Instruction Pipeline ............6-4 Sequencer Unit ..................6-4 6.3.1 Flow Control ................6-5 6.3.2 Issuing Instructions ..............6-6 6.3.3 Interrupts ..................6-7 6.3.4 Implementing the Precise Exception Model .......6-8 6.3.4.1 Restartability After an Interrupt ........6-10 6.3.5...
Page 6 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number PowerPC Architecture Compliance PowerPC User Instruction Set Architecture (Book I) ......7-1 7.1.1 Computation Modes ..............7-1 7.1.2 Reserved Fields ................. 7-1 7.1.3 Classes of Instructions ............... 7-1 7.1.4...
Page 7 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 7.3.6.1 Data Cache Block Invalidate (dcbi) .........7-7 7.3.6.2 TLB Invalidate Entry (tlbie) ..........7-7 7.3.6.3 TLB Invalidate All (tlbia) ..........7-7 7.3.6.4 TLB Synchronize (tlbsync) ..........7-7 7.3.7 Interrupts ..................7-7 7.3.7.1 Classes ................7-7...
Page 8 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 8.2.4 A Full History Buffer ..............8-8 8.2.5 Branch Folding ................8-9 8.2.6 Branch Prediction ..............8-10 Section 9 Instruction Cache Features ....................9-1 Programming the Instruction Cache ............. 9-4 9.2.1...
Page 9 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 10.3.2 Implementation-Specific Operations ........10-4 10.3.3 Special Registers of the Data Cache ........10-4 10.3.3.1 Data Cache Control and Status Register ......10-5 10.3.3.2 Data Cache Address Register ........10-7 10.3.3.3 Reading the Cache Structures ........10-7 10.4...
Page 10 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 11.6.1.7 MMU Data Real Page Number Register ....11-26 11.6.1.8 MMU Instruction Access Protection Register ..... 11-31 11.6.1.9 MMU Data Access Protection Register ...... 11-32 11.6.1.10 MMU Instruction Tablewalk Control Register ..... 11-33 11.6.1.11...
Page 11 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 12.4 The Bus Monitor ................12-11 12.5 The PowerPC Decrementer ..............12-12 12.5.1 Decrementer Register ............12-13 12.6 The PowerPC Timebase ..............12-14 12.6.1 Timebase Register ..............12-14 12.6.2 Timebase Reference Registers ..........12-15 12.6.3...
Page 12 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 13.4.5 Transfer Alignment and Packaging ........13-25 13.4.6 Arbitration Phase-Related Signals ......... 13-27 13.4.6.1 Bus Request Signal ............ 13-28 13.4.6.2 Bus Grant Signal ............13-29 13.4.6.3 Bus Busy Signal ............13-29 13.4.7...
Page 13 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 15.3.1.2 Option Registers ............15-11 15.3.1.3 Memory Status Register ..........15-15 15.3.1.4 Memory Command Register ........15-17 15.3.1.5 Machine A Mode Register ..........15-19 15.3.1.6 Machine B Mode Register ..........15-22 15.3.1.7 Memory Data Register ..........15-26 15.3.1.8...
Page 14 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 15.5.5.3.1 Hierarchical Bus Interface Example ....15-68 15.5.5.3.2 Slow Device Interface Example ..... 15-68 15.6 External Master Support ..............15-69 15.6.1 External Master Examples ............. 15-73 15.6.1.1 Memory System Interface Examples ......15-77 15.6.2...
Page 15 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 16.3.2.2 Software ..............16-27 16.3.2.3 Firmware ..............16-27 16.3.3 Programming the DSP Functions ...........16-27 16.3.3.1 Data Representation ...........16-28 16.3.3.2 Modulo Addressing .............16-29 16.3.3.2.1 DSP Function Descriptors ......16-29 16.3.3.2.2 DSP Parameter RAM Memory Map ....16-30 16.3.3.2.3...
Page 16 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 16.3.4.6.1 Coefficients and Sample Data Buffers ... 16-57 16.3.4.6.2 IIR Function Descriptor ........16-58 16.3.4.6.3 IIR Parameter Packet ........16-59 16.3.4.6.4 Application Example ........16-59 16.3.4.7 MOD–Real Sin, Real Cos, Complex X, and Real/Complex Y ............
Page 17 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 16.4.2.5 Timer Capture Registers ..........16-81 16.4.2.6 Timer Counter Registers ..........16-81 16.4.2.7 Timer Event Registers ..........16-82 16.4.3 Initializing the Timers ..............16-82 16.5 The SDMA Channels ................16-83 16.5.1 SDMA Bus Arbitration and Transfers ........16-85 16.5.2...
Page 18 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 16.7.4.2 One Multiplexed Channel with Dynamic Frames ..16-120 16.7.4.3 Programming the Serial Interface RAM Entries ..16-121 16.7.4.4 Serial Interface RAM Dynamic Changes ....16-124 16.7.5 Serial Interface Programming Model ........16-127 16.7.5.1...
Page 19 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 16.9.10.2 Asynchronous Protocols ...........16-191 16.9.10.3 Digital Phase-Locked Loop Operation ......16-191 16.9.10.4 Encoding and Decoding Data with a DPLL ....16-194 16.9.11 Clock Glitches ..............16-195 16.9.12 DPLL and Serial Infrared Encoder/Decoder ......16-196 16.9.13...
Page 20 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 16.9.15.7 SCCx HDLC Controller Errors ........16-239 16.9.15.8 SCCx HDLC Mode Register ........16-241 16.9.15.9 SCCx HDLC Receive Buffer Descriptor ....16-243 16.9.15.10 SCCx HDLC Transmit Buffer Descriptor ....16-247 16.9.15.11...
Page 21 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 16.9.18.12.1 SCC ASYNC HDLC Mode Register .....16-279 16.9.18.12.2 SCCx ASYNC HDLC Receive Buffer Descriptor ............16-280 16.9.18.12.3 SCCx ASYNC HDLC Transmit Buffer Descriptor ............16-282 16.9.18.12.4 SCCx ASYNC HDLC Event Register ...16-284 16.9.18.12.5...
Page 22 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 16.9.20.14 SCC2 Transparent Programming Example ....16-317 16.9.21 The SCCx in Ethernet Mode ..........16-318 16.9.21.1 Features ..............16-319 16.9.21.2 Ethernet On the MPC823 ......... 16-320 16.9.21.3 Understanding Ethernet on the MPC823 ....16-321 16.9.21.4...
Page 23 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 16.10.8.2 USB Receive Buffer Descriptor ........16-366 16.10.8.3 USB Transmit Buffer Descriptor ......16-369 16.10.8.4 USB Slave Address Register ........16-371 16.10.8.5 USB Command Register ..........16-372 16.10.8.6 USB Endpoint Configuration Registers 0–3 ....16-373 16.10.8.7...
Page 24 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 16.11.7 The SMCx in Transparent Mode .......... 16-410 16.11.7.1 Features ..............16-410 16.11.7.2 SMCx Transparent Channel Transmission Process ..............16-410 16.11.7.3 SMCx Transparent Channel Reception Process ..16-411 16.11.7.4...
Page 25 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 16.12.4 Programming the Serial Peripheral Interface .......16-444 16.12.4.1 SPI Mode Register ............16-444 16.12.4.1.1 SPI Examples With Different LEN Values ..16-446 16.12.4.1.2 SPI Receive Buffer Descriptor .....16-448 16.12.4.1.3 SPI Transmit Buffer Descriptor ....16-450 16.12.4.2...
Page 26 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 16.14.3.4 Port A Pin Assignment Register ....... 16-482 16.14.4 Port A Example Configurations ..........16-483 16.14.5 Port B Pin Functionality ............16-485 16.14.6 The Port B Registers ............16-486 16.14.6.1...
Page 27 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 17.1 Features ....................17-1 17.2 System Configuration ................17-1 17.3 PCMCIA Signals .................17-3 17.3.1 The PCMCIA Cycle Control Signals .........17-3 17.3.2 The PCMCIA Input Port Signals ..........17-5 17.3.3 The PCMCIA Output Port Signals ..........17-6 17.3.4...
Page 28 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 18.3.7 Timing Control ................ 18-13 18.3.8 Contrast and Brightness Control ..........18-13 18.3.9 The LCD Interface ..............18-13 18.3.9.1 Single-Scan and Dual-Scan Panels ......18-14 18.3.9.2 Passive Interface ............18-14 18.3.9.3...
Page 29 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 19.3.9 Video Frame Buffer A Start Address Register (Set 1) ....19-14 19.3.10 Video Frame Buffer B Start Address Register (Set 1) ....19-15 19.4 Video Controller RAM Array ..............19-16 19.4.1...
Page 30 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 20.3.2.4 Trap Enable Programming ......... 20-20 20.4 Hardware Development System Interface ........20-20 20.4.1 Trap Enable Mode ..............20-22 20.4.2 Debug Mode ................20-22 20.4.2.1 Debug Mode Enable vs. Debug Mode Disable ... 20-24 20.4.2.2...
Page 31 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Section 21 IEEE 1149.1 Test Access Port 21.1 The TAP Controller ................21-3 21.2 The Boundary Scan Register ..............21-4 21.3 The Instruction Register ..............21-19 21.3.1 The External Test Instruction ..........21-19 21.3.2...
Page 32 Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Appendix B MPC823 Instruction Set Instruction Formats ................B-1 Split-Field Notation ................B-1 Instruction Fields ...................B-2 Notations and Conventions ..............B-3 The MPC823 Instruction Set ..............B-6 Index MPC823 REFERENCE MANUAL ore Information On This Product,...
Page 33 Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure Page Number Title Number 1-1. MPC823 Block Diagram ..................1-7 1-2. MPC823 System Configuration ..............1-12 2-1. MPC823 Signal Pinout ..................2-1 4-1. Reset Configuration Basic Scheme..............4-7 4-2. Reset Configuration Sampling Scheme For Short PORESET Assertion .................4-8 4-3.
Page 34 Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Page Number Title Number 6-7. Number of Bus Cycles Needed For Unaligned, Single Register Fixed-Point Load/Store Instructions........6-28 6-8. Number of Bus Cycles Needed For String Instruction Execution....6-30 8-1. Example of a Data Cache Load ..............8-4 8-2.
Page 35 Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Page Number Title Number 13-11. Burst-Read Cycle–32-Bit Port Size–Zero Wait State ........13-18 13-12. Burst-Read Cycle–32-Bit Port Size–One Wait State ........13-19 13-13. Burst-Read Cycle–32-Bit Port Size–Wait States Between Beats....13-20 13-14. Basic Flow Diagram of a Burst Write Cycle..........13-21 13-15.
Page 36 Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Page Number Title Number 15-14. GPCM Write Followed By Read (EHTR = 1)..........15-35 15-15. GPCM Read Followed By Read From Different Banks (EHTR = 1) ... 15-36 15-16. GPCM Read Followed By Read From Same Bank (EHTR = 1) ....15-36 15-17.
Page 37 Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Page Number Title Number 15-52. EDO DRAM Single Beat Read Access............15-90 15-53. EDO DRAM Single Beat Write Access............15-91 15-54. EDO DRAM Burst Read Access..............15-92 15-55. EDO DRAM Burst Write Access..............15-93 15-56. EDO DRAM Refresh Cycle (CAS Before RAS)...........15-94 15-57.
Page 38 Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Page Number Title Number 16-35. Timer Cascaded Mode Block Diagram............16-76 16-36. SDMA Data Paths ..................16-83 16-37. SDMA Bus Arbitration ................. 16-84 16-38. IDMA Buffer Descriptor Ring ............... 16-91 16-39. Single-Address, Peripheral Write, Asynchronous TA........ 16-103 16-40.
Page 39 Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Page Number Title Number 16-76. SCCx HDLC Framing Structure..............16-231 16-77. HDLC Address Recognition Example............16-235 16-78. SCC2 HDLC Receive Buffer Descriptor Example ........16-242 16-79. HDLC Interrupt Event Example ..............16-248 16-80. Typical HDLC Bus Multimaster Configuration ...........16-255 16-81.
Page 40 Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Page Number Title Number 16-118. SMSYNx Pin Synchronization ..............16-409 16-119. Time-Slot Assigner Synchronization ............16-410 16-120. SPI Block Diagram ..................16-431 16-121. SPI Memory Format .................. 16-439 16-122. SPI Transfer Format If CP is Set to 0............16-443 16-123.
Page 41 Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Page Number Title Number 18-2. LCD Subsystem.....................18-3 18-3. Passive Interfaces ..................18-4 18-4. Active (TFT) Interface..................18-4 18-5. The MPC823 LCD System ................18-5 18-6. LCD Controller Block Diagram ..............18-6 18-7. LCD Functional Module .................18-7 18-8.
Page 42 Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Page Number Title Number 21-3. Output Pin Cell (O.Pin).................. 21-4 21-4. Observe-Only Input Pin Cell (I.Obs).............. 21-5 21-5. Output Control Cell (IO.CTL)................. 21-5 21-6. General Arrangement of Bidirectional Pin Cells ..........21-6 21-7.
Page 43 Freescale Semiconductor, Inc. LIST OF TABLES Table Page Number Title Number Section 2 External Signals 2-1. Signal Descriptions ..................2-2 2-2. Pin Breakout ....................2-13 Section 3 Memory Map 3-1. MPC823 Internal Memory Map ................3-1 Section 4 Reset 4-1. Possible Reset Results ..................4-1...
Page 44 Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Table Page Number Title Number Section 6 PowerPC Core 6-1. Branch Prediction Policy .................. 6-6 6-2. Before and After Interrupts ................6-8 6-3. Special Ports to Machine State Register Bits ..........6-11 6-4.
Page 45 Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Table Page Number Title Number Section 13 External Bus Interface 13-1. Bus Interface Signals ..................13-4 13-2. Data Bus Requirements For Read Cycles ...........13-26 13-3. Data Bus Contents for Write Cycles .............13-27 13-4. BURST/TSIZE Encoding ................13-33 13-5.
Page 46 Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Table Page Number Title Number Section 16 Communication Processor Module 16-1. RAM Microcode Configurations ..............16-9 16-2. RISC Microcontroller Commands ..............16-11 16-3. Parameter RAM Memory Map ..............16-16 16-4. RISC Timer Table Parameter RAM Memory Map ........16-19 16-5.
Page 47 Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Table Page Number Title Number 16-41. Port A Pin Assignment ................16-480 16-42. Port B Pin Assignment ................16-485 16-43. Port C Pin Assignment ................16-490 16-44. Port D Pin Assignment ................16-497 16-45. Prioritization of CPM Interrupt Sources ............16-503 16-46.
Page 48 Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Table Page Number Title Number Section 21 IEEE 1149.1 Test Access Port 21-1. Boundary Scan Bit Definition ................. 21-7 21-2. Instruction Decoding ..................21-19 Appendix A Serial Communication Performance A-1. MPC823 Performance Table ................A-3...
Page 49: Introduction
SECTION 1 INTRODUCTION The MPC823 microprocessor is a versatile, one-chip integrated microprocessor and peripheral combination that can be used in a variety of portable electronic products. It is a low-cost version of the MPC821 microprocessor, except it has been enhanced with additional communication and display capabilities.
Page 50 Introduction • Data Bus Dynamic Bus Sizing for 8-,16-, and 32-Bit Buses Supports Traditional 68K Big-Endian, Traditional x86 Little-Endian, and PowerPC Little-Endian Memory Systems Twenty-Six External Address Lines • Completely Static Design (0–75MHz Operation) • Communication Processor Module Embedded 32-Bit RISC Microcontroller Architecture for Flexible I/O Interfaces to PowerPC Core Through On-Chip Dual-Access RAM and Virtual (Serial) DMA Channels on a Dedicated DMA Accelerator Continuous Mode Transmission and Reception on All Serial and Parallel Channels...
Page 51 Introduction • Four Independent Baud Rate Generators (for Mask Revision Base #F98S, there are only two baud rate generators) and Two Input Clock Pins for Supplying Clocks to the SCC and SMC Serial Channels • Two Serial Communication Controllers Ethernet/IEEE 802.3 Support (10Mbps and Full-Duplex Operation) GeoPort Support HDLC Bus Implements an HDLC-Based Local Area Network Universal Asynchronous Receiver Transmitter (UART)
Page 52 Introduction Twelve Port Pins with Interrupt Capability Ten Internal Interrupt Sources Programmable Highest Priority Request • Memory Controller (Eight Banks) Contains Complete DRAM Controller Each Bank Can Be a Chip-Select or RAS to Support a DRAM Bank A Maximum of 30 Wait States per Memory Bank Can Be Programmed Glueless Interface to DRAM Single In-Line Memory Modules, Static RAM, Electrically Programmable Read-Only Memory, Flash EPROM or Synchronous DRAM...
Page 53 Introduction LCD Controller — 1-, 2-, or 4-Bit Per Pixel Grayscale Mode Using Advanced Frame Rate Control (FRC) Algorithm — 4-, 8-, 9-, or 12-Bit Parallel Output to LCD Displays — Programmable Display Active Area — Nonsplit- or Vertically Split-Screen Support —...
Page 54: Architecture
Introduction • Development Capabilities and Interface Program Flow Tracking — Instruction Show Cycle — Data Show Cycle — Branching — Exception Traps Watchpoints and Breakpoints — Four Hardware Breakpoints — Five Watchpoint Sources Simple Hardware Interface — High-Speed Data Transfer —...
Page 55 Introduction Figure 1-1. MPC823 Block Diagram MPC823 REFERENCE MANUAL...
Page 56: The Embedded Powerpc Core
Introduction 1.2.1 The Embedded PowerPC Core The PowerPC core complies with standard PowerPC architecture. It has a fully static design that consists of three functional blocks—the integer block, hardware multiplier/divider, and load/store block. The core supports integer operations on a 32-bit internal data path and 32-bit arithmetic hardware.
Page 57: The Communication Processor Module
Introduction The DRAM interface supports 8-, 16-, and 32-bit ports and uses a programmable state machine to support almost any memory interface. Memory banks can be defined in depths of 256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M, or 64M for all port sizes. In addition, the memory depth can be defined as 64K and 128K for 8-bit memory or 128M and 256M for 32-bit memory.
Page 58: The Video/Lcd Controller
Introduction 1.2.4 The Video/LCD Controller The MPC823 has a dual-purpose video/LCD controller that shares common dual-port memory. You can only run one of the controllers at a time. 1.2.4.1 THE VIDEO CONTROLLER. The video controller can be used to drive a digital NTSC/PAL encoder or a wide variety of digital LCD panels.
Page 59: Power Management
Introduction 1.4 POWER MANAGEMENT The MPC823 microprocessor supports a wide range of power management features, including normal high, normal low, doze, sleep, deep-sleep, and power-down modes. In normal high mode, the MPC823 microprocessor is fully powered with all internal units operating at the full speed of the processor.
Page 60: Mpc823 Glueless System Design
Introduction 1.8 MPC823 GLUELESS SYSTEM DESIGN The MPC823 was primarily designed to make it easy for you to interface a microprocessor with other system components. Figure 1-2 illustrates a system configuration that contains one flash EPROM and yet supports DRAM SIMM and one SRAM. Although the MPC823 supports a glueless interface to DRAM, the capacitance of the system bus may require that there be external buffers.
Page 61: External Signals
Freescale Semiconductor, Inc. SECTION 2 EXTERNAL SIGNALS This section briefly describes each of the MPC823 input and output signals. VDDSYN/VSSSYN/VSSSYN1/VDDH/VDDL/VSS/KAPWR A[6:31] USBRXD/PA[15] TSIZ0/REG USBOE/PA[14] TSIZ1 RXD2/PA[13] RD/WR TXD2/PA[12] BURST SMRXD2/L1TXDA/PA[9] BDIP/GPL_B5 SMTXD2/L1RXDA/PA[8] TIN1/L1RCLKA/BRGO1/CLK1/PA[7] TIN3/TOUT1/CLK2/PA[6] TIN2/L1TCLKA/BRGO2/CLK3/PA[5] TIN4/TOUT2/CLK4/PA[4] IRQ2/RSV LCD_A/SPISEL/PB[31] IRQ4/KR/RETRY/SPKROUT SPICLK/TXD3/PB[30]...
Page 62: The System Bus Signals
Freescale Semiconductor, Inc. External Signals 2.1 THE SYSTEM BUS SIGNALS The MPC823 system bus signals consist of all the lines that interface with the external bus. Many of these lines perform different functions, depending on how you assign them. The following input and output signals are identified by their mnemonic name and each signal’s...
Page 63 Freescale Semiconductor, Inc. External Signals Table 2-1. Signal Descriptions (Continued) SIGNAL PIN NUMBER DESCRIPTION Transfer Acknowledge—This bidirectional three-state signal indicates that the slave device addressed in the current transaction has accepted the data transferred by the master (write) or has driven the data bus with valid data (read). The signal behaves as an output when the PCMCIA memory controller takes control of the transaction.
Page 64 Freescale Semiconductor, Inc. External Signals Table 2-1. Signal Descriptions (Continued) SIGNAL PIN NUMBER DESCRIPTION Data Parity 2—This bidirectional three-state signal provides parity generation and checking for the data bus lane D[16:23] by transferring to a slave device initiated by IRQ5 the MPC823.
Page 65 Freescale Semiconductor, Inc. External Signals Table 2-1. Signal Descriptions (Continued) SIGNAL PIN NUMBER DESCRIPTION Chip Select 7—This output signal enables a peripheral or memory device at a programmed address if defined appropriately in the BR7 and OR7 registers of the CE2_B memory controller.
Page 66 Freescale Semiconductor, Inc. External Signals Table 2-1. Signal Descriptions (Continued) SIGNAL PIN NUMBER DESCRIPTION GPL_A2 General-Purpose Line 2 on UPMA—This output signal reflects the value specified GPL_B2 in the UPMA in the memory controller when an external transfer to a slave is controlled by the user programmable machine A (UPMA).
Page 67 Freescale Semiconductor, Inc. External Signals Table 2-1. Signal Descriptions (Continued) SIGNAL PIN NUMBER DESCRIPTION TEXP Timer Expired —This output signal reflects the status of the TEXPS bit of the PLPRCR register in the clock interface. WAIT_B Wait Slot B —This input signal, if asserted low, causes the completion of a transaction to be delayed on the PCMCIA-controlled Slot B.
Page 68 Freescale Semiconductor, Inc. External Signals Table 2-1. Signal Descriptions (Continued) SIGNAL PIN NUMBER DESCRIPTION IP_B6 Input Port B 6—This input signal is sensed by the MPC823 and its value and changes are reported in the PIPR and PSCR registers of the PCMCIA interface.
Page 69 Freescale Semiconductor, Inc. External Signals Table 2-1. Signal Descriptions (Continued) SIGNAL PIN NUMBER DESCRIPTION PA[5] General-Purpose I/O Port A Bit 5—Bit 5 of the general-purpose I/O port A. CLK3 CLK3—This input signal is one of the four clock pins that can be used to clock the serial communication controllers, serial management controllers, and USB.
Page 70 Freescale Semiconductor, Inc. External Signals Table 2-1. Signal Descriptions (Continued) SIGNAL PIN NUMBER DESCRIPTION PB[19] General-Purpose I/O Port B Bit 19—Bit 19 of the general-purpose I/O port B. L1ST1 L1ST1—One of eight output strobes that can be generated by the serial interface.
Page 71 Freescale Semiconductor, Inc. External Signals Table 2-1. Signal Descriptions (Continued) SIGNAL PIN NUMBER DESCRIPTION PC[5] General-Purpose I/O Port C Bit 5—Bit 5 of the general-purpose I/O port C. L1TSYNCA L1TSYNCA—The transmit sync input for the serial interface time-division multiplex port A.
Page 72 Freescale Semiconductor, Inc. External Signals Table 2-1. Signal Descriptions (Continued) SIGNAL PIN NUMBER DESCRIPTION PD[5] General-Purpose I/O Port D Bit 5—Bit 5 of the general-purpose I/O port D. FRAME FRAME—The output signal from the video controller that marks the beginning of a VSYNC new frame.
Page 73: Pin Breakout
Freescale Semiconductor, Inc. External Signals Table 2-2. Pin Breakout SIGNAL PIN NUMBER ADDRESS BUS PINS MPC823 REFERENCE MANUAL 2-13 For More Information On This Product, Go to: www.freescale.com...
Page 74 Freescale Semiconductor, Inc. External Signals Table 2-2. Pin Breakout (Continued) SIGNAL PIN NUMBER DATA BUS PINS MPC823 REFERENCE MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 75 Freescale Semiconductor, Inc. External Signals Table 2-2. Pin Breakout (Continued) SIGNAL PIN NUMBER CHIP SELECT PINS POWER SUPPLY PINS VDDH E5–12, F5, F12, G5, G12, H5, H12, J5, J12, K5, K12, L5, L12, M5–M12 VDDL A7, G1, J16, T7 VDDSYN...
Page 76: Memory Map
Freescale Semiconductor, Inc. SECTION 3 MEMORY MAP This section discusses the internal memory map (including key registers) of the MPC823. Each memory resource is mapped within a contiguous block of 16K storage. The location of this block within the global 4G real storage space can be mapped on 64K resolution through an implementation specific special register called the internal memory map register (IMMR).
Page 77 Freescale Semiconductor, Inc. Memory Map Table 3-1. MPC823 Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION POR1—PCMCIA Interface Option Register 1 17-17 PBR2—PCMCIA Interface Base Register 2 17-16 POR2—PCMCIA Interface Option Register 2 17-17 PBR3—PCMCIA Interface Base Register 3 17-16 POR3—PCMCIA Interface Option Register 3...
Page 78 Freescale Semiconductor, Inc. Memory Map Table 3-1. MPC823 Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION BR5—Base Register Bank 5 15-9 OR5—Option Register Bank 5 15-11 BR6—Base Register Bank 6 15-9 OR6—Option Register Bank 6 15-11 BR7—Base Register Bank 7...
Page 79 Freescale Semiconductor, Inc. Memory Map Table 3-1. MPC823 Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION CLOCKS AND RESET SCCR—System Clock and Reset Control Register PLPRCR—PLL, Low-Power and Reset Control Register RSR—Reset Status Register 28C to 2FF RES—Reserved...
Page 80 Freescale Semiconductor, Inc. Memory Map Table 3-1. MPC823 Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION VBCB—Video Background Color Buffer Register 19-9 80C to 80F RES—Reserved — VFCR0—Video Frame Configuration Register (Set 0) 19-10 VFAA0—Video Frame Buffer A Start Address Register (Set 0) 19-11 VFBA0—Video Frame Buffer B Start Address Register (Set 0)
Page 81 Freescale Semiconductor, Inc. Memory Map Table 3-1. MPC823 Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION 909 to 90B RES—Reserved — — SDMR—SDMA Mask Register (DSP Interrupts) 16-34, 16-88 90D to 90F RES—Reserved — —...
Page 82 Freescale Semiconductor, Inc. Memory Map Table 3-1. MPC823 Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION RES—Reserved — — PDDAT—Port D Data Register 16-494 978 to 97F RES—Reserved — — CPM TIMERS TGCR—Timer Global Configuration Register...
Page 83 Freescale Semiconductor, Inc. Memory Map Table 3-1. MPC823 Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION 9C8 to 9CB RES—Reserved — RCTR1—RISC Controller Trap Register 1 — RCTR2—RISC Controller Trap Register 2 — RCTR3—RISC Controller Trap Register 3 —...
Page 84 Freescale Semiconductor, Inc. Memory Map Table 3-1. MPC823 Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION SERIAL COMMUNICATION CONTROLLER 2 GSMR_L—SCC2 General Mode Low Register 16-163 GSMR_H—SCC2 General Mode High Register 16-163 PSMR—SCC2 Protocol-Specific Mode Register...
Page 85 Freescale Semiconductor, Inc. Memory Map Table 3-1. MPC823 Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION SCCE—SCC3 Event Register 16-184 16-224 (UART) 16-247 (HDLC) 16-281 (AHDLC) 16-311 (Trans) A52-A53 Reserved — SCCM—SCC3 Mask Register 16-184...
Page 86 Freescale Semiconductor, Inc. Memory Map Table 3-1. MPC823 Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION SERIAL PERIPHERAL INTERFACE SPMODE—SPI Mode Register 16-440 RES—Reserved — SPIE—SPI Event Register 16-449 AA7 to AA9 RES—Reserved — —...
Page 87 Freescale Semiconductor, Inc. Memory Map Table 3-1. MPC823 Internal Memory Map (Continued) INTERNAL SIZE PAGE NUMBER ADDRESS REGISTER (IN BITS) LOCATION DUAL-PORT RAM 2000 to 2FFF DPRAM—Dual-Port RAM 4,096 bytes — 3000 to 3BFF DPRAM—Dual-Port RAM Expansion 3,072 bytes* —...
Page 88: Reset
Freescale Semiconductor, Inc. SECTION 4 RESET The reset block of the MPC823 has a reset control logic that determines the cause of reset, synchronizes it if necessary, and resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized only on hard reset.
Page 89: Types Of Reset
Freescale Semiconductor, Inc. Reset 4.1 TYPES OF RESET The MPC823 has several types of inputs to the reset logic: • Power-on reset • External hard reset • Internal hard reset Loss of lock Software watchdog reset Checkstop reset Debug port hard reset JTAG reset •...
Page 90: External Hard Reset
Freescale Semiconductor, Inc. Reset 4.1.2 External Hard Reset HRESET (hard reset) is a bidirectional, active low I/O pin. The MPC823 can only detect an external assertion of HRESET if it occurs while the MPC823 is not asserting reset. During HRESET, SRESET is asserted. HRESET is an open-collector type of pin. SRESET (soft reset) is a bidirectional, active low I/O pin.
Page 91: External Soft Reset
Freescale Semiconductor, Inc. Reset 4.1.3.4 DEBUG PORT HARD RESET. When the development port receives a hard reset request from the development tool, an internal hard reset sequence is generated. In this case, the development tool must reconfigure the debug port. See Section 20.2.1.2.6 Detecting the Trace Window End Address for more information.
Page 92: Reset Status Register
Freescale Semiconductor, Inc. Reset 4.2 RESET STATUS REGISTER The 32-bit reset status register (RSR) is powered by the keep-alive power supply. As shown in Section 3 Memory Map , it is memory-mapped into the MPC823 system interface unit register map and receives its default reset values at power-on reset.
Page 93 Freescale Semiconductor, Inc. Reset SWRS—Software Watchdog Reset Status This bit is cleared by a power-on reset. When a software watchdog expire event occurs, this bit is set and remains that way until the software clears it. The SWRS bit can be negated by writing a 1, but a write of zero has no effect on it.
Page 94: How To Configure Reset
Freescale Semiconductor, Inc. Reset 4.3 HOW TO CONFIGURE RESET In normal operation, you can configure reset with a hard reset. However, to configure the development port you must use a soft reset. 4.3.1 Hard Reset When a hard reset event occurs, the MPC823 reconfigures its hardware system as well as the development port configuration.
Page 95 Freescale Semiconductor, Inc. Reset CLKOUT PORESET INTPORESET HRESET RSTCONF TSUP D[0:31] DEFAULT RSTCONF CONTROLLED Figure 4-2. Reset Configuration Sampling Scheme For Short PORESET Assertion CLKOUT PORESET INTPORESET HRESET RSTCONF TSUP D[0:31] DEFAULT RSTCONF CONTROLLED Figure 4-3. Reset Configuration Sampling Scheme...
Page 96 Freescale Semiconductor, Inc. Reset MPC823 REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com...
Page 97: Hard Reset Configuration Word
Freescale Semiconductor, Inc. Reset 4.3.1.1 HARD RESET CONFIGURATION WORD. The hard reset configuration word is sampled from the data bus. At reset, the bits will determine the default values of the corresponding bits in the SIUMCR, IMMR, and MSR. HARD RESET CONFIGURATION WORD...
Page 98 Freescale Semiconductor, Inc. Reset ISB—Initial Internal Space Base Select This field defines the initial value of the IMMR bits 0-15 and determines the base address of the internal memory space. Make sure that the IMMR is not in the interrupt address space (IIP).
Page 99: Soft Reset
Freescale Semiconductor, Inc. Reset DBPC—Debug Port Pins Configuration This field configures the following pins on the active development port. 00 = ALE_B/DSCK/AT1 functions as defined by DBGC. IP_B6/DSDI/AT0 functions as defined by DBGC. OP3/MODCK2/DSDO functions as defined by DBGC. IP_B7/PTR/AT3 functions as defined by DBGC.
Page 100: Clocks And Power Control
Freescale Semiconductor, Inc. SECTION 5 CLOCKS AND POWER CONTROL The MPC823 clock system provides many different timing options for all on-chip and external devices. It contains phase-locked loop circuitry and frequency dividers that generate programmable clock timing for baud rate generators, timers, the LCD controller, and a variety of low-power mode options.
Page 101: Clocks And Power Control
Freescale Semiconductor, Inc. Clocks and Power Control MODCK[1:2] VDDSYN EXTCLK VCOOUT SPLL GCLK2 GCLK1/GCLK2 GCLK1C/GCLK2C TBS (SCCR) GCLK1_50/GCLK2_50 2:1 MUX LOW-POWER (÷4 OR ÷16 ) DIVIDERS CLOCK BRGCLK DRIVERS LCDCLK SYNCCLK CLKOUT CLKOUT DRIVER TMBCLK TBCLK TMBCLK DRIVER RTDIV RTSEL ÷4...
Page 102: Register Model
Freescale Semiconductor, Inc. Clocks and Power Control 5.2 REGISTER MODEL 5.2.1 System Clock and Reset Control Register The SPLL has a 32-bit control register that is powered by keep-alive power. The system clock and reset control register (SCCR) is memory-mapped into the MPC823 system interface unit’s register map.
Page 103 Freescale Semiconductor, Inc. Clocks and Power Control TBS—Timebase Source This bit determines the clock source that drives the timebase and decrementer. 0 = Timebase frequency source is OSCCLK divided by 4 or 16. 1 = Timebase frequency source is GCLK2 divided by 16.
Page 104 Freescale Semiconductor, Inc. Clocks and Power Control EBDF—External Bus Division Factor This field defines the frequency division factor between GCLKx and GCLKx_50. CLKOUT is similar to GCLK2_50. The GCLKx_50 is used by the bus interface and memory controller to interface with an external system. This field is initialized during hard reset using the hard reset configuration word described in Section 4.3.1.1 Hard Reset Configuration Word .
Page 105 Freescale Semiconductor, Inc. Clocks and Power Control DFNH—Division Factor High Frequency This field sets the VCOOUT frequency division factor for general system clocks to be used in normal mode. In normal mode, the MPC823 automatically switches to the DFNH frequency. To select the DFNH frequency, load this field with the divide value and clear the CSRC bit.
Page 106: Pll, Low-Power, And Reset Control Register
Freescale Semiconductor, Inc. Clocks and Power Control 5.2.2 PLL, Low-Power, and Reset Control Register The 32-bit system PLL, low-power, and reset control register (PLPRCR) is powered by a keep-alive power supply and is used to control the system frequency and low-power mode operation.
Page 107 Freescale Semiconductor, Inc. Clocks and Power Control SPLSS—System PLL Lock Status Sticky This bit is not affected by hard reset. An out-of-lock indication sets the SPLSS bit and it remains set until the software clears it. At power-on reset, the state of the SPLSS bit is zero.
Page 108 Freescale Semiconductor, Inc. Clocks and Power Control LPM—Low-Power Modes This bit, in conjunction with the TEXPS and CSRC bits, specifies the operating mode of the core. There are seven possible modes. In the normal mode, you can write a non-zero value to this field.
Page 109: The Clock Module
Freescale Semiconductor, Inc. Clocks and Power Control 5.3 THE CLOCK MODULE The input frequency source for the phase-locked loop can either be a low frequency crystal or a high frequency crystal (4MHz) that the phase-locked loop multiplies to produce the system clock.
Page 110 Freescale Semiconductor, Inc. Clocks and Power Control OSCCLK PHASE VCOOUT CHARGE COMPARATOR DOWN FEEDBACK PUMP VDDSYN / VSSSYN CLOCK MULTIPLICATION FACTOR DELAY MF[0:11] NORMAL OR DOZE MODE SYNCCLK DFSYNC BRGCLK DFBRG GCLK1C NORMAL MODES CORE GCLK2C PHASE DFNH GCLK1 GCLK2...
Page 111: On-Chip Oscillators And External Clock Input
Freescale Semiconductor, Inc. Clocks and Power Control 5.3.1 On-Chip Oscillators and External Clock Input The main clock oscillator (OSCM) uses either a 3-5MHz source at EXTCLK (4MHz mode) oscillator or a 30-50kHz (32kHz mode) crystal between EXTAL and XTAL to generate the SPLL reference clock (OSSCLK).
Page 112: Spll Stability
Freescale Semiconductor, Inc. Clocks and Power Control The OSCCLK signal goes to the phase comparator that controls the direction in which the charge pump drives the voltage across the external filter capacitor (XFC). Direction is based on whether the feedback signal phase lags or leads the reference signal. The output of the...
Page 113: The Low-Power Clock Divider
Freescale Semiconductor, Inc. Clocks and Power Control The phase jitter is a variation in the skew that occurs between the falling edges of the EXTAL and CLKOUT pins for a specific temperature, voltage, input frequency, MF, and capacitive load on the CLKOUT pin. These variations are a result of the PLL locking mechanism. For input frequencies greater than 15MHz and MF ≤...
Page 114 Freescale Semiconductor, Inc. Clocks and Power Control NORMAL OR DOZE MODE SYNCCLK DFSYNC BRGCLK DFBRG GCLK1C NORMAL MODES CORE GCLK2C PHASE DFNH GCLK1 GCLK2 UPM, GCLK1 PCMCIA, DFNL EXTERNAL GCLK1_50 EBDF INTERFACE PHASE GCLK2_50 LOW-POWER MODE CLKOUT COM[0:1] LCDCLK LCD/VIDEO...
Page 115: Internal Clock Signals
Freescale Semiconductor, Inc. Clocks and Power Control 5.3.4 Internal Clock Signals The internal logic of the MPC823 uses the following internal clock signals: • General system clocks • Baud rate generator clock • Synchronization clocks • LCD clocks The MPC823 also generates an external clock signal called CLKOUT. All internal clock signals originate from the same source, so they are all synchronized to VCOOUT.
Page 116 Freescale Semiconductor, Inc. Clocks and Power Control Notice that GCLK1_50, GCLK2_50, and CLKOUT can have a lower frequency than GCLK1 and GCLK2. This allows the external bus to operate at lower frequencies as controlled by the EBDF bit in the SCCR. GCLK2_50 always rises simultaneously with GCLK2. GCLK1_50...
Page 117 Freescale Semiconductor, Inc. Clocks and Power Control When none of these conditions exist and the CSRC bit of the PLPRCR is set, the general system clock automatically switches back to low frequency. When the general system clock is divided, its duty-cycle is modified. One phase remains the same while the other stretches out.
Page 118 Freescale Semiconductor, Inc. Clocks and Power Control The frequency for the GCLKx system clock is: VCOOUT freq GCLKx -------------------------------------------------------------- freq DFNH DFNL 1 )or 2 The frequency for the GCLKx_50 system clock is: VCOOUT freq × GCLKx_50 -------------------------------------------------------------- --------------------------- freq...
Page 119: The Baud Rate Generator Clock
Freescale Semiconductor, Inc. Clocks and Power Control The baud rate generator clock frequency is: VCOOUT freq BRGCLK freq ------------------------------------------ - × 2 DFBRG 5.3.4.3 THE SYNCHRONIZATION CLOCKS. The synchronization clock signal (SYNCCLK) is used by the serial synchronization circuitry in the serial ports of the communication processor module that includes the serial interface, serial communication controllers, and serial management controllers.
Page 120: The Lcd Clocks
Freescale Semiconductor, Inc. Clocks and Power Control 5.3.4.4 THE LCD CLOCKS. The LCD clocks—LCDCLK and LCDCLK50—are used by the LCD controller circuitry to transfer the frame data to pixel format data. LCDCLK defaults to VCOOUT, which is the user-defined system frequency (25-75MHz).When the PON bit in the LCCR is set, the ratio between the system clock frequency value and the LCD clock frequency value must be an integer value.
Page 121: Clock Configuration
Freescale Semiconductor, Inc. Clocks and Power Control 5.3.5 Clock Configuration You can configure the clock of the MPC823 using the MODCK1 and MODCK2 pins. The SPLL has several power and ground pins (VDDSYN, VSSSYN, VSSSYN1, and XFC) that must be properly terminated for stability and CLKOUT integrity.
Page 122: The System Phase-Locked Loop Pins
Freescale Semiconductor, Inc. Clocks and Power Control Table 5-3. TMBCLK Dividers TBS BIT IN SCCR MODCK1 AT MF + 1 CLOCK SOURCE TMBCLK DIVISION RESET — — GCLK2 — OSCM 1, 2 EXTAL > 2 EXTAL 5.3.5.2 THE SYSTEM PHASE-LOCKED LOOP PINS. The internal frequency of the MPC823 and the output of the CLKOUT pin depends on the quality of the crystal circuit and the MF bit in the PLPRCR.
Page 123: Power Control
Freescale Semiconductor, Inc. Clocks and Power Control 5.4 POWER CONTROL To preserve the life of your battery, the MPC823 provides low-power modes that limit the operation to essential modules. In addition to normal high mode, the MPC823 supports normal low, doze high, doze low, sleep, deep-sleep, and power-down modes. When the communication processor module is idle, it uses its own power-saving mechanism to shut down automatically.
Page 124 Freescale Semiconductor, Inc. Clocks and Power Control All other circuits are powered by the normal supply pins—VDDH and VDDL—and VSS. VDDH feeds the I/O buffers and logic and VDDL supplies the internal chip logic to reduce system power consumption. However, the power supply connected to VDDH must be larger or equal to the one connected to VDDL.
Page 125: Power Switching Example
Freescale Semiconductor, Inc. Clocks and Power Control 5.4.2.1 POWER SWITCHING EXAMPLE. An example of a switching scheme for an optimized low-power system is illustrated in Figure 5-16. MPC823 MAIN POWER SUPPLY VDDSYN 3.3V 2.2V VDDH VDDL KAPWR 2.5-3.3V BACKUP TEXP...
Page 126: Key Registers
Freescale Semiconductor, Inc. Clocks and Power Control 5.4.2.2 REGISTER LOCK. The MPC823 registers that are powered by KAPWR can be write-protected using the associated key register shown in Table 5-6. When the MPC823 disconnects from the main power supply after it enters power-down mode, the value of these registers is automatically preserved.
Page 127: Low-Power Operation
Freescale Semiconductor, Inc. Clocks and Power Control POWER-ON RESET OPEN WRITE 0x55CCAA33 TO WRITE ANY OTHER VALUE TO THE KEY REGISTER THE KEY REGISTER LOCKED Figure 5-17. Register Lock Mechanism 5.5 LOW-POWER OPERATION The low-power dividers can be used to take advantage of the MPC823’s low-power capabilities.
Page 128 Freescale Semiconductor, Inc. Clocks and Power Control CRQEN & CPM_ACT | PRQEN & (POW | INTERRUPT) | CSRC NORMAL LOW MODE (PRQEN | POW & INTERRUPT) & CRQEN | CPM_ACT) & CSRC*** LPM = 00, CSRC = 1 DOZE LOW MODE...
Page 129 Freescale Semiconductor, Inc. Clocks and Power Control The system responds quickly to an interrupt that does not come from the interrupt controller. The wake-up time from normal low, doze high, doze low, or sleep mode is between three and four VCOOUT clocks. For example, it could take 60-80ns to wake up in a 75MHz system.
Page 130: Mpc823 Low-Power Modes
Freescale Semiconductor, Inc. Clocks and Power Control When a timer expires, if enabled, the TEXP pin is asserted asynchronously with CLKOUT to show that the MPC823 is preparing to exit power-down mode. TEXP must be externally connected to a switch that must turn on the power supply to the chip, as illustrated in Figure 5-16.
Page 131: The Powerpc Core
Freescale Semiconductor, Inc. SECTION 6 THE P PC CORE OWER ™ The MPC823 core is where the PowerPC architecture is implemented. It has the functionality of the PowerPC branch processor and fixed-point processor and includes all the PowerPC user mode (problem mode) instructions, except floating-point instructions, relevant privileged instructions, and all the registers associated with the processors and instructions.
Page 132: Basic Structure Of The Core
Freescale Semiconductor, Inc. The PowerPC Core 6.2 BASIC STRUCTURE OF THE CORE To accomplish its tasks, the core is divided into the following subunits: • Sequencer Unit —Consists of the branch processor (next address generation), the instruction prefetch queue, and the interrupt handling mechanism. It controls some data structures within the register unit.
Page 133 Freescale Semiconductor, Inc. The PowerPC Core INSTRUCTION CACHE / INSTRUCTION MMU INTERFACE DATA CACHE / DATA MMU INTERFACE CORE SEQUENCER NEXT ADDRESS BRANCH INSTRUCTION GENERATION UNIT QUEUE CONTROL BUS WRITEBACK BUS (2 SLOTS / CLOCK) LDST CONTR IMUL / ALU /...
Page 134: Basic Instruction Pipeline
Freescale Semiconductor, Inc. The PowerPC Core 6.2.2 Basic Instruction Pipeline Figure 6-3 illustrates the basic instruction pipeline timing. FETCH DECODE READ + EXECUTE WRITE BACK L ADDRESS DRIVE L DATA STORE LOAD LOAD WRITE BACK BRANCH DECODE BRANCH EXECUTE Figure 6-3. Basic Instruction Pipeline Timing Diagram 6.3 SEQUENCER UNIT...
Page 135: Flow Control
Freescale Semiconductor, Inc. The PowerPC Core 6.3.1 Flow Control Flow control operations, or branches disrupt normal instruction pipeline flow. A change in program flow creates bubbles in the pipeline because of the time it takes to fetch the newly targeted instruction stream. In typical code, with 4 or 5 sequential instructions between branches, the machine could waste up to 25% of its execution bandwidth waiting on branch latency.
Page 136: Issuing Instructions
Freescale Semiconductor, Inc. The PowerPC Core In addition to branch folding, the core implements a branch reservation station and static branch prediction so branches can issue as early as possible. The reservation station allows a branch instruction to issue even before its condition is ready. With the branch issued and out of the way, instruction prefetch can continue while the branch operand is being computed and the condition is evaluated.
Page 137: Interrupts
Freescale Semiconductor, Inc. The PowerPC Core 6.3.3 Interrupts The core interrupts can be generated when an exception occurs. An exception results when certain instructions are executed or an asynchronous external event occurs. There are five exception sources in the MPC823: •...
Page 138: Implementing The Precise Exception Model
Freescale Semiconductor, Inc. The PowerPC Core Table 6-2. Before and After Interrupts INTERRUPT TYPE INSTRUCTION BEFORE / CONTENTS OF SRR0 TYPE AFTER Hard Reset Undefined System Reset Before Next Instruction to Execute Machine Check Interrupt Before Faulting Instruction Implementation Specific Instruction /...
Page 139 Freescale Semiconductor, Inc. The PowerPC Core In the event of an exception, the machine state necessary to recover the architectural state is available. As instructions finish executing, they are released (retired) from the queue and the buffer storage is reclaimed for new instructions entering the queue. An exception can be detected at any time during instruction execution and is recorded in the history buffer when the instruction finishes execution.
Page 140: Restartability After An Interrupt
Freescale Semiconductor, Inc. The PowerPC Core 6.3.4.1 RESTARTABILITY AFTER AN INTERRUPT Most of the interrupt cases in the core are always restartable. Some interrupts may be unable to be restarted because they can be recognized when the machine status save/restore 0 and 1 registers (SRR0 and SRR1) are busy. Such interrupts in the PowerPC architecture are known as system reset and machine check.
Page 141: Processing An Interrupt
Freescale Semiconductor, Inc. The PowerPC Core Table 6-3. Special Ports to Machine State Register Bits MNEMONIC USED FOR External Interrupt Enable: End of Interrupt Handler’s Prologue, Enable Nested External Interrupts; End of Critical Code Segment in Which External Interrupts Were Disabled External Interrupt Disable, But Other Interrupts Are Recoverable: End of Interrupt Handler’s Prologue, Keep External...
Page 142: Serialization
Freescale Semiconductor, Inc. The PowerPC Core At time point A the excepting instruction issues and begins executing. During the interval between A and B, previously issued instructions are finishing execution. This interval is equivalent to the time required for all instructions currently in progress to complete. At time point B, the exception is recognized and during the interval between B and D the machine state is being restored.
Page 143: The External Interrupt
Freescale Semiconductor, Inc. The PowerPC Core 6.3.7 The External Interrupt The core provides one external interrupt line: the architectural maskable external interrupt. In the MPC823, this interrupt is generated by the on-chip interrupt controller. It is software acknowledged and maskable by the MSR bit, which is automatically cleared by the hardware to disable external interrupts when any interrupt is taken.
Page 144: Interrupt Ordering
Freescale Semiconductor, Inc. The PowerPC Core 6.3.8 Interrupt Ordering There are two main types of interrupts: • Instruction-related interrupts • Asynchronous interrupts Instruction-related exceptions (interrupt causes) are detected while the instruction is in various stages of being processed by the core. Exceptions found early in instruction processing preclude detection of further exceptions.
Page 145: The Register Unit
Freescale Semiconductor, Inc. The PowerPC Core More than one asynchronous interrupt cause or exception can be present at any time. However, when more than one interrupt causes exist, only the highest priority interrupt is taken, as shown in the following table.
Page 146: Control Registers
Freescale Semiconductor, Inc. The PowerPC Core 6.4.1 Control Registers The following tables describe the core control registers, also known as special-purpose registers, implemented within the MPC823. Table 6-7. Standard Special-Purpose Registers REGISTER PRIVILEGED SERIALIZE ACCESS NAME DECIMAL 00000 00001 Write:...
Page 147 Freescale Semiconductor, Inc. The PowerPC Core Table 6-9. Additional Special-Purpose Registers REGISTER PRIVILEGED SERIALIZE ACCESS NAME DECIMAL 00010 10000 Write 00010 10001 Write 00010 10010 Write 00100 10000 Fetch Sync on Write CMPA Debug 00100 10001 CMPB Debug Fetch Sync on Write...
Page 148 Freescale Semiconductor, Inc. The PowerPC Core Table 6-9. Additional Special-Purpose Registers (Continued) REGISTER PRIVILEGED SERIALIZE ACCESS NAME DECIMAL 10011 11110 IMMR Write - As a Store 10001 10000 IC_CSR Write - As a Store 10001 10001 IC_ADR Write - As a Store...
Page 149: Physical Location Of Special Registers
Freescale Semiconductor, Inc. The PowerPC Core Table 6-10. Other Control Registers DESCRIPTION NAME COMMENTS PRIVILEGED SERIALIZE ACCESS Machine State Register — Write Fetch Sync Condition Register — Only mtcrf 6.4.1.1 PHYSICAL LOCATION OF SPECIAL REGISTERS Some of the special registers in the core are physically located outside of the core. Access to these registers is gained the same way as any other special register—via the appropriate...
Page 150: Machine State Register
Freescale Semiconductor, Inc. The PowerPC Core 6.4.1.2 P PC STANDARD CONTROL REGISTER BIT ASSIGNMENT OWER 6.4.1.2.1 Machine State Register. The 32-bit machine state register (MSR) defines the state of the processor. It can be read by the mfmsr instruction. However, it can be modified by the mtmsr, sc, and rfi instructions, as well as the hard reset configuration word.
Page 151 Freescale Semiconductor, Inc. The PowerPC Core PR—Problem State This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The appropriate bit in the MSR is loaded from this bit when an rfi is executed.
Page 152: The Condition Register
Freescale Semiconductor, Inc. The PowerPC Core DR—Data Relocate This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The appropriate bit in the MSR is loaded from this bit when an rfi is executed.
Page 153: Fixed-Point Exception Cause Register
Freescale Semiconductor, Inc. The PowerPC Core 6.4.1.2.3 Fixed-Point Exception Cause Register. The following table provides the bit assignments for the fixed-point exception cause register (XER). The bits are based on the final result produced by executing an instruction. FIELD RESERVED...
Page 154: Initializing The Control Registers
Freescale Semiconductor, Inc. The PowerPC Core 6.4.1.3 INITIALIZING THE CONTROL REGISTERS 6.4.1.3.1 System Reset Interrupt. A system reset interrupt occurs when the IRQ0 pin is asserted. The only control registers affected by the system reset interrupt are the MSR, SRR0, and SRR1 registers. For information on the values of these registers, refer to Section 7.3.7.3.1 System Reset Interrupt.
Page 155: The Load/Store Unit
Freescale Semiconductor, Inc. The PowerPC Core 6.6 THE LOAD/STORE UNIT The load/store unit handles all data transfers between the register file and chip internal bus. It is implemented as an independent execution unit so that stalls in the memory pipeline do not cause the master instruction pipeline to stall, unless there is a data dependency.
Page 156: Issuing Load/Store Instructions
Freescale Semiconductor, Inc. The PowerPC Core CORE FIXED-POINT FIXED-POINT UNIT REGISTERS FILE ADDRESS FIXED-POINT FIXED-POINT LOAD DATA STORE DATA ADDRESS FIXED-POINT QUEUE DATA QUEUE INCREMENT LOAD / STORE UNIT D-CACHE / D-MMU INTERFACE Figure 6-6. Load/Store Unit Functional Block Diagram To execute multiple (lmw, stmw) instructions, string instructions, and unaligned accesses, the load/store unit contains an address incrementor that generates the needed addresses.
Page 157: Serializing Load/Store Instructions
Freescale Semiconductor, Inc. The PowerPC Core If there are no prior instructions waiting in the address queue, the load/store instruction is issued to the data cache immediately at the time the instruction is taken. Otherwise, if there are prior instructions remaining whose addresses have not yet been issued to the data cache, the instruction is inserted into the address queue and data is inserted into the respective store data queue.
Page 158: Executing Unaligned Instructions
Freescale Semiconductor, Inc. The PowerPC Core 6.6.6 Executing Unaligned Instructions The load/store unit supports fixed-point unaligned accesses in the hardware. The 32-bit L-bus only supports naturally aligned transfers. For an unaligned instruction, the load/store unit breaks the instruction into a series of aligned transfers that are pipelined into the bus.
Page 159: Little-Endian Mode Support
Freescale Semiconductor, Inc. The PowerPC Core 6.6.7 Little-Endian Mode Support The load/store unit implements the little-endian mode as it is specified by the PowerPC architecture and in this mode the modified address is issued to the data cache. For an individual scalar unaligned transfer or an attempted execution of a multiple/string instruction, an alignment exception is generated.
Page 160: Instruction Timing
Freescale Semiconductor, Inc. The PowerPC Core 6.6.9 Instruction Timing The following table summarizes the different load/store instructions timing in the case of zero wait state memory references on a parked bus. With external memory accesses, pipelined external accesses are assumed.
Page 161: Storage Control Instructions
Freescale Semiconductor, Inc. The PowerPC Core 6.6.12 Storage Control Instructions Cache management instructions and lookaside buffer management instructions are implemented by the load/store unit. These instructions are implemented as the special bus write cycles, which are issued to the data cache interface.
Page 162: Powerpc Architecture Compliance
Freescale Semiconductor, Inc. SECTION 7 PC ARCHITECTURE COMPLIANCE OWER This section describes implementation-dependent choices made for the core on issues that ™ architecture as defined in the PowerPC Architecture Books are optional on the PowerPC I, II, and III . It also describes features that exist in the architecture, but are not supported by the core.
Page 163: Exceptions
Freescale Semiconductor, Inc. PowerPC Architecture Compliance 7.1.4 Exceptions Invocation of the system software for any exception caused by an instruction in the core is precise, regardless of the type and setting. 7.1.5 The Branch Processor 7.1.6 Fetching Instructions The core fetches a number of instructions into its internal buffer (the instruction prefetch queue) prior to execution.
Page 164: The Load/Store Processor
Freescale Semiconductor, Inc. PowerPC Architecture Compliance 7.1.8.1 MOVE TO/FROM SYSTEM REGISTER INSTRUCTIONS. Move to/from invalid special registers in which spr =1 invokes the privilege instruction error interrupt handler if the processor is in problem state (user mode). For a list of all implemented special registers, refer to Section 6.4.1 Control Registers.
Page 165: Optional Instructions
Freescale Semiconductor, Inc. PowerPC Architecture Compliance 7.1.9.4 STORAGE SYNCHRONIZATION INSTRUCTIONS. For these type of instructions, EA must be a multiple of four. If it is not, the system alignment error handler is invoked. 7.1.9.5 OPTIONAL INSTRUCTIONS. No optional instructions are supported.
Page 166: The Effect Of Operand Placement On Performance
Freescale Semiconductor, Inc. PowerPC Architecture Compliance 7.2.2 The Effect Of Operand Placement on Performance The load/store unit hardware supports all of the PowerPC load/store instructions. An optimal performance can be obtained for naturally aligned operands. These accesses result in optimal performance for a maximum size of four bytes. Unaligned operands are supported in the hardware and are broken into a series of aligned transfers.
Page 167: Timebase
Freescale Semiconductor, Inc. PowerPC Architecture Compliance 7.2.4 Timebase A description of the timebase register can be found in Section 12 System Interface Unit and Section 5 Clocks and Power Control. 7.3 P PC OPERATING ENVIRONMENT ARCHITECTURE (BOOK III) OWER The MPC823 has an internal memory space that includes memory-mapped control registers and memory that is used by various modules on the chip.
Page 168: Reference And Change Bits
Freescale Semiconductor, Inc. PowerPC Architecture Compliance The features of the MMU hardware is as follows: • 8-entry fully associative instruction TLB • 8-entry fully associative data TLB • Supports up to 16 virtual address spaces • Supports 16 access protection groups •...
Page 169: Definitions
Freescale Semiconductor, Inc. PowerPC Architecture Compliance 7.3.7.3 DEFINITIONS. The following table defines the offset value by interrupt type and the sections that follow describe each interrupt in detail. Table 7-1. Offset of First Instruction by Interrupt Type OFFSET (HEX) INTERRUPT TYPE...
Page 170 Freescale Semiconductor, Inc. PowerPC Architecture Compliance 7.3.7.3.1 System Reset Interrupt. A system reset interrupt occurs when the IRQ0 pin is asserted and the following registers are set. Execution begins at physical address 0x100 if the hard reset configuration word IIP bit is 1. Execution begins at physical address 0xFFF00100 if the hard reset configuration word IIP bit is 0.
Page 171: Alignment Interrupt
Freescale Semiconductor, Inc. PowerPC Architecture Compliance SRR1—Save/Restore Register 1 Set to 1 for instruction fetch-related errors and 0 for load/store-related errors. 2–4 Set to 0. 10–15 Set to 0. Other Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of the SRR1 is never cleared, except by loading a zero value from MSR MSR—Machine State Register...
Page 172: Program Interrupt
Freescale Semiconductor, Inc. PowerPC Architecture Compliance 7.3.7.3.6 Program Interrupt. The MPC823 cannot generate a floating-point exception type interrupt. Likewise, an illegal instruction type program interrupt is not generated by the core, but an implementation-dependent software emulation interrupt is generated instead. A...
Page 173: Implementation-Dependent Software
Freescale Semiconductor, Inc. PowerPC Architecture Compliance 7.3.7.3.10 Implementation-Dependent Software Emulation Interrupt. An implementation-dependent software emulation interrupt occurs as a result of one of the following conditions: • When executing any unimplemented instruction, including all illegal and unimplemented optional and floating-point instructions.
Page 174 Freescale Semiconductor, Inc. PowerPC Architecture Compliance SRR1—Save/Restore Register 1 0–3 Set to 0. Set to 1. Set to 1. 11–15 Set to 0. Other Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of the SRR1 is never cleared, except by loading a zero value from MSR MSR—Machine State Register...
Page 175: Implementation-Specific Data Tlb Miss
Freescale Semiconductor, Inc. PowerPC Architecture Compliance MSR—Machine State Register No change. No change. Bits are copied from the ILE. Other Set to 0. Some instruction TLB registers are set to a value described in Section 11 Memory Management Unit. Execution resumes at offset x’01300’ from the base address indicated by MSR 7.3.7.3.13 Implementation-Specific Data TLB Miss Interrupt.
Page 176 Freescale Semiconductor, Inc. PowerPC Architecture Compliance SRR1—Save/Restore Register 1 1–4 Set to 0. 10–15 Set to 0. Other Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of the SRR1 is never cleared, except by loading a zero value from MSR MSR—Machine State Register...
Page 177 Freescale Semiconductor, Inc. PowerPC Architecture Compliance The following registers are set: SRR0—Save/Restore Register 0 For I-breakpoints, set to the effective address of the instruction that caused the interrupt. For L-breakpoint, set to the effective address of the instruction following the instruction that caused the interrupt.
Page 178 Freescale Semiconductor, Inc. PowerPC Architecture Compliance 7.3.7.4 PARTIALLY EXECUTED INSTRUCTIONS. In general, the architecture allows instructions to be partially executed when an alignment or data storage interrupt occurs. In the core, instructions are not executed if an alignment interrupt condition is detected or if a data storage interrupt is never generated by the hardware.
Page 179: Instruction Execution Timing
Freescale Semiconductor, Inc. SECTION 8 INSTRUCTION EXECUTION TIMING This section describes the timing of the instruction cycles in terms of clock cycles, including serialization, latency, and blockage. 8.1 INSTRUCTION TIMING LIST The following table lists the instruction execution timing in terms of latency and blockage of the appropriate execution unit.
Page 180 Freescale Semiconductor, Inc. Instruction Execution Timing Table 8-1. Instruction Execution Timing (Continued) INSTRUCTIONS LATENCY BLOCKAGE EXECUTION SERIALIZING UNIT INSTRUCTION Move from Others: Serialize + 1 Serialize + 1 — See List mfcr, mfmsr Fixed-Point Arithmetic: ALU / BFU addi, add[o][.], addis, subf[o][.], addic, subfic, addic., addc[o][.], adde[o][.],...
Page 181 Freescale Semiconductor, Inc. Instruction Execution Timing Table 8-1. Instruction Execution Timing (Continued) INSTRUCTIONS LATENCY BLOCKAGE EXECUTION SERIALIZING UNIT INSTRUCTION Storage Control Instructions: Serialize Serialize Branch isync Order Storage Access: LDST Next Load or Store eieio is Synchronized Relative to All Prior...
Page 182: Instruction Execution Timing Examples
Freescale Semiconductor, Inc. Instruction Execution Timing 8.2 INSTRUCTION EXECUTION TIMING EXAMPLES All examples assume an instruction cache hit. 8.2.1 Data Cache Load r12,64 (SP) r3,r12,3 addic r4,r14,1 mulli r5,r3,3 addi r4,3(r0) ADDIC MULLI ADDI FETCH ADDIC DECODE BUBBLE ADDIC READ + EXECUTE...
Page 183: Writeback
Freescale Semiconductor, Inc. Instruction Execution Timing 8.2.2 Writeback 8.2.2.1 WRITEBACK ARBITRATION mulli r12,r4,3 r3,r15,3 addic r4,r12,1 GCLK1 MULLI ADDIC FETCH MULLI ADDIC DECODE MULLI SUB, MULLI BUBBLE ADDIC READ + EXECUTE MULLI WRITEBACK Figure 8-2. Example of a Writeback Arbitration The addic instruction is dependent on the mulli result.
Page 184: Private Writeback Bus Load
Freescale Semiconductor, Inc. Instruction Execution Timing In this example, the addic instruction is dependent on the sub rather than on the mulli . Although the writeback of the mulli is delayed two clocks, there is no bubble in the execution stream.
Page 185: Fastest External Load (Data Cache Miss)
Freescale Semiconductor, Inc. Instruction Execution Timing 8.2.3 Fastest External Load (Data Cache Miss) r12,64 (SP) r3,r12,3 addic r4,r14,1 GCLK1 ADDIC FETCH DECODE BUBBLE BUBBLE BUBBLE BUBBLE READ + EXECUTE WRITEBACK L ADDRESS DRIVE L DATA CACHE ADDRESS LOAD WRITEBACK E ADDRESS E DATA Figure 8-5.
Page 186: A Full History Buffer
Freescale Semiconductor, Inc. Instruction Execution Timing 8.2.4 A Full History Buffer r12,64 (SP) r5,r5,3 addic r4,r14,1 r3,r4.r5 r4,r3,r5 r7,r8,1 GCLK1 ADDIC FETCH ADDIC DECODE ADDIC BUBBLE BUBBLE READ + EXECUTE WRITEBACK L ADDRESS DRIVE L DATA CACHE ADDRESS LOAD WRITEBACK...
Page 187: Branch Folding
Freescale Semiconductor, Inc. Instruction Execution Timing 8.2.5 Branch Folding r12,64 (SP) r3,r12,3 addic r4,r14,1 func func: mulli r5,r3,3 addi r4,3(r0) GCLK1 ADDIC BUBBLE MULLI ADDI FETCH ADDIC MULLI DECODE BUBBLE BUBBLE ADDIC MULLI READ + EXECUTE WRITEBACK L ADDRESS DRIVE...
Page 188: Branch Prediction
Freescale Semiconductor, Inc. Instruction Execution Timing 8.2.6 Branch Prediction while: mulli r3,r12,r4 addi r4,3(r0) r12,64 (r2) cmpi 0,r12,3 addic r6,r5,1 cr0,while GCLK1 CMPI ADDIC BUBBLE MULLI ADDI FETCH CMPI ADDIC MULLI DECODE BUBBLE BUBBLE CMPI ADDIC MULLI READ + EXECUTE...
Page 189: Instruction Cache
Freescale Semiconductor, Inc. SECTION 9 INSTRUCTION CACHE The MPC823 instruction cache is a 2K two-way, set associative storage area. It is organized into 64 sets, two lines per set and four words per line. Cache lines are aligned on 4-word boundaries in memory and can be used as an SRAM that allows the application to lock critical code segments that need fast and deterministic execution time.
Page 190 Freescale Semiconductor, Inc. Instruction Cache • Supports Cache Inhibit As a cache mode of operation (cache disable) On memory regions (supported by the memory management unit) • Efficiently Uses the Pipeline of the Internal Bus by Initiating a New Burst Cycle (if a Miss is Detected) while Bringing the Tail of the Previously Missed Line to the Cache.
Page 191 Freescale Semiconductor, Inc. Instruction Cache INSTRUCTION POINTER WORD SELECT WAY0 WAY1 SET0 TAG0 W0 W1 W2 W3 TAG0 W0 W1 W2 W3 SET1 TAG1 W0 W1 W2 W3 TAG1 W0 W1 W2 W3 SET62 TAG62 W0 W1 W2 W3 TAG62...
Page 192: Programming The Instruction Cache
Freescale Semiconductor, Inc. Instruction Cache ADDRESS [22:27] CACHE DECODER ARRAY ADDRESS [28:29] WORDS LINE BUFFER STREAM WORD WORDS SELECT BURST 2->1 BUFFER 4->1 DATA BYPASS 2->1 INSTRUCTION TO CORE INTERNAL BUS DATA Figure 9-2. Cache Data Path Block Diagram 9.2 PROGRAMMING THE INSTRUCTION CACHE...
Page 193: Instruction Cache Control And Status Register
Freescale Semiconductor, Inc. Instruction Cache 9.2.1 Instruction Cache Control and Status Register The instruction cache control and status register (IC_CST) is used to configure and access the status of the instruction cache. IC_CST FIELD RESERVED RESERVED CCER1 CCER2 CCER3 RESERVED RESET —...
Page 194: Instruction Cache Address Register
Freescale Semiconductor, Inc. Instruction Cache CCER1—Instruction Cache Error Type 1 This field is sticky and set by the hardware. It is read-only and cleared when read. 0 = No Error. 1 = Error. CCER2—Instruction Cache Error Type 2 This field is sticky and set by the hardware. It is read-only and cleared when read.
Page 195: Instruction Cache Data Port Register
Freescale Semiconductor, Inc. Instruction Cache 9.2.3 Instruction Cache Data Port Register The instruction cache data port register (IC_DAT) contains data that is received from the instruction cache. IC_DAT FIELD RESET — FIELD RESET — NOTE: — = Undefined. DAT—Data This field represents the data received when reading information from the instruction cache.
Page 196: Instruction Cache Miss
Freescale Semiconductor, Inc. Instruction Cache 9.3.2 Instruction Cache Miss When an instruction cache miss occurs, the address of the missed instruction is driven on the internal bus with a 4-word burst transfer read request. A cache line is then selected to receive the data that will be coming from the bus.
Page 197: Invalidating The Instruction Cache
Freescale Semiconductor, Inc. Instruction Cache Some commands may take some time to generate errors. In the current implementation, LOAD & LOCK is the only command to which this applies. Therefore, when executing these commands, you must insert an isync instruction immediately after the instruction cache command and check the error status in the IC_CST after the isync.
Page 198: Loading And Locking The Instruction Cache
Freescale Semiconductor, Inc. Instruction Cache 9.4.2 Loading and Locking the Instruction Cache The LOAD & LOCK command is used to lock critical code segments in the instruction cache. This operation is privileged and any attempt to perform it when the core is in the problem state (MSR = 1) results in a program interrupt.
Page 199: Unlocking The Entire Instruction Cache
Freescale Semiconductor, Inc. Instruction Cache 9.4.4 Unlocking the Entire Instruction Cache The UNLOCK ALL command is used to unlock the entire instruction cache. This operation is privileged and any attempt to perform it when the core is in the problem state (MSR results in a program interrupt.
Page 200: Instruction Cache Read
Freescale Semiconductor, Inc. Instruction Cache 9.4.6 Instruction Cache Read The MPC823 allows you to read all data stored in the instruction cache, including the content of the tags array. However, this operation is privileged and any attempt to perform it when the core is in the problem state (MSR =1) results in a program interrupt.
Page 201 Freescale Semiconductor, Inc. Instruction Cache SET—Set Select This field is used to select the set index of the cache array. WORD—Word Select This field is used to select a word within a set and way. Bits 30–31—Reserved These bits are reserved and must be set to 0.
Page 202: Instruction Cache Write
Freescale Semiconductor, Inc. Instruction Cache Bits 25–31—Reserved These bits are reserved and must be set to 0. 9.4.7 Instruction Cache Write Instruction cache write is only enabled when the MPC823 is in test mode. 9.5 RESTRICTIONS Zero wait state devices that are placed on the internal bus are considered to be in the cache-inhibited memory region and the hardware correct operation trusts the software to follow the exact steps mentioned in Section 9.7 Updating Code And Memory Region...
Page 203: Fetching Instructions From The Development Port
Freescale Semiconductor, Inc. Instruction Cache LRU bits are updated. Therefore, in the simple case of the debug routine it is read from memory like any other miss. However, for performance reasons, it might be preferable to run the debug routine from the cache. Follow these steps with little variation: 1.
Page 204: Data Cache
Freescale Semiconductor, Inc. SECTION 10 DATA CACHE The MPC823 data cache is a 1K two-way, set-associative cache. It is organized into 32 sets, two lines per set and four words per line. Cache lines are aligned on 4-word boundaries in memory and can be used as an SRAM that allows the application to lock critical data segments that need a fast and deterministic execution time.
Page 205 Freescale Semiconductor, Inc. Data Cache 10.2 ORGANIZATION OF THE DATA CACHE The data cache is a 1K two-way, set associative, physically addressed cache that has 16-byte line and a 32-bit data path to and from the load/store unit, which allows for a 4-byte transfer per cycle.
Page 206 Freescale Semiconductor, Inc. Data Cache ADDRESS [23:27] CACHE DECODER ARRAY WORD SELECT STREAM 4->1 WORDS WORDS DIRTY BURST 2->1 BUFFER BUFFER DATA BYPASS 2->1 DATA INTERNAL BUS DATA TO CORE Figure 10-2. Cache Data Path Block Diagram 10.3 PROGRAMMING THE DATA CACHE 10.3.1 PowerPC Architecture Instructions...
Page 207 Freescale Semiconductor, Inc. Data Cache 10.3.1.2 P PC VIRTUAL ENVIRONMENT ARCHITECTURE (BOOK II) OWER The data cache supports the following instructions: • Data cache block flush ( dcbf ) • Data cache block store ( dcbst ) • Data cache block touch (dcbt) •...
Page 208 Freescale Semiconductor, Inc. Data Cache 10.3.3.1 DATA CACHE CONTROL AND STATUS REGISTER. The data cache control and status register (DC_CST) is used to configure and access the status of the data cache. DC_CST FIELD DFWT RESERVED CCER1 CCER2 CCER3 RESERVED...
Page 209 Freescale Semiconductor, Inc. Data Cache Bits 3, 8, and 9—Reserved These bits are reserved and must be set to 0. CMD—Command The following commands can be written to the CMD field to control and configure the data cache. The machine must be in privilege mode (MSR =1).
Page 210 Freescale Semiconductor, Inc. Data Cache 10.3.3.2 DATA CACHE ADDRESS REGISTER. The data cache address register (DC_ADR) contains the address to be used in the command programmed in the CMD field of the DC_CST. It also may contain the internal address for the read tags and register operation.
Page 211 Freescale Semiconductor, Inc. Data Cache The DC_ADR must be configured into the following fields before the internal parts of the data cache are read from the DC_DAT register. DC_ADR (CACHE READ COMMAND FORMAT) FIELD RESERVED RESET — FIELD RESERVED RESERVED...
Page 212 Freescale Semiconductor, Inc. Data Cache When reading from the DC_DAT register, the 23 bits of the tag (and related information) that is selected by the DC_ADR are placed in the targeted general-purpose register. The following table illustrates the DC_DAT register’s bit layout when reading a tag. Writing to DC_DAT is illegal and can result in an undefined data cache state.
Page 213 Freescale Semiconductor, Inc. Data Cache 10.4 OPERATING THE DATA CACHE The data cache is a three-state design. Two bits are included in each cache line to maintain the line’s state information. The status bits keep track of whether or not the line is valid or if it has been modified relative to memory.
Page 214: Copyback Mode
Freescale Semiconductor, Inc. Data Cache 10.4.2.1 COPYBACK MODE In copyback mode, write operations do not necessarily update the external memory. For this reason, copyback mode is the preferred mode of operation when it is necessary to keep bus bandwidth usage and power consumption at a minimum. The possible outcomes of a data cache write in copyback mode are: •...
Page 215: Writethrough Mode
Freescale Semiconductor, Inc. Data Cache 10.4.2.2 WRITETHROUGH MODE. In writethrough mode, store operations always update memory. This mode is used when external memory and internal cache images must agree. It gives a lower worst-case interrupt latency at the expense of average performance (for example, if it does not have to do flush accesses).
Page 216: Flushing And Invalidating The Cache
Freescale Semiconductor, Inc. Data Cache 10.4.5 Data Cache Coherency The MPC823 data cache provides no support for snooping external bus activity. All coherency between the internal caches and memory/devices external to the extended core must be controlled by the software. In addition, there is no mechanism provided for DMA or other internal masters to access the data cache directly.
Page 217: Dcbi, Dcbst, Dcbf And Dcbz Instructions
Freescale Semiconductor, Inc. Data Cache 10.5.4 Data Cache Instructions 10.5.4.1 dcbi, dcbst, dcbf AND dcbz INSTRUCTIONS The dcbz, dcbi, dcbst, and dcbf instructions operate on a block basis of cache line, which is 16 bytes (4 words) long. A data TLB miss exception is generated if the effective address of one of these instructions cannot be translated and data address relocation is enabled.
Page 218: Memory Management Unit
Freescale Semiconductor, Inc. SECTION 11 MEMORY MANAGEMENT UNIT The MPC823 implements a virtual memory management scheme that provides cache control, storage access protection, and effective-to-real address translation. This implementation includes separate instruction and data memory management units. The MPC823 memory management unit is compliant with the PowerPC Microprocessor Family:...
Page 219: Address Translation
Freescale Semiconductor, Inc. Memory Management Unit 11.2 ADDRESS TRANSLATION The MPC823 core generates 32-bit effective addresses and, when enabled, the memory management unit translates the effective address to a real address that is used for cache or memory access. If disabled, the effective address is passed as the real address to the memory, which bypasses the appropriate translation lookaside buffer.
Page 220: Protection
Freescale Semiconductor, Inc. Memory Management Unit A successful TLB hit occurs if the incoming effective address matches the EPN stored in a valid TLB entry and the CASID value stored in the M_CASID register matches the entry’s ASID field. At the same time, the subpage validity flag is set for the subpage pointed to by the incoming effective address.
Page 221: Storage Control
Freescale Semiconductor, Inc. Memory Management Unit Each TLB entry holds an access protection group (APG) number. When a match is detected, the value of the matched entry’s APG is used to index a field in the access protection register that defines access control for the translation. The access protection register contains 16 fields.
Page 222: Translation Table Structure
Freescale Semiconductor, Inc. Memory Management Unit 11.5 TRANSLATION TABLE STRUCTURE The MPC823 memory management unit includes special hardware to assist in a two-level software tablewalk. Other table structures are not precluded. Figure 11-2 and Figure 11-3 illustrate the two levels of translation table structures supported by MPC823 special hardware.
Page 223 Freescale Semiconductor, Inc. Memory Management Unit EFFECTIVE ADDRESS LEVEL 1 INDEX LEVEL 2 INDEX PAGE OFFSET LEVEL ONE TABLE POINTER LEVEL ONE TABLE BASE LEVEL 1 INDEX LEVEL ONE TABLE LEVEL ONE DESCRIPTOR 0 LEVEL ONE DESCRIPTOR 1 LEVEL ONE DESCRIPTOR N...
Page 224 Freescale Semiconductor, Inc. Memory Management Unit EFFECTIVE ADDRESS 11 12 LEVEL 1 INDEX LEVEL 2 INDEX PAGE OFFSET LEVEL ONE TABLE POINTER LEVEL ONE TABLE BASE LEVEL 1 INDEX LEVEL ONE TABLE LEVEL ONE DESCRIPTOR 0 LEVEL ONE DESCRIPTOR 1...
Page 225 Freescale Semiconductor, Inc. Memory Management Unit During the memory management unit’s address translation, the most-significant bits of the missed effective address are replaced by the real page address bits from the level two page descriptor. The number of replaced bits depends on the page size. The rest of the real address bits are taken directly from the effective address.
Page 226: Level One Descriptor
Freescale Semiconductor, Inc. Memory Management Unit 11.5.1 Level One Descriptor The following table describes the hardware-assisted level one descriptor format that minimizes the software tablewalk routine. LEVEL ONE DESCRIPTOR FORMAT FIELD L2BA RESET — ADDR SYSTEM MEMORY XXXXX0000 FIELD L2BA...
Page 227: Level Two Descriptor
Freescale Semiconductor, Inc. Memory Management Unit V—Valid 0 = Segment is not valid. 1 = Segment is valid. 11.5.2 Level Two Descriptor The following table describes the hardware-assisted level two descriptor format that minimizes the software tablewalk routine. LEVEL TWO DESCRIPTOR FORMAT...
Page 228 Freescale Semiconductor, Inc. Memory Management Unit PAGES OVER 4K WITH 4K RESOLUTION PROTECTION (EXTENDED ENCODING) INSTRUCTION PAGES DATA PAGES SETTING PRIVILEGED MODE PROBLEM MODE PRIVILEGED MODE PROBLEM MODE No access No access No access No access Executable No access Read-only...
Page 229 Freescale Semiconductor, Inc. Memory Management Unit PP2 SETTING PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP1 contains PowerPC encoding PP1 contains Extended Encoding Page is writable Page is write-protected PP3—Protection for the Third 1K Subpage in a 4K Page This field contains protection code for the third subpage in a 4K page. Depending on the encoding mode, this field has different meanings.
Page 230 Freescale Semiconductor, Inc. Memory Management Unit PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP3 SETTING CASE: Mx_CTR (PPCS) = 1 No hit for any state Hit only for problem accesses Hit only for privilege accesses Hit for both problem and privilege accesses PP4—Protection for the Fourth 1K Subpage in a 4K Page...
Page 231 Freescale Semiconductor, Inc. Memory Management Unit PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP4 SETTING CASE: Mx_CTR (PPCS) = 1 Must be zero Reserved Reserved Reserved LPS—Large Page Size This bit must be set to 0 for 1K resolution protection.
Page 232: Programming The Memory Management Unit
Freescale Semiconductor, Inc. Memory Management Unit 11.6 PROGRAMMING THE MEMORY MANAGEMENT UNIT The memory management unit implements specific operations using control and status registers, which can be accessed with the PowerPC mtspr/mfspr instructions. In addition, the PowerPC tlbie and tlbia architecture instructions are supported. The memory...
Page 233: Control Registers
Freescale Semiconductor, Inc. Memory Management Unit 11.6.1 Control Registers 11.6.1.1 MMU INSTRUCTION CONTROL REGISTER. The MMU instruction control register (MI_CTR) is a special register that is used to control the operation of the instruction memory management unit. MI_CTR FIELD CIDEF...
Page 234: Mmu Data Control Register
Freescale Semiconductor, Inc. Memory Management Unit ITLB_INDX—Instruction TLB Index This field acts as a pointer to the instruction TLB entry to be loaded. It is automatically decremented at every instruction translation lookaside buffer update. Bits 24–31—Reserved These bits are reserved and must be set to 0. Ignored on write and returns a 0 on read.
Page 235: Mmu Current Address Space Id Register
Freescale Semiconductor, Inc. Memory Management Unit TWAM—Tablewalk Assist Mode 0 = 1K subpage hardware assist. 1 = 4K page hardware assist. PPCS—Privilege/Problem State Compare Mode 0 = Ignore problem/privilege state during address compare. 1 = Consider problem/privilege state according to MD_RPN[24:27].
Page 236: Mmu Instruction Effective Page Number Register
Freescale Semiconductor, Inc. Memory Management Unit 11.6.1.4 MMU INSTRUCTION EFFECTIVE PAGE NUMBER REGISTER. The MMU instruction effective page number (MI_EPN) register contains the effective address to be loaded into a TLB entry. MI_EPN FIELD RESET ADDR SPR 787 FIELD RESERVED...
Page 237: Mmu Data Effective Page Number Register
Freescale Semiconductor, Inc. Memory Management Unit 11.6.1.5 MMU DATA EFFECTIVE PAGE NUMBER REGISTER. The MMU data effective page number (MD_EPN) register contains the effective address to be loaded into a TLB entry. MD_EPN FIELD RESET — ADDR SPR 795 FIELD...
Page 238: Mmu Instruction Real Page Number Register
Freescale Semiconductor, Inc. Memory Management Unit 11.6.1.6 MMU INSTRUCTION REAL PAGE NUMBER REGISTER. The MMU instruction real page number (MI_RPN) register contains the physical address and the storage attributes of an entry to be loaded into a translation lookaside buffer. This register must be written after the MI_EPN and MI_TWC registers are written.
Page 239 Freescale Semiconductor, Inc. Memory Management Unit PAGES OVER 4K WITH 4K RESOLUTION PROTECTION (EXTENDED ENCODING) INSTRUCTION PAGES SETTING PRIVILEGED MODE PROBLEM MODE No access No access Executable No access Reserved Reserved Reserved Reserved PAGES OVER 4K WITH 4K RESOLUTION PROTECTION...
Page 240 Freescale Semiconductor, Inc. Memory Management Unit PP2 SETTING PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP1 contains PowerPC encoding PP1 contains Extended Encoding Page is writable Page is write-protected PP3—Protection for the Third 1K Subpage in a 4K Page This field contains protection code for the third subpage in a 4K page. Depending on the encoding mode, this field has different meanings.
Page 241 Freescale Semiconductor, Inc. Memory Management Unit PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP3 SETTING CASE: MI_CTR (PPCS) = 1 No hit for any state Hit only for problem accesses Hit only for privilege accesses Hit for both problem and privilege accesses PP4—Protection for the Fourth 1K Subpage in a 4K Page...
Page 242 Freescale Semiconductor, Inc. Memory Management Unit PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP4 SETTING CASE: MI_CTR (PPCS) = 1 Must be zero Reserved Reserved Reserved LPS—Large Page Size This bit must be set to 0 for 1K resolution protection.
Page 243: Mmu Data Real Page Number Register
Freescale Semiconductor, Inc. Memory Management Unit 11.6.1.7 MMU DATA REAL PAGE NUMBER REGISTER. The MMU data real page number (MD_RPN) register contains the physical address and the storage attributes of an entry to be loaded into a translation lookaside buffer. This register must be written after the MD_EPN and MD_TWC registers.
Page 244 Freescale Semiconductor, Inc. Memory Management Unit PAGES OVER 4K WITH 4K RESOLUTION PROTECTION (EXTENDED ENCODING) DATA PAGES SETTING PRIVILEGED MODE PROBLEM MODE No access No access Read-only No access Reserved Reserved Reserved Reserved PAGES OVER 4K WITH 4K RESOLUTION PROTECTION...
Page 245 Freescale Semiconductor, Inc. Memory Management Unit PP2 SETTING PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP1 contains PowerPC encoding PP1 contains Extended Encoding Page is writable Page is write-protected PP3—Protection for the Third 1K Subpage in a 4K Page This field contains protection code for the third subpage in a 4K page. Depending on the encoding mode, this field has different meanings.
Page 246 Freescale Semiconductor, Inc. Memory Management Unit PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP3 SETTING CASE: MD_CTR (PPCS) = 1 No hit for any state Hit only for problem accesses Hit only for privilege accesses Hit for both problem and privilege accesses PP4—Protection for the Fourth 1K Subpage in a 4K Page...
Page 247 Freescale Semiconductor, Inc. Memory Management Unit PAGES OVER 4K WITH 4K RESOLUTION PROTECTION PP4 SETTING CASE: MD_CTR (PPCS) = 1 Must be zero Reserved Reserved Reserved LPS—Large Page Size This bit must be set to 0 for 1K resolution protection.
Page 248: Mmu Instruction Access Protection Register
Freescale Semiconductor, Inc. Memory Management Unit 11.6.1.8 MMU INSTRUCTION ACCESS PROTECTION REGISTER. The MMU instruction access protection (MI_AP) register contains the access protection group for the instruction memory management unit. MI_AP FIELD RESET — — — — — — —...
Page 249: Mmu Data Access Protection Register
Freescale Semiconductor, Inc. Memory Management Unit 11.6.1.9 MMU DATA ACCESS PROTECTION REGISTER. The MMU data access protection (MD_AP) register contains the access protection group for the data memory management unit. MD_AP FIELD RESET — — — — — — —...
Page 250: Mmu Instruction Tablewalk Control Register
Freescale Semiconductor, Inc. Memory Management Unit 11.6.1.10 MMU INSTRUCTION TABLEWALK CONTROL REGISTER. The MMU instruction tablewalk control (MI_TWC) register contains the access protection group and page size of the entry to be loaded into the translation lookaside buffer. MI_TWC FIELD...
Page 251: Mmu Data Tablewalk Control Register
Freescale Semiconductor, Inc. Memory Management Unit V—Entry Valid Default value on instruction TLB miss is 1. 0 = Entry is not valid. 1 = Entry is valid. 11.6.1.11 MMU DATA TABLEWALK CONTROL REGISTER. The MMU data tablewalk control (MD_TWC) register contains the second level pointer and access protection group of an entry to be loaded into the translation lookaside buffer.
Page 252 Freescale Semiconductor, Inc. Memory Management Unit When read, this bit returns MD_EPN[10:19] when MD_CTR = 1 and MD_EPN[12:21] TWAM when MD_CTR = 0. TWAM PS—Page Size When written, this field has the following settings and is set to 0 on a data TLB miss. When this field is read, it returns a zero.
Page 253: Mmu Tablewalk Base Register
Freescale Semiconductor, Inc. Memory Management Unit 11.6.1.12 MMU TABLEWALK BASE REGISTER. The MMU tablewalk base (M_TWB) register contains a pointer to the level one table to be used in hardware-assisted tablewalk mode. M_TWB FIELD L1TB RESET — ADDR SPR 796...
Page 254: Mmu Tablewalk Special Register
Freescale Semiconductor, Inc. Memory Management Unit 11.6.1.13 MMU TABLEWALK SPECIAL REGISTER. The MMU tablewalk special (M_TW) register is used as a scratch register in the software tablewalk interrupt handler. M_TW RESET M_TW ADDR SPR 799 RESET M_TW ADDR SPR 799 NOTE: —...
Page 255: Mmu Data Cam Entry Read Register
Freescale Semiconductor, Inc. Memory Management Unit 11.6.2.1 MMU DATA CAM ENTRY READ REGISTER. When the content-addressable memory of the MMU data CAM entry read (MD_CAM) register is read, it contains the effective address and page sizes of an entry indexed by the DTLB_INDX field of the MD_CTR.
Page 256: Mmu Data Ram Entry Read Register 0
Freescale Semiconductor, Inc. Memory Management Unit PS—Page Size 000 = 4K. 001 = 16K. 011 = 512K. 111 = 8M. 010 = Reserved. 100 = Reserved. 101 = Reserved. 110 = Reserved. SH—Shared Page 0 = This entry matches only if the ASID field in the data TLB entry matches the value of the M_CASID register.
Page 257 Freescale Semiconductor, Inc. Memory Management Unit PS—Page Size 000 = 4K. 001 = 16K. 011 = 512K. 111 = 8M. 010 = Reserved. 100 = Reserved. 101 = Reserved. 110 = Reserved. APGI—Access Protection Group Inverted This field is an inversion of the access protection group in the MD_TWC register.
Page 258: Mmu Data Ram Entry Read Register 1
Freescale Semiconductor, Inc. Memory Management Unit 11.6.2.3 MMU DATA RAM ENTRY READ REGISTER 1. The MMU data RAM entry read register 1 (MD_RAM1) contains the protection mode information of the entry indexed by the DTLB_INDX field of the MD_CTR. This register is only updated when you write a value to it.
Page 259 Freescale Semiconductor, Inc. Memory Management Unit SA—Privileged (Supervisor) Access For Bit 19: 0 = Subpage 0 (address[20:21]=00) privileged access is not permitted. 1 = Subpage 0 (address[20:21]=00) privileged access is permitted. For Bit 20: 0 = Subpage 1 (address[20:21]=01) privileged access is not permitted.
Page 260: Mmu Instruction Content-Addressable Registers
Freescale Semiconductor, Inc. Memory Management Unit UWP3—Problem (User) Write Permission Page Three 0 = Subpage 3 (address[20:21]=11) problem write access is not permitted. 1 = Subpage 3 (address[20:21]=11) problem write access is permitted. 11.6.3 MMU Instruction Content-Addressable Registers The MI_CAM, MI_RAM0, and MI_RAM1 registers are interface registers that allow you to read the data memory management unit CAM and RAM entries.
Page 261 Freescale Semiconductor, Inc. Memory Management Unit PS—Page Size 000 = 4K. 001 = 16K. 011 = 512K. 111 = 8M. 010 = Reserved. 100 = Reserved. 101 = Reserved. 110 = Reserved. ASID—Address Space ID This field represents the data TLB entry to be compared with the CASID field in the M_CASID register.
Page 262: Mmu Instruction Ram Entry Read Register 0
Freescale Semiconductor, Inc. Memory Management Unit 11.6.3.2 MMU INSTRUCTION RAM ENTRY READ REGISTER 0. The MMU instruction RAM entry read register 0 (MI_RAM0) contains the physical page number and page attributes of an entry indexed by the ITLB_INDX field of the MI_CTR. This register is only updated when you write to the MI_CAM register.
Page 263: Mmu Instruction Ram Entry Read Register 1
Freescale Semiconductor, Inc. Memory Management Unit SFP—Privileged (Supervisor) Fetch Permission Bit 28: 0 = Subpage 0 (address[20:21]=00) privileged fetch is not permitted. 1 = Subpage 0 (address[20:21]=00) privileged fetch is permitted. Bit 29: 0 = Subpage 1 (address[20:21]=01) privileged fetch is not permitted.
Page 264: Interrupts
Freescale Semiconductor, Inc. Memory Management Unit UFP—Problem (User) Fetch Permission Bit 26: 0 = Subpage 0 (address[20:21]=00) problem fetch is not permitted. 1 = Subpage 0 (address[20:21]=00) problem fetch is permitted. Bit 27: 0 = Subpage 1 (address[20:21]=01) problem fetch is not permitted.
Page 265: Implementation-Specific Instruction Tlb Error
Freescale Semiconductor, Inc. Memory Management Unit 11.7.3 Implementation-Specific Instruction TLB Error The implementation-specific instruction TLB error interrupt occurs under one of the following conditions: • The effective address cannot be translated. Either the segment or page valid bit of this page is cleared in the translation table.
Page 266: Manipulating The Translation Lookaside Buffer
Freescale Semiconductor, Inc. Memory Management Unit 11.8 MANIPULATING THE TRANSLATION LOOKASIDE BUFFER 11.8.1 Reloading the Translation Lookaside Buffer The TLB reload (tablewalk) function is performed in the software with optional hardware assistance in the following ways: • Automatically stores the missed effective data or instruction address and default attributes in the MI_EPN or MD_EPN registers, respectively.
Page 267: Translation Reload Examples
Freescale Semiconductor, Inc. Memory Management Unit 11.8.1.1 TRANSLATION RELOAD EXAMPLES. The following are code examples for generating the real page number using a two-level tree page table structure. The first example is for a data TLB reload and the second is for an instruction TLB reload. Notice that the following assumptions are made: •...
Page 268: Controlling The Tlb Replacement Counter
Freescale Semiconductor, Inc. Memory Management Unit 11.8.2 Controlling the TLB Replacement Counter The TLB replacement counter can be programmed to only select among the first six entries in each translation lookaside buffer by setting the RSV2I bit in the MI_CTR or the RSV2D bit in the MD_CTR.
Page 269: Requirements For Accessing The Memory Management Unit Control Registers
Freescale Semiconductor, Inc. Memory Management Unit 11.9 REQUIREMENTS FOR ACCESSING THE MEMORY MANAGEMENT UNIT CONTROL REGISTERS All instruction and data memory management unit control registers must be accessed when instruction and data address translation is turned off. Prior to an mtspr MD_DBCAM receive instruction, an eieio instruction must be placed and executed before you write to the Mx_CAM register.
Page 270: System Interface Unit
Freescale Semiconductor, Inc. SECTION 12 SYSTEM INTERFACE UNIT The system interface unit controls system startup, initialization, operation, and protection, as well as the external system bus. The system configuration and protection function controls the overall system and provides various monitors and timers, including the bus ™...
Page 271: Features
Freescale Semiconductor, Inc. System Interface Unit 12.1 FEATURES The following is a list of the system interface unit’s main features: • System Configuration and Protection • System Interrupt Configuration • System Reset Monitoring and Generation • Clock Synthesizer • Power Management •...
Page 272 Freescale Semiconductor, Inc. System Interface Unit • Periodic Interrupt Timer —Generates periodic interrupts to be used with the real-time operating system or the application software. The periodic interrupt timer is clocked by the PITRTCLK clock, thus providing a period from 122 microseconds to 8,000 milliseconds assuming a 32.768kHz crystal.
Page 273 Freescale Semiconductor, Inc. System Interface Unit Figure 12-1 illustrates a block diagram of the system configuration and protection logic. MODULE CONFIGURATION MONITOR PERIODIC INTERRUPT INTERRUPT TIMER SOFTWARE INTERRUPT OR WATCHDOG TIMER SYSTEM RESET POWERPC CLOCK INTERRUPT DECREMENTER POWERPC INTERRUPT TIMEBASE COUNTER...
Page 274: Interrupt Configuration
Freescale Semiconductor, Inc. System Interface Unit 12.3 INTERRUPT CONFIGURATION Many aspects of MPC823 system configuration are controlled by the SIU module configuration register (SIUMCR). The SIUMCR primarily controls the external bus arbitration logic, external master support, and pin multiplexing. See Section 12.12.1.1 SIU Module Configuration Register for more information.
Page 275: Priority Of The Interrupt Sources
Freescale Semiconductor, Inc. System Interface Unit Notice that the core takes the system reset interrupt when a nonmaskable interrupt is asserted and the external interrupt when any other interrupt is asserted by the interrupt controller. Each one of the external IRQx pins has its own dedicated assigned priority level and there are eight additional interrupt priority levels.
Page 276: Programming The Interrupt Controller
Freescale Semiconductor, Inc. System Interface Unit 12.3.3 Programming the Interrupt Controller The system interface unit’s interrupt controller consists of the SIPEND, SIMASK, SIEL and SIVEC registers. 12.3.3.1 SIU INTERRUPT PENDING REGISTER. The 32-bit SIU interrupt pending (SIPEND) register contains bits that individually correspond to an interrupt request. If they are set, the bits associated with internal exceptions indicate that an interrupt service is requested, if they are not masked by the corresponding bit in the SIMASK register.
Page 277: Siu Interrupt Mask Register
Freescale Semiconductor, Inc. System Interface Unit Bits 16–31—Reserved These bits are reserved and must be set to 0. 12.3.3.2 SIU INTERRUPT MASK REGISTER. The 32-bit read/write SIU interrupt mask (SIMASK) register contains bits that individually correspond to the interrupt request bits in the SIPEND register.
Page 278: Siu Interrupt Edge/Level Register
Freescale Semiconductor, Inc. System Interface Unit LVM—Level Mask 0–7 When set, these bits enable a LEVELx interrupt request from an internal source to be generated. The SIPEND register contains the corresponding LVLx bits. See Figure 12-2 for more information. 0 = Disable the generation of an IRQx bit in the SIPEND register.
Page 279: Siu Interrupt Vector Register
Freescale Semiconductor, Inc. System Interface Unit Bits 16–31—Reserved These bits are reserved and must be set to 0. 12.3.3.4 SIU INTERRUPT VECTOR REGISTER. The 32-bit read-only SIU interrupt vector (SIVEC) register contains an 8-bit code that represents the unmasked interrupt source of the highest priority level.
Page 280: The Bus Monitor
Freescale Semiconductor, Inc. System Interface Unit INTR: • • • INTR: • • • Save state Save state R3 <- @ SIVEC R3 <- @ SIVEC R4 <-- Base of branch table R4 <-- Base of branch table • • •...
Page 281: The Powerpc Decrementer
Freescale Semiconductor, Inc. System Interface Unit 12.5 THE POWERPC DECREMENTER The 32-bit decrementing counter is defined by the PowerPC architecture to provide a decrementer interrupt. This binary counter is clocked by the same frequency as the timebase. In the MPC823, the decrementer is clocked by the TMBCLK clock, so you must enable the TBE bit in the TBSCR for the decrementer to start.
Page 282: Decrementer Register
Freescale Semiconductor, Inc. System Interface Unit 12.5.1 Decrementer Register The 32-bit decrementer (DEC) register is a special-purpose register defined by PowerPC architecture. The decrementer causes an interrupt whenever Bit 0 changes from a logic 0 to a logic 1. The contents of this register can be read or written to by the mfspr or mtspr instruction.
Page 283: The Powerpc Timebase
Freescale Semiconductor, Inc. System Interface Unit 12.6 THE POWERPC TIMEBASE The timebase is defined by the PowerPC architecture and is a 64-bit free-running binary counter that is incremented at a frequency determined by each implementation of the timebase. There is no interrupt or other indication generated when the count rolls over. The period of the timebase depends on the driving frequency.
Page 284: Timebase Reference Registers
Freescale Semiconductor, Inc. System Interface Unit TB-LOWER FIELD RESET — 268 (READ), 284 (WRITE) FIELD RESET 268 (READ), 284 (WRITE) NOTE: — = Undefined. TBL—Timebase Lower The value stored in this field is used as the lower part of the timebase register.
Page 285: Timebase Status And Control Register
Freescale Semiconductor, Inc. System Interface Unit TBREFL FIELD TBREFL RESET — ADDR (IMMR & 0xFFFF0000) + 0x208 FIELD TBREFL RESET — ADDR (IMMR & 0xFFFF0000) + 0x20A NOTE: — = Undefined. TBREFL—Timebase Reference Lower These bits represent the 32-bit reference value for the lower part of the timebase.
Page 286: The Real-Time Clock
Freescale Semiconductor, Inc. System Interface Unit Bits 10–11—Reserved These bits are reserved and must be set to 0. REFAE and REFBE—Reference Interrupt Enable If one of these bits is asserted, the timebase generates an interrupt on assertion of the REFA or REFB bit.
Page 287: Real-Time Clock Status And Control Register
Freescale Semiconductor, Inc. System Interface Unit 12.7.1 Real-Time Clock Status and Control Register The real-time clock status and control (RTCSC) register is used to enable the different real-time clock functions and for reporting the source of the interrupts. A status bit is cleared by writing a 1 (writing a zero has no effect) and more than one status bit can be cleared at a time.
Page 288: Real-Time Clock Register
Freescale Semiconductor, Inc. System Interface Unit ALE—Alarm Interrupt Enable This bit allows the real-time clock to generate an interrupt when the ALR bit is set. 0 = Disables the seconds interrupt. 1 = The real-time clock generates an interrupt. RTF—Real-Time Clock Freeze Enable 0 = The real-time clock is unaffected by the FRZ signal.
Page 289: Real-Time Clock Alarm Seconds Register
Freescale Semiconductor, Inc. System Interface Unit 12.7.3 Real-Time Clock Alarm Seconds Register The 32-bit real-time clock alarm seconds register (RTSEC) contains the value which divides the oscillator by 8,192 or 9,600 to generate one clock per second. This register is cleared when the RTC register is written.
Page 290: Real-Time Clock Alarm Register
Freescale Semiconductor, Inc. System Interface Unit 12.7.4 Real-Time Clock Alarm Register The 32-bit read/write real-time clock alarm (RTCAL) register is an alarm reference register. When the RTC register increments to the value stored in this register, an alarm interrupt is generated.
Page 291: The Periodic Interrupt Timer
Freescale Semiconductor, Inc. System Interface Unit 12.8 THE PERIODIC INTERRUPT TIMER The periodic interrupt timer consists of a 16-bit counter clocked by a PITRTCLK clock supplied by the clock module. It decrements to zero when loaded with a value from the periodic interrupt timer count register (PITC) and after the timer reaches zero, the PS bit is set and an interrupt is generated if the PIE bit is a logic 1.
Page 292: Periodic Interrupt Status And Control Register
Freescale Semiconductor, Inc. System Interface Unit 12.8.1 Periodic Interrupt Status and Control Register The read/write periodic interrupt status and control register (PISCR) contains the interrupt request level and the interrupt status bits. It also controls the 16 bits to be loaded in a modulus counter.
Page 293: Periodic Interrupt Timer Count Register
Freescale Semiconductor, Inc. System Interface Unit 12.8.2 Periodic Interrupt Timer Count Register The read/write periodic interrupt timer count (PITC) register contains a 16-bit value that will be loaded into the periodic interrupt down counter. PITC FIELD PITC RESET — ADDR (IMMR &...
Page 294: Periodic Interrupt Timer Register
Freescale Semiconductor, Inc. System Interface Unit 12.8.3 Periodic Interrupt Timer Register The periodic interrupt timer register (PITR) is a read-only register that shows the current value in the periodic interrupt down counter. Writes to this register do not affect this register and reads of this register do not have any affect on the counter.
Page 295: The Software Watchdog Timer
Freescale Semiconductor, Inc. System Interface Unit 12.9 THE SOFTWARE WATCHDOG TIMER The system interface unit provides the software watchdog timer (SWT) option that prevents system lockout when the software gets trapped in loops without a controlled exit. The software watchdog timer is enabled after system reset to automatically generate a system reset if it times out.
Page 296: Software Service Register
Freescale Semiconductor, Inc. System Interface Unit The decrementer begins counting when it is loaded with a value from the SWTC field. After the timer reaches 0x0, a software watchdog expiration request is issued to the reset or NMI control logic. At reset, the value in the SWTC register is set to the maximum value and is loaded into the software watchdog register (SWR) again, thus starting the process over.
Page 297: Freeze Operation
Freescale Semiconductor, Inc. System Interface Unit 12.10 FREEZE OPERATION When the FRZ signal is asserted, the clocks to the software watchdog, periodic interrupt timer, real-time clock, timebase counter, and decrementer can be disabled. This is controlled by the associated bits in the control register of each timer. If they are programmed to stop counting when FRZ is asserted, the counters maintain their values until FRZ is negated.
Page 298: Multiplexing The System Interface Unit Pins
Freescale Semiconductor, Inc. System Interface Unit 12.11 MULTIPLEXING THE SYSTEM INTERFACE UNIT PINS Due to the limited number of pins available in the MPC823 package, some of the functionalities share pins. The actual MPC823 pinout is illustrated in Section 2 External Signals. The following table shows how the functionality is controlled on each pin.
Page 299: Programming The System Interface Unit
Freescale Semiconductor, Inc. System Interface Unit 12.12 PROGRAMMING THE SYSTEM INTERFACE UNIT 12.12.1 System Configuration and Protection Registers 12.12.1.1 SIU MODULE CONFIGURATION REGISTER. The SIU module configuration register (SIUMCR) contains bits that configure various features in the system interface unit.
Page 300 Freescale Semiconductor, Inc. System Interface Unit DBGC—Debug Pin Configuration This field configures the debug pin functionality. The default value is set by the hard reset configuration word, as shown in Section 4.3.1.1 Hard Reset Configuration Word. 00 = IP_B[0:1]/IWP[0:1]/VFLS[0:1] functions as IP_B[0:1].
Page 301 Freescale Semiconductor, Inc. System Interface Unit TDI/DSDI functions as DSDI. TDO/DSDO functions as DSDO. 01 = ALE_B/DSCK/AT1 functions as defined by DBGC. IP_B6/DSDI/AT0 functions as defined by DBGC. OP3/MODCK2/DSDO functions as defined by DBGC. IP_B7/PTR/AT3 functions as defined by DBGC.
Page 302 Freescale Semiconductor, Inc. System Interface Unit MPRE—Multiprocessors Reservation Enable If this bit is set, then the interprocessor reservation protocol is enabled. The RSV pin functions as defined in Section 13.4.10 Storage Reservation Protocol. RSV/IRQ2 functions as IRQ2. RSV/IRQ2 functions as RSV.
Page 303: Internal Memory Map Register
Freescale Semiconductor, Inc. System Interface Unit B3DD—Bank 3 Double Drive If this bit is set, the CS3 signal is reflected on GPL_x3. 12.12.1.2 INTERNAL MEMORY MAP REGISTER. The internal memory map register (IMMR) is located within the PowerPC special register space. It contains the identification of a specific device, as well as a base for the internal memory map.
Page 304: System Protection Control Register
Freescale Semiconductor, Inc. System Interface Unit MASKNUM—Mask Number This read-only field is mask-programmed with a code corresponding to the mask number of the part on which the system interface unit is located. It is intended to help with factory test and user code that is sensitive to part refinements.
Page 305: Transfer Error Status Register
Freescale Semiconductor, Inc. System Interface Unit SWF—Software Watchdog Freeze 0 = The software watchdog timer continues counting even if the FRZ signal is asserted. 1 = The software watchdog timer stops counting when the FRZ signal is asserted. SWE—Software Watchdog Enable This bit enables the software watchdog timer.
Page 306 Freescale Semiconductor, Inc. System Interface Unit IEXT—Instruction External Transfer Error Acknowledge This bit is set if the cycle is terminated by an externally generated TEA signal when an instruction fetch is initiated. ITMT—Instruction Transfer Monitor Timeout This bit is set if the cycle is terminated by a bus monitor timeout when an instruction fetch is initiated.
Page 307: External Bus Interface
Freescale Semiconductor, Inc. SECTION 13 EXTERNAL BUS INTERFACE The MPC823 bus is synchronous and burstable. Signals driven on this bus are required to make the setup and hold time relative to the bus clock’s rising edge. This bus has the ability to support multiple masters.
Page 308 Freescale Semiconductor, Inc. External Bus Interface Furthermore, for all inputs, the MPC823 latches the level of the input during a sample window around the rising edge of the clock signal. This window is illustrated in Figure 13-1, where tsu and tho are the input setup and hold times, respectively. To ensure that an input signal is recognized on a specific falling edge of the clock, the input must be stable during the sample window.
Page 309: Control Signals
Freescale Semiconductor, Inc. External Bus Interface 13.2.1 Control Signals The MPC823 initiates a bus cycle by driving the address, size, address type, cycle type, and read/write outputs. At the beginning of a bus cycle, the TSIZ0 and TSIZ1 signals are driven with the AT signals.
Page 310: Bus Signal Descriptions
Freescale Semiconductor, Inc. External Bus Interface 13.3 BUS SIGNAL DESCRIPTIONS The following table decribes each bus interface signal. More detailed descriptions can be found in subsequent sections of this manual. Table 13-1. Bus Interface Signals MNEMONIC PINS ACTIVE DESCRIPTION ADDRESS AND TRANSFER ATTRIBUTES...
Page 311 Freescale Semiconductor, Inc. External Bus Interface Table 13-1. Bus Interface Signals (Continued) MNEMONIC PINS ACTIVE DESCRIPTION BDIP Burst Data In Progress—Driven by the MPC823 when it owns the external bus. It is part of the burst protocol. Asserted indicates that the second beat in front of the current one is requested by the master.
Page 312 Freescale Semiconductor, Inc. External Bus Interface Table 13-1. Bus Interface Signals (Continued) MNEMONIC PINS ACTIVE DESCRIPTION DP[0:3] High Parity Bus —Each parity signal corresponds to each one of the data bus lanes: Data Bus Byte Parity Line D[0:7] D[8:15] D[16:23]...
Page 313: Bus Interface Operation
Freescale Semiconductor, Inc. External Bus Interface Table 13-1. Bus Interface Signals (Continued) MNEMONIC PINS ACTIVE DESCRIPTION ARBITRATION Bus Request—When the internal arbiter is asserted, it indicates that an external master is requesting the bus. Driven by the MPC823 when the internal arbiter is disabled and the chip is not parked .
Page 314: Basic Transfers
Freescale Semiconductor, Inc. External Bus Interface 13.4.1 Basic Transfers The basic transfer protocol defines the sequence of actions that must occur on the MPC823 bus to perform a complete bus transaction. The chronological sequence or phase of a typical bus transfer is as follows: 1.
Page 315: Single Beat Read Flow
Freescale Semiconductor, Inc. External Bus Interface 13.4.2.1 SINGLE BEAT READ FLOW. The basic read cycle begins with a bus arbitration, followed by the address transfer and the data transfer. The handshakes are illustrated in the following diagrams as applicable to the fixed transaction protocol.
Page 316 Freescale Semiconductor, Inc. External Bus Interface CLKOUT RECEIVE BUS GRANT AND BUS BUSY NEGATED ASSERT BB, DRIVE ADDRESS AND ASSERT TS A[6:31] RD/WR TSIZ[0:1],AT[0:3] BURST DATA DATA IS VALID Figure 13-4. Single Beat Read Cycle–Basic Timing–Zero Wait States MPC823 REFERENCE MANUAL...
Page 317 Freescale Semiconductor, Inc. External Bus Interface CLKOUT RECEIVE BUS GRANT AND BUS BUSY NEGATED ASSERT BB, DRIVE ADDRESS AND ASSERT TS A[6:31] RD/WR TSIZ[0:1],AT[0:3] BURST DATA WAIT STATE DATA IS VALID Figure 13-5. Single Beat Read Cycle–Basic Timing–One Wait State...
Page 318: Single Beat Write Flow
Freescale Semiconductor, Inc. External Bus Interface 13.4.2.2 SINGLE BEAT WRITE FLOW. The basic write cycle begins with a bus arbitration, followed by the address transfer and the data transfer. The handshakes are illustrated in Figure 13-6, Figure 13-7, Figure 13-8, and Figure 13-9 as applicable to the fixed transaction protocol.
Page 319 Freescale Semiconductor, Inc. External Bus Interface CLKOUT RECEIVE BUS GRANT AND BUS BUSY NEGATED ASSERT BB, DRIVE ADDRESS AND ASSERT TS A[6:31] RD/WR TSIZ[0:1],AT[0:3] BURST DATA DATA IS SAMPLED Figure 13-7. Single Beat Write Cycle–Basic Timing–Zero Wait States MPC823 REFERENCE MANUAL...
Page 320 Freescale Semiconductor, Inc. External Bus Interface CLKOUT RECEIVE BUS GRANT AND BUS BUSY NEGATED ASSERT BB, DRIVE ADDRESS AND ASSERT TS A[6:31] RD/WR TSIZ[0:1],AT[0:3] BURST DATA WAIT STATE DATA IS SAMPLED Figure 13-8. Single Beat Write Cycle of One Wait State...
Page 321 Freescale Semiconductor, Inc. External Bus Interface A typical single beat transfer assumes that the external memory has a 32-bit port size. The MPC823 provides an effective mechanism for interfacing with 16-bit port size memories and 8-bit port size memories, thus allowing transfers to these devices when they are controlled by the internal memory controller.
Page 322: Burst Transfers
Freescale Semiconductor, Inc. External Bus Interface 13.4.3 Burst Transfers The MPC823 uses burst transfers to access 16-byte operands. A burst accesses a block of 16 bytes that must be aligned to a 16-byte memory boundary by supplying a starting address that points to the critical words and requiring the memory device to sequentially drive/sample each word on the data bus.
Page 323 Freescale Semiconductor, Inc. External Bus Interface MASTER SLAVE REQUEST BR RECEIVE BG FROM ARBITER ASSERT BB IF NO OTHER MASTER IS DRIVING ASSERT TS ASSERT ADDRESS AND ATTRIBUTES ASSERT BURST RECEIVE ADDRESS ASSERT BDIP RETURN DATA ASSERT TA RECEIVE DATA...
Page 324 Freescale Semiconductor, Inc. External Bus Interface CLKOUT A[6:31],AT[0:3] RD/WR TSIZ[0:1] ‘00’ BURST LAST BEAT EXPECTS ANOTHER DATA BDIP DATA ‘00’ DATA DATA DATA DATA IS VALID IS VALID IS VALID IS VALID Figure 13-11. Burst-Read Cycle–32-Bit Port Size–Zero Wait State...
Page 325 Freescale Semiconductor, Inc. External Bus Interface CLKOUT A[6:31],AT[0:3] RD/WR TSIZ[0:1] ‘00’ BURST LAST BEAT EXPECTS ANOTHER DATA BDIP DATA ‘00’ DATA DATA DATA DATA WAIT STATE IS VALID IS VALID IS VALID IS VALID Figure 13-12. Burst-Read Cycle–32-Bit Port Size–One Wait State...
Page 326 Freescale Semiconductor, Inc. External Bus Interface CLKOUT A[6:31],AT[0:3] RD/WR TSIZ[0:1] ‘00’ BURST LAST BEAT EXPECTS ANOTHER DATA BDIP DATA ‘00’ DATA DATA DATA DATA IS VALID IS VALID IS VALID IS VALID WAIT STATE Figure 13-13. Burst-Read Cycle–32-Bit Port Size–Wait States Between Beats...
Page 327 Freescale Semiconductor, Inc. External Bus Interface MASTER SLAVE REQUEST BR RECEIVE BG FROM ARBITER ASSERT BB IF NO OTHER MASTER IS DRIVING ASSERT TS ASSERT ADDRESS AND ATTRIBUTES ASSERT BURST RECEIVE ADDRESS DRIVE DATA ASSERT BDIP RECEIVE DATA ASSERT TA...
Page 328 Freescale Semiconductor, Inc. External Bus Interface CLKOUT A[6:31],AT[0:3] RD/WR TSIZ[0:1] ‘00’ BURST BDIP DATA ‘10’ Figure 13-15. Burst-Read Cycle–16-Bit Port Size–One Wait State Between Beats MPC823 REFERENCE MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 329 Freescale Semiconductor, Inc. External Bus Interface CLKOUT A[6:31],AT[0:3] RD/WR TSIZ[0:1] ‘00’ BURST LAST BEAT WILL DRIVE ANOTHER DATA BDIP DATA DATA DATA DATA DATA IS SAMPLED IS SAMPLED IS SAMPLED IS SAMPLED Figure 13-16. Burst-Write Cycle–32-Bit Port Size–Zero Wait States...
Page 330 Freescale Semiconductor, Inc. External Bus Interface CLKOUT A[6:27] A[28:29] N+1 MOD 4 N+2 MOD 4 N+3 MOD 4 A[30:31] RD/WR TSIZ[0:1] ‘00’ BURST BDIP DATA Figure 13-17. Burst-Inhibit Cycle–32-Bit Port Size MPC823 REFERENCE MANUAL MOTOROLA For More Information On This Product,...
Page 331: Transfer Alignment And Packaging
Freescale Semiconductor, Inc. External Bus Interface 13.4.5 Transfer Alignment and Packaging The MPC823 external bus only supports natural address alignment that forces the following restrictions: • Byte access can have any address alignment • Half-word access must have address bit 31 equal to 0 •...
Page 332 Freescale Semiconductor, Inc. External Bus Interface Figure 13-19 illustrates the device connections on the data bus. INTERFACE OUTPUT REGISTER D[0:7] D[8:15] D[16:23] D[24:31] 32-BIT PORT SIZE 16-BIT PORT SIZE 8-BIT PORT SIZE Figure 13-19. Interface To Different Port Size Devices Table 13-2 lists the bytes for read cycles required on the data bus.
Page 333: Arbitration Phase-Related Signals
Freescale Semiconductor, Inc. External Bus Interface Table 13-3 lists the patterns of the data transfer for write cycles when accesses are initiated by the MPC823. Table 13-3. Data Bus Contents for Write Cycles TRANSFER TSIZE INTERNAL EXTERNAL DATA BUS PATTERN...
Page 334: Bus Request Signal
Freescale Semiconductor, Inc. External Bus Interface Figure 13-20 illustrates the basic protocol for bus arbitration. For more information, see Section 12.12.1.1 SIU Module Configuration Register. REQUESTING DEVICE ARBITER REQUEST THE BUS 1. ASSERT BR GRANT BUS ARBITRATION 1. ASSERT BG ACKNOWLEDGE BUS MASTERSHIP 1.
Page 335: Bus Grant Signal
Freescale Semiconductor, Inc. External Bus Interface 13.4.6.2 BUS GRANT SIGNAL. The BG signal is asserted by the arbiter to indicate that the bus is granted to the requesting device. The BG signal can be negated after BR is negated. The current bus master may choose to keep BG asserted to park the bus and maintain ownership without rearbitrating until another master makes a request.
Page 336 Freescale Semiconductor, Inc. External Bus Interface CLKOUT ADDR + ATTR MASTER 0 MASTER 0 MASTER 1 NEGATES “TURNS ON” “TURNS ON” DRIVES DRIVES “TURNS OFF” SIGNALS SIGNALS Figure 13-22. Bus Arbitration Timing Diagram At system reset, the MPC823 can be configured to use the internal bus arbiter and it will be parked on the bus.
Page 337: Address Transfer Phase-Related Signals
Freescale Semiconductor, Inc. External Bus Interface EXT OWNER BG = 0 MPC823 INTERNAL MASTER WITH HIGHER BB = T.S EXT MASTER PRIORITY THAN THE EXTERNAL DEVICE REQUESTS BUS REQUIRES THE BUS EXT MASTER BR = 1 BB = 0 RELEASE BUS...
Page 338: Address Bus
Freescale Semiconductor, Inc. External Bus Interface 13.4.7.2 ADDRESS BUS. The 26-bit address bus consists of address bits 6–31 and Bit 6 is most-significant. The bus is byte addressable, so each address can address one or more bytes. The address and its attributes are driven on the bus with the TS signal and stay valid until the bus master received a TA signal from the slave.
Page 339: Transfer Size Signal
Freescale Semiconductor, Inc. External Bus Interface 13.4.7.3.3 Transfer Size Signal. The TSIZx signals indicate the size of the requested data transfer and they can be used with the BURST and A[30:31] signals to determine the byte lanes of the data bus that are involved in the transfer. For nonburst transfers, the TSIZx signals specify the number of bytes starting from the byte location addressed by the A[30:31] signals.
Page 340 Freescale Semiconductor, Inc. External Bus Interface MPC823 REFERENCE MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 341 Freescale Semiconductor, Inc. External Bus Interface MPC823 REFERENCE MANUAL 13-35 For More Information On This Product, Go to: www.freescale.com...
Page 342: Burst Data In Progress Signal
Freescale Semiconductor, Inc. External Bus Interface 13.4.7.3.6 Burst Data in Progress Signal. The BDIP signal is sent from the master to the slave to indicate that there is a data beat following the current data beat. The master uses this signal to give the slave advanced warning of the remaining data in the burst. By negating the BDIP signal, you can terminate a burst cycle early.
Page 343: Protocol For Termination Signals
Freescale Semiconductor, Inc. External Bus Interface 13.4.9.4 PROTOCOL FOR TERMINATION SIGNALS. The transfer protocol was defined to avoid electrical contention on signals that can be driven by various sources. To do that, a slave must not drive signals associated with the data transfer until the address phase is completed and it recognizes the address as its own.
Page 344: Storage Reservation Protocol
Freescale Semiconductor, Inc. External Bus Interface 13.4.10 Storage Reservation Protocol The MPC823 storage reservation protocol supports multilevel bus structure. For each local bus, storage reservation is handled by the local reservation logic. The protocol tries to optimize reservation cancellation so that a PowerPC processor is notified of storage reservation loss on a remote bus only when it has issued a stwcx cycle to that address.
Page 345 Freescale Semiconductor, Inc. External Bus Interface The reservation protocol for a single-level (local) bus is illustrated in Figure 13-26. It assumes that external logic on the bus performs the following functions: • Snoops accesses to all local bus slaves • Holds one reservation for each local master capable of storage reservations •...
Page 346 Freescale Semiconductor, Inc. External Bus Interface The local bus interface block implements a reservation “flag” for the local bus master. The reservation “flag” is set by the local bus interface when a load with reservation is issued by the local bus master and the reservation address is located on the remote bus. The “flag” is reset when an alternative master on the remote bus accesses the same location in a write cycle.
Page 347: Exception Control Cycles
Freescale Semiconductor, Inc. External Bus Interface 13.4.11 Exception Control Cycles The MPC823 bus architecture requires the TA signal to be asserted from an external device to indicate that the bus cycle is complete. TA is not asserted when one of the following conditions occur: •...
Page 348 Freescale Semiconductor, Inc. External Bus Interface CLKOUT BG(OUTPUT) ALLOW EXTERNAL MASTER TO GAIN THE BUS A[6:31] RD/WR TSIZ[0:1] BURST DATA RETRY Figure 13-28. RETRY Transfer Timing–Internal Arbiter MPC823 REFERENCE MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 349 Freescale Semiconductor, Inc. External Bus Interface CLKOUT BR(OUTPUT) ALLOW EXTERNAL MASTER TO GAIN THE BUS A[6:31] RD/WR TSIZ[0:1] BURST DATA RETRY Figure 13-29. RETRY Transfer Timing–External Arbiter MPC823 REFERENCE MANUAL 13-43 For More Information On This Product, Go to: www.freescale.com...
Page 350 Freescale Semiconductor, Inc. External Bus Interface When a burst access is initiated by the MPC823, the bus interface only recognizes the RETRY assertion as a retry termination if it detects it before the first data beat is acknowledged by the slave device. When the RETRY signal is asserted as a termination signal on the second or third data beat of the access, the MPC823 recognizes it as a transfer error acknowledgement.
Page 351 Freescale Semiconductor, Inc. External Bus Interface In reference to Figure 13-30, if the BI signal is asserted at the first beat of a burst, then the remaining beats of the 16-byte transfer retry are recognized as a transfer error acknowledge. Table 13-6 summarizes how the MPC823 recognizes the termination signals provided by the slave device that the initiated transfer addressed.
Page 352: Endian Modes
Freescale Semiconductor, Inc. SECTION 14 ENDIAN MODES This section will discuss how the MPC823 supports three system endian configurations: • Little-endian system • Big-endian system ™ • PowerPC little-endian system A general description of the different endian modes can be found in The PowerPC Microprocessor Family: The Programming Environments (MPCFPE/AD) manual that is available from Motorola.
Page 353 Freescale Semiconductor, Inc. Endian Modes The hardware operations that are used to support the different endian modes are: • Address munging in the core is controlled by the MSR bit. Refer to the PowerPC Microprocessor Family: The Programming Environments for 32-Bit Microprocessors manual for more information.
Page 354: Little-Endian Features
Freescale Semiconductor, Inc. Endian Modes 14.1 LITTLE-ENDIAN FEATURES The following is a list of the little-endian system’s main features: • System Memory Organization and E-Bus Format are Little-Endian • U-Bus Data, Instruction and Data Caches, and Internal Memory Format are Big-Endian •...
Page 355 Freescale Semiconductor, Inc. Endian Modes Table 14-4. Little-Endian Program/Data Path Between the Register and 16-Bit Memory FETCH/ LITTLE- U-BUS EXTERNAL DATA IN THE U-BUS AND E-BUS FORMAT LITTLE-ENDIAN LOAD ENDIAN REGISTER CACHES FORMAT PROGRAM/DATA STORE ADDRESS CACHES ADDRESS TYPE ADDRESS...
Page 356: Big-Endian System Features
Freescale Semiconductor, Inc. Endian Modes 14.2 BIG-ENDIAN SYSTEM FEATURES The following is a list of the big-endian system’s main features: • Caches, U-Bus, E-Bus, System Memory, and I/O Organization Format is Big-Endian • Same Byte Order between the Media and System Memory •...
Page 357: Memory Controller
Freescale Semiconductor, Inc. SECTION 15 MEMORY CONTROLLER The memory controller is responsible for controlling a maximum of eight memory banks shared between a general-purpose chip-select machine and a pair of sophisticated user-programmable machines. It supports a glueless interface to SRAM, EPROM, flash EPROM, regular DRAM devices, self-refresh DRAMs, extended data output DRAM devices, synchronous DRAMs, and other peripherals.
Page 358 Freescale Semiconductor, Inc. Memory Controller • Two User-Programmable Machines RAM-based machine controls the timing of the external signals with a granularity of one quarter of a system clock period User-specified patterns run when a single read access, single write access, burst...
Page 359 Freescale Semiconductor, Inc. Memory Controller ADDRESS[0:16], AT[0:2] ADDRESS LATCH MULTIPLEXER INCREMENTOR BASE REGISTER (BR) BASE REGISTER (BR) BASE REGISTER (BR) BASE REGISTER (BR) BASE REGISTER (BR) BASE REGISTER (BR) BASE REGISTER (BR) BASE REGISTER (BR) NA AND AMX FIELDS OPTION REGISTER (OR)
Page 360: Architecture
Freescale Semiconductor, Inc. Memory Controller 15.2 ARCHITECTURE The memory controller consists of three basic machines: • General-purpose chip-select machine • User-programmable machine A • User-programmable machine B As illustrated in Figure 15-2, each bank can be assigned to any one of these machines via the MS field in the base register.
Page 361 Freescale Semiconductor, Inc. Memory Controller Some features are common to all eight memory banks. The full 32-bit decode is available internally, even if all 32 address bits are not visible outside the MPC823. For external master transactions, the memory controller extends the 26-bit external address line to 32 bits and the six most-significant bits are zero.
Page 362 Freescale Semiconductor, Inc. Memory Controller The two user-programmable machines (UPMA and UPMB) in the memory controller provide a flexible interface to many types of memory devices. Each UPM can control the address multiplexing necessary to access DRAM devices, the timing of the BS signals, and the timing of the GPLx signals.
Page 363: Register Model
Freescale Semiconductor, Inc. Memory Controller INTERNAL/EXTERNAL MEMORY ACCESS REQUEST ADDRESS, ADDRESS TYPE ADDRESS COMPARATOR USER- GENERAL-PURPOSE USER- BANK SELECT PROGRAMMABLE PROGRAMMABLE CHIP-SELECT MACHINE B MACHINE MACHINE A FIELD SIGNALS SIGNALS TIMING GENERATOR TIMING GENERATOR EXTERNAL SIGNALS Figure 15-4. Basic Memory Controller Operation 15.3 REGISTER MODEL...
Page 364 Freescale Semiconductor, Inc. Memory Controller The memory controller registers are used by the general-purpose chip-select machine and the user-programmable machines as specified in Table 15-1. See Section 15.3.1 Register Descriptions for specific register information. Table 15-1. Memory Controller Register Usage...
Page 365: Register Descriptions
Freescale Semiconductor, Inc. Memory Controller 15.3.1 Register Descriptions 15.3.1.1 BASE REGISTERS. The base registers (BR0-7) contain the base address and address types that are used by the memory controller to compare the address bus with the current address accessed. It also includes a memory attribute and selects the machine for memory operation handling.
Page 366 Freescale Semiconductor, Inc. Memory Controller BA—Base Address This field, the upper 17 bits of each base address register, and the AT field are compared to the address on the address bus to determine if a memory bank controlled by the memory controller is being accessed by an internal bus master.
Page 367 Freescale Semiconductor, Inc. Memory Controller Bits 26–30—Reserved These bits are reserved and must be set to 0. V—Valid This bit indicates that the contents of the base and option registers are valid. The CSx signal does not assert until this bit is set. An access to a region that does not have this bit set can cause a bus monitor timeout.
Page 368 Freescale Semiconductor, Inc. Memory Controller OR x FIELD RESET ADDR (IMMR & 0xFFFF0000) + 0x104 (OR0), 0x10C (OR1), 0x114 (OR2), 0x11C (OR3), 0x124 (OR4),0x12C (OR5), 0x134 (OR6), 0x13C (OR7) CSNT/ FIELD ACS/G5LA,G5LS SETA TRLX EHTR RESET ADDR (IMMR & 0xFFFF0000) + 0x106 (OR0), 0x10E (OR1), 0x116 (OR2), 0x11E (OR3), 0x126 (OR4), 0x12E (OR5), 0x136 (OR6), 0x13E (OR7) NOTE: The reset value of OR0 has predefined values as shown in the boot OR0 register table.
Page 369 Freescale Semiconductor, Inc. Memory Controller ACS—Address to Chip-Select Setup/G5LA This field is used for the GPCM and the G5LA and G5LS fields are used for the UPM. This field controls CSx signal assertion in relation to address lines valid. 00 = CSx is output at the same time as the address lines.
Page 370 Freescale Semiconductor, Inc. Memory Controller If you want to use an external TA response (SETA bit = 1), then these bits are not used. 0000 = 0 clock cycle wait state. 0001 = 1 clock cycle wait state. 0010 = 2 clock cycle wait states.
Page 371 Freescale Semiconductor, Inc. Memory Controller EHTR—Extended Hold Time on Read When this bit is set, it adds one clock cycle after a read from the current bank and any CPU write or read to a different bank. 0 = Timing is defined by the memory controller.
Page 372 Freescale Semiconductor, Inc. Memory Controller PER6—Parity Error Bank 6 When this bit is set it indicates that a parity error was detected during a Bank 6 read cycle initiated by the memory controller. PER7—Parity Error Bank 7 When this bit is set it indicates that a parity error was detected during a Bank 7 read cycle initiated by the memory controller.
Page 373 Freescale Semiconductor, Inc. Memory Controller 15.3.1.4 MEMORY COMMAND REGISTER. The memory command register (MCR) allows you to issue commands to stimulate UPM routine execution. This capability enables the CPU to perform special memory operations in addition to the standard read/write and periodic timer service operations.
Page 374 Freescale Semiconductor, Inc. Memory Controller MB—Memory Bank This field selects the appropriate CSx pin when a RUN command is executed. 000 = CS0 is selected. 001 = CS1 is selected. 010 = CS2 is selected. 011 = CS3 is selected.
Page 375 Freescale Semiconductor, Inc. Memory Controller 15.3.1.5 MACHINE A MODE REGISTER. The machine A mode register (MAMR) contains the configuration for the user-programmable machine A. See Figure 15-1 (page 15-3) for more information. MAMR FIELD PTAE RESET ADDR (IMMR & 0xFFFF0000) + 0x170...
Page 376 Freescale Semiconductor, Inc. Memory Controller PTAE—Periodic Timer A Enable This bit allows the periodic timer A to request service. 0 = Periodic timer A is disabled. 1 = Periodic timer A is enabled. AMA—Address Multiplex Size A This field specifies the number of address lines to be output on the bus at the first clock of the memory cycle (see Table 15-7 on page 15-60 for more information).
Page 377 Freescale Semiconductor, Inc. Memory Controller GPLA4DIS—GPLA4 Output Line Disable This bit determines whether or not the UPWAITA/GPL_A4 pin will behave as an output line controlled by the internal GPL4 signal and the UPM RAM word. 0 = UPWAITA/GPL_A4 is defined as GPL_A4.
Page 378 Freescale Semiconductor, Inc. Memory Controller TLFA—Timer Loop Field A This field specifies the number of times a loop defined in the UPMA RAM word is executed for a periodic timer service. 0001 = The loop is executed 1 time. 0010 = The loop is executed 2 times.
Page 379 Freescale Semiconductor, Inc. Memory Controller PTB—Periodic Timer B This field affects the periodic timer B and determines the timer period using the following equation: × System Clock (MHz) Service Duration (µs) -------------------------------------------------------------------------------------------------------------------- - × × × 2 DFBRG Prescaler (PTP) NCS is an integer between 1 and 8 that represents the number of enabled chip-selects that select this UPM.
Page 380 Freescale Semiconductor, Inc. Memory Controller Refer to Section 15.5.4.2 RAM Word Operation for more specific DRAM example information. 00 = 1-cycle disable period. 01 = 2-cycle disable period. 10 = 3-cycle disable period. 11 = 4-cycle disable period. G0CLB—General Line 0 Control B This field selects the address line that is output to the internal GPL0 signal when the UPMB is selected to control memory access.
Page 381 Freescale Semiconductor, Inc. Memory Controller WLFB—Write Loop Field B This field specifies the number of times a loop defined in the UPMB RAM word is executed for a burst write or a single beat write cycle. 0001 = The loop is executed 1 time.
Page 382 Freescale Semiconductor, Inc. Memory Controller 15.3.1.7 MEMORY DATA REGISTER. The memory data register (MDR) contains the data to be written to or read from the RAM array for UPM command operations. This register must be set up before you issue a write command to the memory command register.
Page 383 Freescale Semiconductor, Inc. Memory Controller 15.3.1.9 MEMORY PERIODIC TIMER PRESCALER REGISTER. The memory periodic timer prescaler register (MPTPR) defines the divisor of the BRGCLK used as the memory periodic timer input clock. Refer to Section 5.3.4 Internal Clock Signals for details.
Page 384 Freescale Semiconductor, Inc. Memory Controller Anywhere from 0 to 30 wait states can be programmed for TA generation. The WEx signals are available for each byte that is written to memory. Also, an OE signal is provided to eliminate external glue logic. On system reset, a global chip-select (CS0) is asserted to provide a boot ROM chip-select before the system is fully conﬁgured.
Page 385 Freescale Semiconductor, Inc. Memory Controller Next, the banks selected by the general-purpose chip-select machine support an option to output the CSx signal at different timings with respect to the external address bus. CSx can be output in any of the following conﬁgurations: •...
Page 386 Freescale Semiconductor, Inc. Memory Controller As illustrated in Figure 15-6, the timing of the CSx signal is the same as the timing of the address lines. The strobes for the transaction are supplied by the OE or WEx signals, depending on the transaction direction (read or write). The negation of the WEx signal is controlled by the CSNT bit of the ORx register.
Page 387 Freescale Semiconductor, Inc. Memory Controller Figure 15-7 illustrates the basic connection between the MPC823 and an external peripheral device. In this case, CSx is connected directly to the CE signal of the memory device and the R/W signal is connected to the respective R/W signal in the peripheral device.
Page 388 Freescale Semiconductor, Inc. Memory Controller The general-purpose chip-select machine also provides a CSNT attribute in the option register that controls the timing for the appropriate strobe negation in write cycles. When this attribute is asserted, the strobe is negated one quarter of a clock before the normal case.
Page 389 Freescale Semiconductor, Inc. Memory Controller CLOCK ADDRESS ACS = 10 ACS = 11 DATA Figure 15-10. MPC823 GPCM–Relaxed Timing–Write Access (ACS = 10 or 11, SCY = 0, CSNT = 0, and TRLX = 1) CLOCK ADDRESS ACS = 10...
Page 390 Freescale Semiconductor, Inc. Memory Controller CLOCK ADDRESS DATA Figure 15-12. MPC823 GPCM–Relaxed Timing–Write Access (ACS = 00, SCY = 0, CSNT = 1, and TRLX = 1) 15.4.1.1 PROGRAMMABLE WAIT STATE CONFIGURATION. The general-purpose chip-select machine supports internal TA signal generation. It allows “fast” accesses to external memory through an internal bus master or it allows a maximum 17-clock access.
Page 391 Freescale Semiconductor, Inc. Memory Controller CLOCK ADDRESS HOLD TIME DATA Figure 15-13. GPCM Read Followed By Write (EHTR = 0) CLOCK ADDRESS HOLD TIME DATA LONG HOLD TIME ALLOWED Figure 15-14. GPCM Write Followed By Read (EHTR = 1) MPC823 REFERENCE MANUAL...
Page 392 Freescale Semiconductor, Inc. Memory Controller CLOCK ADDRESS HOLD TIME DATA LONG HOLD TIME ALLOWED Figure 15-15. GPCM Read Followed By Read From Different Banks (EHTR = 1) CLOCK ADDRESS HOLD TIME DATA Figure 15-16. GPCM Read Followed By Read From Same Bank (EHTR = 1)
Page 393 Freescale Semiconductor, Inc. Memory Controller 15.4.1.3 BOOT CHIP-SELECT OPERATION. Boot chip-select operation allows address decoding for a boot ROM before system initialization occurs. The CS0 signal is the boot chip-select output and its operation differs from the other external chip-select outputs on system reset.
Page 394 Freescale Semiconductor, Inc. Memory Controller 15.4.1.4 SRAM INTERFACE. Figure 15-17 illustrates a simple connection between an SRAM device and the MPC823. MEMORY 32-BIT WIDE SRAM 128K GPL_x1 / OE A[15:29] ADDRESS D[0:31] DATA Figure 15-17. GPCM to SRAM Configuration 15.4.1.5 EXTERNAL ASYNCHRONOUS MASTER SUPPORT. Figure 15-18 illustrates the basic interface between an asynchronous external master and the GPCM to allow connection to “static RAM”...
Page 395 Freescale Semiconductor, Inc. Memory Controller Figure 15-19 illustrates the timing for TRLX = 0 when an external asynchronous master accesses SRAM. The TA signal remains asserted with the WEx and OE signals until the AS signal is negated by the external master.
Page 396 Freescale Semiconductor, Inc. Memory Controller 15.5 USER-PROGRAMMABLE MACHINES Each of the two user-programmable machines (UPMs) is a flexible interface that connects to a wide range of memory devices. At the heart of each UPM is an internal memory RAM array that specifies the logical value driven on the external memory controller pins for a given clock cycle.
Page 397 Freescale Semiconductor, Inc. Memory Controller 15.5.1 Requests The user-programmable machine has four basic requests that can initiate a UPM cycle. There is a special start address in the RAM array that is associated with each of the following cycle types: •...
Page 398 Freescale Semiconductor, Inc. Memory Controller 15.5.1.1 INTERNAL/EXTERNAL MEMORY ACCESS REQUESTS. When any of the internal masters request a new access to external memory, the address and type of the transfer are compared to each one of the valid banks defined in the base register. The value of the MS field in the base register selects the UPM that will handle the memory access.
Page 399 Freescale Semiconductor, Inc. Memory Controller 15.5.1.3 SOFTWARE REQUESTS. The software can initiate a request to the user-programmable machine by issuing one of three commands—read, write, or execute a RAM word—to the memory command register. Every memory device has its own signal handshaking protocol to put it into self-refresh mode or any special protocol mode.
Page 400 Freescale Semiconductor, Inc. Memory Controller Each of the UPMs can control how the address of the current access is output to the external pins. Address multiplexing configurations for a specific memory or device can be selected in the machine mode register. There is also a multiplexing field in the RAM word that is used to control cycle-by-cycle accesses.
Page 401 Freescale Semiconductor, Inc. Memory Controller SYSTEM CLOCK CLKOUT GCLK1 GCLK2 CLOCK PHASE Figure 15-24. UPM Clock Scheme Two (Division Factor = 2) The CSx signals are handled in a similar way, except that only the CSx signal corresponding to the currently accessed bank is modified. The BS signal assertion and negation timing is...
Page 402 Freescale Semiconductor, Inc. Memory Controller The clock phases shown in these figures refer to the timing windows when the signals controlled by these bits in the RAM word are driven. SYSTEM CLOCK CLKOUT GCLK1 GCLK2 CST4 CST1 CST2 CST3 CST4...
Page 403 Freescale Semiconductor, Inc. Memory Controller SYSTEM CLOCK CLKOUT GCLK1 GCLK2 CST1 CST1 CST4 CST2 CST3 CST4 CST2 CST3 GPL1 G1T4 G1T3 G1T4 G1T3 GPL2 G2T4 G2T3 G2T4 G2T3 CLOCK PHASE RAM WORD 1 RAM WORD 2 Figure 15-26. UPM Signals Timing Example Two...
Page 404 Freescale Semiconductor, Inc. Memory Controller 15.5.4 The RAM Array The RAM array size for each UPM is 64 locations deep and 32 bits wide as illustrated in Figure 15-27. The selected bank is one of eight banks that matches the current address.
Page 405 Freescale Semiconductor, Inc. Memory Controller 15.5.4.1 THE RAM WORD. The RAM word is a 32-bit wide micro-instruction that is stored in one of 64 locations in the RAM array. 15.5.4.1.1 RAM Word Format. The RAM word format selects and specifies the timing of all external signals controlled by the user-programmable machine.
Page 406 Freescale Semiconductor, Inc. Memory Controller CST3—Chip-Select Timing 3 This bit defines the state of the CSx signal during clock phase 4. 0 = The CSx signal is asserted at the trailing edge of GCLK1. 1 = The CSx signal is negated at the trailing edge of GCLK1.
Page 407 Freescale Semiconductor, Inc. Memory Controller G0H—General-Purpose Line 0 Higher This field defines the state of the GPL0 signal during clock phase 4. 10 = The GPL0 signal is asserted at the trailing edge of GCLK1. 11 = The GPL0 signal is negated at the trailing edge of GCLK1.
Page 408 Freescale Semiconductor, Inc. Memory Controller G4T4/DLT3—General-Purpose Line 4 Timing 4/Delay Time 3 This bit performs two functions depending on the value of the GPLx4DIS bit in the machine mode register. If the MxMR defines the UPWAITx/GPL_x4 pin as an output (GPL_x4), then this bit functions as G4T4.
Page 409 Freescale Semiconductor, Inc. Memory Controller LOOP—Loop The first RAM word in the RAM array where LOOP is 1 is recognized as the Loop Start Word. The next RAM word where LOOP is 1 is recognized as the Loop End Word. The RAM words between the beginning and end are defined as the loop.
Page 410 Freescale Semiconductor, Inc. Memory Controller UTA—UPM Transfer Acknowledge This bit controls the state of the TA signal sampled by the external bus interface in the current memory cycle. The TA signal is output at the rising edge of GCLK2. 0 = The TA signal is driven low on the next rising edge of GCLK2.
Page 411 Freescale Semiconductor, Inc. Memory Controller 15.5.4.2.2 Chip-Select Signals. The MS field in the base register of the accessed memory bank selects a user-programmable machine on the currently requested cycle. The selected UPM only affects the assertion and negation of the appropriate CSx signal and its timing is specified in the UPM RAM word.
Page 412 Freescale Semiconductor, Inc. Memory Controller 15.5.4.2.3 Byte-Select Signals. The MS field in the base register of the accessed memory bank selects a user-programmable machine on the currently requested cycle. The selected UPM only affects the assertion and negation of the appropriate BSx signal and its timing as specified in the RAM word.
Page 413 Freescale Semiconductor, Inc. Memory Controller The uppermost byte select (BS0) signal indicates that the most-significant eight bits of the data bus (D0-7) contain valid data during a cycle and the upper-middle byte-select (BS1) indicates that the upper-middle eight bits of the data bus (D[8-15]) signal contain valid data during a cycle.
Page 414 Freescale Semiconductor, Inc. Memory Controller 15.5.4.2.4 General-Purpose Signals. The general-purpose (GPL[1:5]) signals have two bits in the RAM word that define the logical value of the signal to be changed at the falling edge of GCLK1 or GCLK2. GPL0 has two 2-bit fields that perform the same function with additional phase control.
Page 415 Freescale Semiconductor, Inc. Memory Controller 15.5.4.2.5 Loop Control. The LOOP bit in the RAM word allows you to run a repetitive program fragment a specific number of times. The first time the LOOP bit is asserted in a RAM word, the memory controller recognizes it as a Loop Start Word. At this time, the memory loop counter is loaded with the corresponding contents of the LOOP field shown in Table 15-6.
Page 416 Freescale Semiconductor, Inc. Memory Controller 15.5.4.2.7 Address Multiplexing. You can control the address signals that go to the external bus. The AMA and AMB fields of the MxMR control how the address signals are multiplexed. The SAM bit in the option register determines the address multiplexing for the first clock cycle.
Page 417 Freescale Semiconductor, Inc. Memory Controller Table 15-8. AMA/AMB Definition For DRAM Interface DATA BUS MEMORY NUMBER OF NUMBER OF MPC823 AMA/AMB WIDTH SIZE DRAM ROW DRAM COLUMN ADDRESS PIN IN MxMR ADDRESS PINS ADDRESS PINS CONNECTION 8 Bits A24 - A31...
Page 418 Freescale Semiconductor, Inc. Memory Controller Table 15-8. AMA/AMB Definition For DRAM Interface (Continued) DATA BUS MEMORY NUMBER OF NUMBER OF MPC823 AMA/AMB WIDTH SIZE DRAM ROW DRAM COLUMN ADDRESS PIN IN MxMR ADDRESS PINS ADDRESS PINS CONNECTION 8 Bits A19 - A31...
Page 419 Freescale Semiconductor, Inc. Memory Controller Table 15-8. AMA/AMB Definition For DRAM Interface (Continued) DATA BUS MEMORY NUMBER OF NUMBER OF MPC823 AMA/AMB WIDTH SIZE DRAM ROW DRAM COLUMN ADDRESS PIN IN MxMR ADDRESS PINS ADDRESS PINS CONNECTION 32 Bits 256K...
Page 420 Freescale Semiconductor, Inc. Memory Controller 15.5.4.2.8 Transfer Acknowledge and Data Sample Control. During a memory access, the UTA bit of the RAM word controls the state of the TA signal sampled by the bus master. The TA signal is driven on the rising edge of GCLK2. When a read access is handled by the...
Page 421 Freescale Semiconductor, Inc. Memory Controller 15.5.5 The Wait Mechanism If the UPM reads a RAM word with the WAEN bit set, the external UPWAITx signal is sampled and synchronized by the memory controller and the current request is frozen. If the...
Page 422 Freescale Semiconductor, Inc. Memory Controller The UPWAITx signal is sampled at the falling edge of the CLKOUT. If the signal is asserted and the WAEN bit is set in the current RAM word, the UPM is frozen until the UPWAITx signal is recognized as negated.
Page 423 Freescale Semiconductor, Inc. Memory Controller 15.5.5.3 HANDLING VARIABLE ACCESS TIME AND SLOW DEVICES. The memory controller provides two different mechanisms to interface with slave devices that are either very slow or cannot guarantee a predefined access time—the wait state and the external TA signal.
Page 424 Freescale Semiconductor, Inc. Memory Controller 15.6 EXTERNAL MASTER SUPPORT The memory controller supports internal and external bus masters. Accesses that originate from the core, CPM, and LCD controller are considered internal and those initiated by an external bus master are external. External bus master support can be enabled in the SIU module configuration register (SIUMCR), as indicated in Section 12.12.1.1 SIU Module...
Page 425 Freescale Semiconductor, Inc. Memory Controller The A[28:20] pins must be used to generate addresses to memory devices during burst accesses. They duplicate the value of the A[28:20] signals when an internal master initiates a transaction on the external bus. When an external master initiates a transaction on the external bus, the A[28:20] pins reflect the value of the A[28:20] pins on the first clock cycle of the memory access.
Page 426 Freescale Semiconductor, Inc. Memory Controller ADDRESS MEMORY MATCH DEVICE ACCESS COMPARE CLKOUT A[6:27] A[28:31] TSIZEx DATA Figure 15-36. Asynchronous External Master Access To connect to external memory devices that require address multiplexing, use the GPL_x5 pin. The state of the GPL_x5 signal logic value depends on the configuration defined in Table 15-9.
Page 427 Freescale Semiconductor, Inc. Memory Controller Table 15-9. GPL_x5 Signal (Pin) Behavior MACHINE MACHINE G5LA G5LS G5T4 G5T3 GPL_x5 BEHAVIOR CONTROLLING CONTROLLING (ORx) (ORx) (RAM (RAM AT THE CONTROLLING THE SLAVE WORD) WORD) CLOCK EDGE MEMORY ACCESS ACCESS CLOCK CYCLE GPCM GPL_A5 and GPL_B5 do not change their value.
Page 428 Freescale Semiconductor, Inc. Memory Controller 15.6.1 External Master Examples A synchronous example interconnection in which an external master and the MPC823 can both share access to a DRAM bank is illustrated in Figure 15-37. Notice that CS1, UPMA, and GPL_A5 were chosen to assist in the control of DRAM bank accesses. To perform burst accesses initiated by the external master or MPC823 using this configuration, the A[28:30] signals are connected to the multiplexer controlled by GPL_A5.
Page 429 Freescale Semiconductor, Inc. Memory Controller CLKOUT GCLK1 A[6:31] BURST D[0:31] [0:3] [0:3]) A[28:29] GPL_A5 cst4 (Bit 0) cst1 (Bit 1) cst2 (Bit 2) cst3 (Bit 3) bst4 (Bit 4) bst1 (Bit 5) bst2 (Bit 6) bst3 (Bit 7) g0l0 (Bit 8) ≈...
Page 430 Freescale Semiconductor, Inc. Memory Controller An asynchronous example interconnection in which an external master and the MPC823 can both share access to a DRAM bank is illustrated in Figure 15-39. Notice that CS1, UPMA, and GPL_A5 were chosen to assist in the control of DRAM bank accesses.
Page 431 Freescale Semiconductor, Inc. Memory Controller CLKOUT/GCLK2 GCLK1 A[6:31] D[0:31] BS_x [0:3]) GPL_x5 cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 ≈ g4t4 Bit 18...
Page 432 Freescale Semiconductor, Inc. Memory Controller 15.7 MEMORY SYSTEM INTERFACE EXAMPLES The following examples illustrate how to connect and set up the UPM RAM array for two types of DRAM—page mode DRAM and page mode extended data out DRAM. The values used in these examples apply to either UPMA or UPMB.
Page 433 Freescale Semiconductor, Inc. Memory Controller 3. Translate the timing diagrams into RAM words for each type of memory access. The bottom half of the figures represent the RAM array contents that handle each of the possible cycles and each column represents a different word in the RAM array. A blank cell in each figure indicates a “don’t care”...
Page 434 Freescale Semiconductor, Inc. Memory Controller CLKOUT/GCLK2 GCLK1 A[6:31] COLUMN D[0:31] [0:3] BS_A (CAS[0:3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8...
Page 435 Freescale Semiconductor, Inc. Memory Controller CLKOUT/GCLK2 GCLK1 A[6:31] COLUMN D[0:31] [0:3] BS_A [0:3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8...
Page 436 Freescale Semiconductor, Inc. Memory Controller CLKOUT/GCLK2 GCLK1 A[6:31] COLUMN 1 COLUMN 2 COLUMN 3 COLUMN 4 D[0:31] [0:3] BS_A [0:3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6...
Page 437 Freescale Semiconductor, Inc. Memory Controller CLKOUT/GCLK2 GCLK1 A[6:31] COLUMN 1 COLUMN 2 COLUMN 3 COLUMN 4 D[0:31] [0:3] BS_A [0:3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6...
Page 438 Freescale Semiconductor, Inc. Memory Controller CLKOUT/GCLK2 GCLK1 A[6:31] COLUMN 1 COLUMN 2 COLUMN 3 COLUMN 4 D[0:31] [0:3] BS_A [0:3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6...
Page 439 Freescale Semiconductor, Inc. Memory Controller CLKOUT/GCLK2 GCLK1 A[6:31] COLUMN 1 COLUMN 2 COLUMN 3 COLUMN 4 D[0:31] [0:3] BS_A [0:3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6...
Page 440 Freescale Semiconductor, Inc. Memory Controller CLKOUT/GCLK2 GCLK1 A[6:31] D[0:31] [0:3] BS_A [0:3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8 g0l1...
Page 441 Freescale Semiconductor, Inc. Memory Controller CLKOUT/GCLK2 GCLK1 A[6:31] D[0:31] [0:3] BS_A [0:3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8 g0l1...
Page 442 Freescale Semiconductor, Inc. Memory Controller You can significantly increase the performance of a page read access when you set GPLA4DIS to 1 in the MAMR and ignore the GPL_A4 pin. The processor samples the data bus at the falling edge of GCLK1 when the TA signal is asserted. Figure 15-50 illustrates how to modify the burst read access to page mode DRAM (no loop) using this feature.
Page 443 Freescale Semiconductor, Inc. Memory Controller CLKOUT/GCLK2 GCLK1 A[6:31] COL 1 COL 2 COL 3 COL 4 D[0:31] [0:3] BS_A [0:3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6...
Page 444 Freescale Semiconductor, Inc. Memory Controller 15.7.2 Page Mode Extended Data-Out DRAM Interface Example The configuration for a 1M, 32-bit wide memory system using two 256K x 16-bit page mode extended data-out (EDO) DRAMs is illustrated in Figure 15-51. Also shown is the physical connection between UPMB and the EDO DRAMs.
Page 445 Freescale Semiconductor, Inc. Memory Controller 4. Define the UPMB (or UPMA) parameters that control the memory system in the following sequence. For additional details, see Table 15-11. — Program the RAM array using the memory command register (MCR) and memory data register (MDR). The RAM word must be written into the MDR before you issue the WRITE command to the MCR.
Page 446 Freescale Semiconductor, Inc. Memory Controller CLKOUT/GCLK2 GCLK1 A[6:31] COLUMN 1 D[0:31] [0:3] BS_B [0:3]) GPL_B1 cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0...
Page 447 Freescale Semiconductor, Inc. Memory Controller CLKOUT/GCLK2 GCLK1 A[6:31] COLUMN 1 D[0:31] [0:3] BS_B [0:3]) GPL_B1 cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0...
Page 448 Freescale Semiconductor, Inc. Memory Controller CLKOUT/GCLK2 GCLK1 A[6:31] COLUMN 1 COLUMN 2 COLUMN 3 COLUMN 4 D[0:31] [0:3] BS_B [0:3]) GPL_B1 cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2...
Page 449 Freescale Semiconductor, Inc. Memory Controller CLKOUT/GCLK2 GCLK1 A[6:31] COLUMN 1 COLUMN 2 COLUMN 3 COLUMN 4 D[0:31] [0:3] BS_B [0:3]) GPL_B1 cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2...
Page 450 Freescale Semiconductor, Inc. Memory Controller CLKOUT/GCLK2 GCLK1 A[6:31] D[0:31] [0:3] BS_B [0:3]) GPL_B1 cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8...
Page 451 Freescale Semiconductor, Inc. Memory Controller CLKOUT/GCLK2 GCLK1 A[6:31] D[0:31] [0:3] BS_B [0:3]) GPL_B1 cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8...
Page 452 Freescale Semiconductor, Inc. Memory Controller CLKOUT/GCLK2 GCLK1 A[6:31] D[0:31] [0:3] BS_x [0:3]) GPL_x1 cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8...
Page 453 Freescale Semiconductor, Inc. SECTION 16 COMMUNICATION PROCESSOR MODULE The MPC823 communication processor module (CPM) provides a flexible and integrated approach to communication-intensive environments. To reduce system frequency and save power, the communication processor module has its own independent RISC microcontroller that is optimized and tuned to handle serial communications.
Page 454 Freescale Semiconductor, Inc. Communication Processor Module The following blocks and protocols contain primary programming functionalities that use parameter RAM tables as their communication interface. • RISC microcontroller Dual port RAM RISC timer table DSP functions Independent DMA • Serial communication controllers...
Page 455 Freescale Semiconductor, Inc. Communication Processor Module The block diagram of the communication processor module is illustrated in Figure 16-1. U - BUS INTERRUPT BUS INTERFACE SDMA CONTROLLER INTERNAL BUS RISC TIMERS MICROCONTROLLER SEQUENCER DUAL-PORT PARALLEL I/O PORTS REGISTER FILE BAUD RATE GENERATORS...
Page 456 Freescale Semiconductor, Inc. Communication Processor Module The MPC823 offers an extremely flexible set of communication capabilities. The remainder of this section discusses all the possible ways you can configure the communication processor module. Figure 16-2 illustrates a sample configuration for a personal digital assistant (PDA) application that supports various communication links and protocols.
Page 457 Freescale Semiconductor, Inc. Communication Processor Module 16.2.1 RISC Microcontroller Features The following is a list of the RISC microcontroller’s main features. • One System Clock Cycle Per Instruction • Fixed-Length Instruction Object Code • Code is Executed from Internal ROM or Dual-Port RAM •...
Page 458 Freescale Semiconductor, Inc. Communication Processor Module 16.2.2 Communication Between the Microcontroller and Core The RISC microcontroller communicates with the core in the following ways: • By exchanging parameters using the 8K dual-port RAM. With simultaneous accesses, the microcontroller experiences a one-clock delay when accessing the dual-port RAM, but the host is never delayed.
Page 459 Freescale Semiconductor, Inc. Communication Processor Module 18. SPI RX 19. SPI TX 20. I C RX 21. I C TX 22. RISC timer tables 23. IDMA DREQ1 (option 3) 24. IDMA DREQ2 (option 3) 16.2.4 Executing Microcode From RAM or ROM The microcontroller can execute microcode from a portion of 8K dual-port RAM.
Page 460 Freescale Semiconductor, Inc. Communication Processor Module TIME—Timer Enable This bit controls whether the microcontroller’s internal timer can send a tick to the microcontroller based on the value programmed into the TIMEP field. 0 = Stop RISC timer table scanning. 1 = Start RISC timer table scanning.
Page 461: Memory Map
Freescale Semiconductor, Inc. Communication Processor Module SCD—Scheduler Configuration Configure this bit as instructed in the download process of a Motorola-supplied RAM microcode package. 0 = Normal operation. 1 = Alternate configuration of the scheduler. ERAM—Enable RAM Microcode Configure this field as instructed in the download process of a Motorola-supplied RAM microcode package.
Page 462 Freescale Semiconductor, Inc. Communication Processor Module CPCR FIELD RESERVED OPCODE CH_NUM RESERVED RESET ADDR (IMMR & 0xFFFF0000) + 0x9C0 RST—Software Reset Command This bit is set by the core and cleared by the communication processor module and when this command is executed, the RST and FLG bits are cleared within two general system clocks.
Page 463 Freescale Semiconductor, Inc. Communication Processor Module FLG—Command Semaphore Flag The bit is set by the core and cleared by the communication processor module. 0 = The communication processor module is ready to receive a new command. 1 = The CPCR contains a command that the communication processor module is currently processing.
Page 464 Freescale Semiconductor, Inc. Communication Processor Module The RISC microcontroller commands consist of the following: • INIT TX AND RX PARAMS—The initialize transmit and receive parameter command initializes the transmit and receive parameters in the parameter RAM to the values that they had when the communication processor module was last reset.
Page 465 Freescale Semiconductor, Inc. Communication Processor Module • GCI TIMEOUT—The GCI timeout command causes the MPC823 transmitter to send an abort request on the E bit of the GCI bus. • USB—The USB commands have the same opcode. See Section 16.10 Universal Serial Bus Controller for a more detailed description.
Page 466 Freescale Semiconductor, Inc. Communication Processor Module The dual-port RAM can either be accessed by the RISC microcontroller or one of two bus masters—the core or the serial DMA channel. When the dual-port RAM is accessed by one of these, it is accessed in two clocks. However, when it is accessed by the microcontroller, it is accessed in one clock.
Page 467 Freescale Semiconductor, Inc. Communication Processor Module When the dual-port RAM is accessed by the core or SDMA channel, the data and address are passed to and from the U-bus. The microcontroller has access to the entire dual-port RAM for data fetches and portions of the system RAM for microcode instruction fetches. The dual-port RAM is used to complete the following tasks.
Page 468 Freescale Semiconductor, Inc. Communication Processor Module For example, in some locations the Ethernet parameter RAM memory map is defined in the same way that the HDLC-specific parameter RAM is defined. Table 16-3. Parameter RAM Memory Map PAGE ADDRESSES PERIPHERAL IMMR + 0x3C00...
Page 469 Freescale Semiconductor, Inc. Communication Processor Module 16.2.6.4 THE RISC TIMER TABLES. The RISC microcontroller can have a maximum of 16 timers that are separate and distinct from the four general-purpose timers and baud rate generators of the communication processor module. These timers are ideal for protocols that do not require extreme precision, but do need to free the host CPU from scanning the software’s timer tables.
Page 470 Freescale Semiconductor, Inc. Communication Processor Module 16.2.6.4.1 RISC Timer Table Parameter RAM Memory Map. Two areas of internal RAM are used for the RISC timer tables—RISC timer table parameter RAM and the RISC timer table entries—which are illustrated in Figure 16-6. The RISC timer table parameter RAM area begins at the RISC timer base address and is used for the general timer parameters.
Page 471 Freescale Semiconductor, Inc. Communication Processor Module Table 16-4. RISC Timer Table Parameter RAM Memory Map ADDRESS NAME WIDTH DESCRIPTION Timer Base + 00 TM_BASE Half-word RISC Timer Table Base Address Index Pointer Timer Base + 02 TM_PTR Half-word RISC Timer Table Pointer...
Page 472 Freescale Semiconductor, Inc. Communication Processor Module • R_TMR—Only the RISC microcontroller uses this register to store the mode of the timer—one-shot (0) or restart (1). You must not modify this register. Instead, you must use the SET TIMER command in the CPCR to control the timer mode.
Page 473 Freescale Semiconductor, Inc. Communication Processor Module • TM_CMD—This register is used as a parameter location when the SET TIMER command is issued. You must write this location prior to issuing the SET TIMER command. The bits of this register are defined as follows.
Page 474 Freescale Semiconductor, Inc. Communication Processor Module 16.2.6.4.2 RISC Timer Table Entries. The 16 timers are located in the block of memory that TM_BASE points to and each timer occupies 4 bytes. The first half-word forms the initial value of the timer written when the SET TIMER command is executed. The next half-word is the current value of the timer that gets decremented until it reaches zero.
Page 475 Freescale Semiconductor, Inc. Communication Processor Module 16.2.6.5 RISC TIMER EVENT REGISTER. The 16-bit RISC timer event register (RTER) is used to report events recognized by the 16 timers and to generate interrupts. However, an interrupt is only generated if the RISC timer table bit is set in the CPM interrupt mask register.
Page 476 Freescale Semiconductor, Inc. Communication Processor Module 16.2.6.7 RISC TIMER INITIALIZATION SEQUENCE EXAMPLE. Follow these steps to initialize the RISC timers: 1. Configure the RCCR to determine the preferred tick interval that will be used for the entire timer table. Normally, you can set the TIME bit at this time. However, it can be set later if all RISC timers must be synchronized.
Page 477 Freescale Semiconductor, Inc. Communication Processor Module 16.2.6.8 RISC TIMER INTERRUPT HANDLING EXAMPLE. An interrupt handler for the RISC timer tables is normally written in the following sequence: 1. Once an interrupt occurs, the RTER is read to determine which of the timers have caused interrupts.
Page 478 Freescale Semiconductor, Inc. Communication Processor Module 16.3 DIGITAL SIGNAL PROCESSING Many embedded control applications require DSP-style algorithm implementations, such as finite impulse response (FIR) filters with or without adaptive equalization, data compression, and scrambling. These are written in software on the MPC823 and do not require your system to have a separate DSP processor, which would cost you more and consume more power.
Page 479 Freescale Semiconductor, Inc. Communication Processor Module 16.3.2.1 HARDWARE. The RISC microcontroller’s hardware contains special DSP processing units, such as a multiplier and accumulator that is capable of handling real or complex numbers, and an address generator that can access cyclic buffer structures in dual-port RAM.
Page 480 Freescale Semiconductor, Inc. Communication Processor Module DUAL-PORT MEMORY SYSTEM MEMORY RECEIVE FD CHAIN DSP1 RX CHAIN BASE DSP2 TX CHAIN BASE INPUT, OUTPUT, AND COEFFICIENT TRANSMIT FD CHAIN BUFFERS Figure 16-8. DSP Function Descriptor Operation 16.3.3.1 DATA REPRESENTATION. The inputs, coefficients, and outputs are represented by 16-bit, fixed-point, 2’s complement numbers.
Page 481 Freescale Semiconductor, Inc. Communication Processor Module 16.3.3.2 MODULO ADDRESSING. The input and output buffers are circular within a certain programmable size that must be a multiple of 2 . The base address of the circular buffer must be aligned on its natural size boundary. For example, if your input buffer size is 128 bytes, your base address must be aligned on a 128-byte boundary.
Page 482 Freescale Semiconductor, Inc. Communication Processor Module W—Wrap (Final Function Descriptor in Table) 0 = This is not the last function descriptor in the function descriptor table. 1 = This is the last function descriptor in the function descriptor table. After this buffer has been used, the communication processor module processes the first function descriptor that the FDBASE index pointer points to in the table.
Page 483 Freescale Semiconductor, Inc. Communication Processor Module Table 16-7. DSP Parameter RAM Memory Map ADDRESS NAME WIDTH DESCRIPTION DSP Base + 0x00 FDBASE Word Function Descriptor Table Base Address DSP Base + 0x04 FD_PTR Word Function Descriptor Pointer DSP Base + 0x08...
Page 484 Freescale Semiconductor, Inc. Communication Processor Module I—Current Function Descriptor Number of Iterations This bit is only used by the RISC microcontroller, so you do not need to modify it in any way. TAP—Current Function Descriptor Number of Taps The bit is only used by the RISC microcontroller, so you do not need to modify it in any way.
Page 485 Freescale Semiconductor, Inc. Communication Processor Module 16.3.3.3 DSP EVENT REGISTER. For DSP interrupts, the memory-mapped SDMA status register (SDSR) is used to generate maskable interrupts to the core. An interrupt is set when the function finishes executing if the I bit is set in the function descriptor. There are two interrupt events—DSP1 and DSP2—that are each associated with a corresponding chain.
Page 486 Freescale Semiconductor, Inc. Communication Processor Module 16.3.3.4 DSP MASK REGISTER. The 8-bit read/write SDMA mask register (SDMR) is used to mask the DSP interrupts and has the same bit format as the SDSR. If a bit in the SDMR is a 1, the corresponding interrupt in the SDSR is enabled and if it is zero, the corresponding interrupt is masked.
Page 487 Freescale Semiconductor, Inc. Communication Processor Module 16.3.3.5 DSP IMPLEMENTATION. There are basically two ways to implement a DSP task—run C code on the core or use the communication processor module functions. Figure 16-10 illustrates an example section of a V.32 modem’s transmit (TX) data pump flow.
Page 488 Freescale Semiconductor, Inc. Communication Processor Module 16.3.3.5.1 DSP Programming Example (Core Only) void tx_filter () S16 *coefr S16 *samplr, *sampli S16 *coefend; S32 filtoutr, filtouti; U8 subcount, sampleindex; extern S16 mult(S16 p1, S16 p2); /* in-line invocation */ coefr=txfiltcoef_str; coefend=txfiltcoef_end;...
Page 489 Freescale Semiconductor, Inc. Communication Processor Module 16.3.3.5.2 DSP Programming Example (Core and CPM). Figure 16-11 illustrates the organization of the data buffer and function descriptor data in system memory and dual-port RAM. The function descriptor resides in system memory and all input, ouput, and coefficient data must reside in dual-port RAM.
Page 490 Freescale Semiconductor, Inc. Communication Processor Module /* Buffer Descriptors */ typedef struct dsp_fd { unsigned short status; unsigned short parameter[7]; } DSP_FD; #define WRAP 0x2000 /* wrap bit */ #define INTR 0x1000 /* interrupt on completion */ /* define for function opcodes */...
Page 491 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.1 FIR1–REAL C, REAL X, AND REAL Y. The FIR1 function implements a basic FIR filter with k real coefficients, real input samples, and real output. The input data is in a circular buffer with size M+1 and the output data is in a circular buffer with size N+1.
Page 492 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.1.2 FIR1 Function Descriptor. The FIR1 function descriptor bit table is described below. RES IALL INDEX OPCODE OFFSET + 0 OFFSET + 2 OFFSET + 4 CBASE OFFSET + 6 OFFSET + 8 XYPTR...
Page 493 Freescale Semiconductor, Inc. Communication Processor Module INDEX— Auto-Increment Index 00 = The X (input) pointer is not incremented. 01 = The X (input) pointer is incremented by one sample. 10 = The X (input) pointer is incremented by two samples.
Page 494 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.2 FIR2–REAL C, COMPLEX X, AND COMPLEX Y. The FIR2 function implements a basic FIR filter with k real coefficients, complex input samples, and complex output. The input data is in a circular buffer with size M+1 and the output data is in a circular buffer with size N+1.
Page 495 Freescale Semiconductor, Inc. Communication Processor Module COEFFICIENTS INPUT SAMPLES OUTPUT C(0) C(1) C(2) imag {x(n-k+1)} real {x(n-k+1)} imag{Y(n-k+1)} real{Y(n-k+1)} C(k-1) imag {x(n-2)} real{x(n-2)} imag{x(n-1)} imag{Y(n-2)} real{x(n-1)} real{Y(n-2)} imag{x(n)} imag{Y(n-1)} real{x(n)} real{Y(n-1)} imag{Y(n)} real{Y(n)} 2K bytes M + 1 bytes N + 1 bytes Figure 16-15.
Page 496 Freescale Semiconductor, Inc. Communication Processor Module Bits 1, 4, 9, and 10—Reserved These bits are reserved and must be set to 0. W—Wrap (Final Function Descriptor in Table) 0 = This is not the last function descriptor in the function descriptor table.
Page 497 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.2.3 FIR2 Parameter Packet. The FIR2 parameter packet is composed of seven 16-bit half-words and described in the table below. Table 16-9. FIR2 Parameter Packet ADDRESS NAME DESCRIPTION Half-word 1 Number of Iterations. Half-word 2 Number of TAPs-1.
Page 498 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.3 FIR3–COMPLEX C, COMPLEX X, AND REAL/COMPLEX Y. The FIR3 function implements a basic FIR filter with k complex coefficients, complex input samples, and real or complex output. The input data is in a circular buffer with size M+1 and the output data is in a circular buffer with size N+1.
Page 499 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.3.1 Coefficients and Sample Data Buffers. The coefficients vector occupies k pairs of 16-bit half-words (real and imaginary components) in memory and C(0) is stored in the first location. The sample input buffer is a cyclic buffer containing M+1 bytes and each input sample is two 16-bit half-words (real and imaginary components).
Page 500 Freescale Semiconductor, Inc. Communication Processor Module The first half-word is composed of the following bits: S—STOP 0 = Do not stop after executing this function descriptor. 1 = Stop after executing this function descriptor. Bits 1, 9, and 10—Reserved These bits are reserved and must be set to 0.
Page 501 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.3.3 FIR3 Parameter Packet. The FIR3 parameter packet is composed of seven 16-bit half-words and described in the table below. Table 16-10. FIR3 Parameter Packet ADDRESS NAME DESCRIPTION Half-word 1 Number of Iterations Half-word 2...
Page 502 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.4 FIR5–COMPLEX C, COMPLEX X, AND COMPLEX Y. The FIR5 function implements a basic FIR filter with k complex coefficients, complex input samples, and complex output. The input data is in a circular buffer with size M+1 and the output data is in a circular buffer with size N+1.
Page 503 Freescale Semiconductor, Inc. Communication Processor Module COEFFICIENTS INPUT SAMPLES REAL OUTPUT COMPLEX OUTPUT (X=0) (X=1) imag{C(0)} real{C(0)} imag{C(1)} imag {x(n-k+1)} imag{Y(n-k+1)} real{C(1)} real {x(n-k+1)} real{Y(n-k+1)} Y(n-K+1) imag {x(n-2)} imag{C(k-1)} real{x(n-2)} imag{Y(n-2)} real{C(k-1)} imag{x(n-1)} Y(n-2) real{Y(n-2)} real{x(n-1)} Y(n-1) imag{Y(n-1)} imag{x(n)} Y(n)
Page 504 Freescale Semiconductor, Inc. Communication Processor Module Bits 1, 9, and 10—Reserved These bits are reserved and must be set to 0. W—Wrap (Final Function Descriptor in Table) 0 = This is not the last function descriptor in the function descriptor table.
Page 505 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.4.3 FIR5 Parameter Packet. The FIR5 parameter packet is composed of seven 16-bit half-words and described in the table below. Table 16-11. FIR5 Parameter Packet ADDRESS NAME DESCRIPTION Half-word 1 Number of Iterations Half-word 2 Number of TAPs-1.
Page 506 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.5 FIR6–COMPLEX C, REAL X, AND COMPLEX Y. The FIR6 function implements a basic FIR filter with k complex coefficients, real input samples, and complex output. The input data is in a circular buffer with size M+1 and the output data is in a circular buffer with size N+1.
Page 507 Freescale Semiconductor, Inc. Communication Processor Module COEFFICIENTS INPUT SAMPLES OUTPUT imag{C(0)} real{C(0)} imag{C(1)} x(n-k+1) real{C(1)} imag{Y(n-k+1)} real{Y(n-k+1)} x(n-2) imag{C(k-1)} x(n-1) real{C(k-1)} x(n) imag{Y(n-2)} real{Y(n-2)} imag{Y(n-1)} real{Y(n-1)} imag{Y(n)} real{Y(n)} 2K bytes M + 1 bytes N + 1 bytes Figure 16-21. FIR6 Coefficients and Sample Data Buffers 16.3.4.5.2 FIR6 Function Descriptor.
Page 508 Freescale Semiconductor, Inc. Communication Processor Module Bits 1, 4, 9, and 10—Reserved These bits are reserved and must be set to 0. W—Wrap (Final Function Descriptor in Table) 0 = This is not the last function descriptor in the function descriptor table.
Page 509 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.5.3 FIR6 Parameter Packet. The FIR6 parameter packet is composed of seven 16-bit half-words and described in the table below. Table 16-12. FIR6 Parameter Packet ADDRESS NAME DESCRIPTION Half-word 1 Number of Iterations-1 (0 = one iteration) Half-word 2 Number of TAPs-1.
Page 510 Freescale Semiconductor, Inc. Communication Processor Module COEFFICIENTS INPUT SAMPLES OUTPUT C(0) C(1) C(2) x(n-k+1) C(3) C(4) Y(n-k+1) C(5) x(n-2) x(n-1) x(n) Y(n-2) Y(n-1) Y(n) 2K bytes M + 1 bytes N + 1 bytes Figure 16-23. IIR Coefficients and Sample Data Buffers 16.3.4.6.2 IIR Function Descriptor.
Page 511 Freescale Semiconductor, Inc. Communication Processor Module W—Wrap (Final Function Descriptor in Table) 0 = This is not the last function descriptor in the function descriptor table. 1 = This is the last function descriptor in the function descriptor table. After this buffer has been used, the CPM processes the first function descriptor that the FDBASE index pointer points to in the table.
Page 512 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.7 MOD–REAL SIN, REAL COS, COMPLEX X, AND REAL/COMPLEX Y. The MOD function implements a basic modulator function with a modulation table composed of {cos ωnT, sin ωnT} pairs, complex input samples, and real outputs. The input data is in a circular buffer with size M+1 and the output data is in a circular buffer with size N+1.
Page 513 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.7.2 MOD Function Descriptor. The MOD function descriptor bit table is described below. OPCODE OFFSET + 0 OFFSET + 2 OFFSET + 4 MPTR OFFSET + 6 OFFSET + 8 XYPTR OFFSET + A...
Page 514 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.7.3 MOD Parameter Packet. The MOD parameter packet is composed of seven 16-bit half-words and is described in the table below. Table 16-14. MOD Parameter Packet ADDRESS NAME DESCRIPTION Half-word 1 Number of Iterations Half-word 2 Modulation Table Size-1.
Page 515 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.8.1 Modulation Table, Sample Data Buffers, and AGC Constant. The modulation table is composed of 16-bit cosine and sine pairs that occupy K +1 bytes in memory. The samples input buffer is a cyclic buffer containing M+1 bytes. Each sample is a 16-bit half-word and the new sample is stored in the address that follows the previous sample.
Page 516 Freescale Semiconductor, Inc. Communication Processor Module The first half-word is composed of the following bits: S—STOP 0 = Do not stop after executing this function descriptor. 1 = Stop after executing this function descriptor. Bits 1, 4–10—Reserved These bits are reserved and must be set to 0.
Page 517 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.8.4 Application Example. The DEMOD is used in the modulator. The following example demonstrates how the function descriptor structure can be used to implement the MOD function. 01001 OFFSET + 0 I=3 (THREE ITERATIONS) OFFSET + 2 16.3.4.9 LMS1–COMPLEX COEFFICIENTS, COMPLEX SAMPLES, AND...
Page 518 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.9.2 LMS1 Function Descriptor. The LMS1 function descriptor bit table is described below. INDEX OPCODE OFFSET + 0 RESERVED OFFSET + 2 OFFSET + 4 CBASE OFFSET + 6 OFFSET + 8 XYPTR OFFSET + A...
Page 519 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.9.3 LMS1 Parameter Packet. The LMS1 parameter packet is composed of seven 16-bit half-words and is described in the table below. Table 16-16. LMS1 Parameter Packet ADDRESS NAME DESCRIPTION Half-word 1 Reserved Half-word 2 Number of Taps-1.
Page 520 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.10.1 Coefficients and Sample Data Buffers. The coefficients vector occupies k pairs of 16-bit half-words (real and imaginary components) in memory and C(0) is stored in the first location. The sample input buffer is a cyclic buffer containing M+1 bytes. Each sample is a pair of 16-bit half-words (real and imaginary components) and the new sample is stored in the address that follows the previous sample.
Page 521 Freescale Semiconductor, Inc. Communication Processor Module The first half-word is composed of the following bits: S—STOP 0 = Do not stop after executing this function descriptor. 1 = Stop after executing this function descriptor. Bits 1, 5, and 8–10—Reserved These bits are reserved and must be set to 0.
Page 522 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.10.3 LMS2 Parameter Packet. The LMS2 parameter packet is composed of seven 16-bit half-words and is described in the table below. Table 16-17. LMS2 Parameter Packet ADDRESS NAME DESCRIPTION Half-word 1 Reserved Half-word 2 Number of Taps-1.
Page 523 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.11.1 Coefficients and Sample Data Buffers. Each input vector is stored in a cyclic buffer containing M+1 bytes. Each sample is a 16-bit half-word and the newest sample is stored in the address that follows the previous sample. The output buffer is a cyclic buffer that contains N+1 bytes.
Page 524 Freescale Semiconductor, Inc. Communication Processor Module The first half-word is composed of the following bits: S—STOP 0 = Do not stop after executing this function descriptor. 1 = Stop after executing this function descriptor. Bits 1 and 4–10—Reserved These bits are reserved and must be set to 0.
Page 525 Freescale Semiconductor, Inc. Communication Processor Module 16.3.4.11.4 Application Example. By specifying different values, several functions can be implemented as shown in the table below. Table 16-19. WADD Functions FUNCTION 0≤ α ≥1 1-α Linear Interpolation y(n) = αx (n) Scalar Multiply...
Page 526 Freescale Semiconductor, Inc. Communication Processor Module 16.4 TIMERS The communication processor module includes four identical 16-bit general-purpose timers that can be cascaded into two 32-bit timers. Each general-purpose timer consists of a timer mode register, a timer capture register, a timer counter, a timer reference register, a timer event register, and a timer global configuration register.
Page 527 Freescale Semiconductor, Inc. Communication Processor Module 16.4.2 Timer Operation The clock input to the prescaler can be selected from three sources: • The general system clock • The general system clock divided by 16 • The corresponding TINx pin The general system clock is generated in the clock synthesizer and defaults to the system frequency (25 or 50MHz).
Page 528 Freescale Semiconductor, Inc. Communication Processor Module Restart gate mode performs the same function as normal mode, except it also resets the counter on the falling edge of the TGATE1 pin. This mode can be used in the following applications: • Pulse Measurement—The restart gate mode can measure a low pulse on the TGATE1 pin.
Page 529 Freescale Semiconductor, Inc. Communication Processor Module 16.4.2.2 TIMER GLOBAL CONFIGURATION REGISTER. The 16-bit, memory-mapped, read/write timer global configuration register (TGCR) contains configuration parameters that are used by both timers. It allows simultaneous starting and stopping of any number of timers as long as one bus cycle is used to access TGCR.
Page 530 Freescale Semiconductor, Inc. Communication Processor Module GM1—Gate Mode for Pin 1 This bit is only valid if the gate function is enabled in timer 1 or 2. 0 = Restart gate mode. A falling TGATE1 pin enables and restarts the count and a rising edge of TGATE1 disables the count.
Page 531 Freescale Semiconductor, Inc. Communication Processor Module FRR—Free Run/Restart 0 = Free run. The timer count continues to increment after the reference value is reached. 1 = Restart. The timer count is reset immediately after the reference value is reached. ICLK—Input Clock Source for the Timer 00 = Internally cascaded input.
Page 532 Freescale Semiconductor, Inc. Communication Processor Module 16.4.2.5 TIMER CAPTURE REGISTERS. Each of the 16-bit, memory-mapped, read-only timer capture registers (TCR1–TCR4) are used to latch the value of the counter at the falling edge of every TINx signal. The CE field in the TMRx register defines whether the counter starts at the rising or falling edge of the TINx signal.
Page 533 Freescale Semiconductor, Inc. Communication Processor Module 16.4.2.7 TIMER EVENT REGISTERS. Each of the 16-bit, memory-mapped timer event registers (TER1–TER4) are used to report events recognized by the timers. When an output reference event is recognized, the timer sets the REF bit, regardless of the corresponding ORI bit in the TMRx register.
Page 534 Freescale Semiconductor, Inc. Communication Processor Module 5. Write 0xFFFF to the TER2. This clears the TER2 of any bits that might have been set. 6. Write 0x00040000 to the CIMR. This enables a timer 2 interrupt in the CPM interrupt controller and initializes the CICR.
Page 535 Freescale Semiconductor, Inc. Communication Processor Module Each SDMA channel can be programmed to output one of eight function codes that identify the channel currently accessing memory. The SDMA channel can be assigned a big-endian (Motorola) or little-endian format for accessing buffer data. These features are programmed...
Page 536 Freescale Semiconductor, Inc. Communication Processor Module 16.5.1 SDMA Bus Arbitration and Transfers The instruction cache, data cache, system interface unit, and SDMA can become internal bus masters whose relative priority can be determined by examining their arbitration IDs. However, you can only adjust SDMA arbitration. All other arbitration IDs are fixed. All 12 SDMA channels share the same ID that you are responsible for programming.
Page 537 Freescale Semiconductor, Inc. Communication Processor Module 16.5.2 The SDMA Registers The SDMA channels share a configuration register, address register, and status register. They are all controlled by the configuration of the serial communication controllers, serial management controllers, serial peripheral interface, and I C controller.
Page 538 Freescale Semiconductor, Inc. Communication Processor Module LAM—LCD/Video Aggressive Mode The use of aggressive mode (as determined by the LAM, RAID and LAID fields) is not recommended for use above waiting on response. If used above waiting on response unexpected behavior will result. This behavior is caused by edge conflicts in the internal logic for this mode of operation.
Page 539 Freescale Semiconductor, Inc. Communication Processor Module 16.5.2.2 SDMA STATUS REGISTER. Shared by all 12 SDMA channels, the 8-bit memory-mapped SDMA status register (SDSR) is used to report events recognized by the SDMA controller. When an event is recognized, the SDMA sets the corresponding bit in the SDSR.
Page 540 Freescale Semiconductor, Inc. Communication Processor Module 16.5.2.3 SDMA MASK REGISTER. The 8-bit read/write SDMA mask register (SDMR) has the same bit format as the SDMA status register. If a bit in the SDMA mask register is a 1, the corresponding interrupt in the event register is enabled. If the bit is zero, the corresponding interrupt is masked.
Page 541 Freescale Semiconductor, Inc. Communication Processor Module 16.5.2.4 SDMA ADDRESS REGISTER. The 32-bit read-only SDMA address register (SDAR) contains the system address that is accessed during an SDMA bus error. It is undefined at reset. SDAR FIELD SBEA RESET — ADDR (IMMR &...
Page 542 Freescale Semiconductor, Inc. Communication Processor Module 16.6.1 Features The following is a list of the MPC823 IDMA’s main features: • Two independent, fully programmable DMA channels • Dual address or single address transfers with 32-bit address and data capability • 32-bit byte transfer counters •...
Page 543 Freescale Semiconductor, Inc. Communication Processor Module Follow these steps to perform an IDMA transfer: 1. Define the source (peripheral) address to be burst aligned. 2. Define the destination address to be burst aligned. 3. Program the IDMA mode register (DCMR) to 0x0000.
Page 544 Freescale Semiconductor, Inc. Communication Processor Module 16.6.3.2 IDMA PARAMETER RAM MEMORY MAP. The MPC823 uses the IDMA parameters listed in the table below to configure the IDMA channel for autobuffer or buffer chaining mode. Table 16-21. IDMA Parameter RAM Memory Map...
Page 545 Freescale Semiconductor, Inc. Communication Processor Module • DCMR—This register controls the operation mode of the IDMA channel. DCMR FIELD RESERVED SIZE TYPE RESET ADDR (IMMR & 0xFFFF0000) + 0x3CC2 (IDMA1) AND 0x3DC2 (IDMA2) Bits 0–10—Reserved These bits are reserved and must be set to 0.
Page 546 Freescale Semiconductor, Inc. Communication Processor Module • S_STATE—This parameter must not be modified. • ITEMP—This parameter must not be modified. • SR_MEM—This parameter must not be modified. • READ_SP—This parameter must not be modified. • D_STATE—This parameter must not be modified.
Page 547 Freescale Semiconductor, Inc. Communication Processor Module 16.6.3.4 IDMA MASK REGISTERS. The 8-bit read/write IDMA1 or 2 mask registers (IDMRx) have the same bit format as the IDSRx. If a bit in the IDMRx is 1, the corresponding interrupt in the status register is enabled. If an IDMRx bit is zero, the corresponding interrupt in the status register is masked.
Page 548 Freescale Semiconductor, Inc. Communication Processor Module 16.6.3.5 IDMA BUFFER DESCRIPTORS. The special IDMA buffer descriptors present the source addresses, destination addresses, and byte counts to the RISC microcontroller. The RISC microcontroller reads the buffer descriptors, programs the SDMA channel, and notifies the core about the completion of a buffer transfer using the IDMA buffer descriptors.
Page 549 Freescale Semiconductor, Inc. Communication Processor Module W—Wrap (Final Buffer Descriptor in Table) 0 = This is not the last buffer descriptor in the table. 1 = This is the last buffer descriptor in the table. After the associated buffer has been used, the RISC microcontroller transfers data from the first buffer descriptor that IBASE register points to in the table.
Page 550 Freescale Semiconductor, Inc. Communication Processor Module SFCR—Source Function Code Register The 8-bit source function code register contains the value that you would like to appear on the AT pins when the associated DMA channel accesses the source memory. This register controls the byte-ordering convention used in transfers.
Page 551 Freescale Semiconductor, Inc. Communication Processor Module DFCR—Destination Function Code Register The 8-bit destination function code register contains the value that you would like to appear on the AT pins when the associated DMA channel accesses the destination memory. This register also controls the byte-ordering convention used in transfers.
Page 552 Freescale Semiconductor, Inc. Communication Processor Module SOURCE BUFFER POINTER This field contains the address of the associated source data buffer and can reside in internal or external memory. Note: In single address mode when the source is a device, the SOURCE BUFFER POINTER field is ignored.
Page 553 Freescale Semiconductor, Inc. Communication Processor Module 16.6.3.7 STARTING IDMA. Once the channel has been initialized with all parameters required for a transfer operation, IDMA is started by setting the DREQx bit in the port C special option (PCSO) register. Once DREQx has been set, the channel is active and accepts operand transfer requests through the channel’s corresponding DREQx pin.
Page 554 Freescale Semiconductor, Inc. Communication Processor Module 16.6.3.11 IDMA OPERAND TRANSFERS. Once IDMA successfully arbitrates for the bus, it can begin making operand transfers. The source IDMA bus cycle has timing identical to an internal master read bus cycle. The destination IDMA bus cycle’s timing is controlled by the memory controller and is therefore identical to any other internal access.
Page 555 Freescale Semiconductor, Inc. Communication Processor Module Regardless of the source size, destination size, source starting address, or destination starting address, IDMA uses the most efficient packing algorithm possible to perform the transfer in the lowest number of bus cycles. 16.6.3.11.3 Single-Address Mode (Fly-By Transfers). Each IDMA channel can be independently programmed to provide single-address transfers.
Page 556 Freescale Semiconductor, Inc. Communication Processor Module CLKOUT ADDRESS RD / DATA SDACKx DREQx Figure 16-40. Single-Address, Peripheral Write, Synchronous TA • Single address destination write—During this type of IDMA cycle, the source device is controlled by the IDMA handshake signals (DREQx and SDACKx). When the source device requests service from the IDMA channel, IDMA asserts SDACKx to allow the source device to drive data onto the data bus.
Page 557 Freescale Semiconductor, Inc. Communication Processor Module CLKOUT ADDRESS RD / DATA SDACKx DREQx Figure 16-41. Single-Address, Peripheral Read, Synchronous TA 16.6.3.11.4 Single-Buffer Burst Fly-By Mode. This mode is used to transfer a data block from a peripheral to system memory. When the buffer has been completely transferred, channel operation is terminated.
Page 558 Freescale Semiconductor, Inc. Communication Processor Module Interlaced mode can be set up using the following steps: 1. Initialize the IDMA single buffer mode parameter RAM. 2. In the RCCR, set the EIE bit to 1 and the DR1M bit according to the requested mode.
Page 559 Freescale Semiconductor, Inc. Communication Processor Module You must initialize the parameter RAM values before the channel is enabled. However, they must only be modified when there is no DMA activity. • Buffer Address Pointer—The buffer address pointer (BAPR) contains 32 address bits of the destination buffer address used by the IDMA.
Page 560 Freescale Semiconductor, Inc. Communication Processor Module BO—Byte Ordering You must set this field to select the required byte ordering of the data buffer. If this field is modified on-the-fly, it will take effect at the beginning of the next buffer descriptor.
Page 561 Freescale Semiconductor, Inc. Communication Processor Module BPR—Bursts Per Request This field determines how many bursts will be transferred per request. 00 = One burst per request. 01 = Two burst per request. 10 = Reserved. 11 = Four bursts per request.
Page 562 Freescale Semiconductor, Inc. Communication Processor Module 16.6.3.13 IDMA MASK REGISTERS. The 8-bit read/write IDMA1 and 2 mask registers (IDMRx) have the same bit format as the IDMAx status registers. If a bit in the IDMRx is a one, the corresponding interrupt in the IDSRx will be enabled. If an IDMRx bit is zero, the corresponding interrupt in the IDSRx will be masked.
Page 563 Freescale Semiconductor, Inc. Communication Processor Module CLKOUT GCLK1 A[0:31] COLUMN 1 COLUMN 2 COLUMN 3 COLUMN 4 RD/WR D[0:31] (RAS) BS[0:3] (CAS[0:3]) BDIP SDACK1 DREQ1 Figure 16-42. IDMA Single-Address Burst Read or Write 16.6.3.15 DOWNLOAD SEQUENCE. The microcode package is provided in S-records format.
Page 564 Freescale Semiconductor, Inc. Communication Processor Module 16.6.3.16 BUS EXCEPTIONS. When IDMA has the bus and is performing operand transfers, bus exceptions can occur. When a synchronous bus structure like those supported by the MPC823 is used, you can make provisions that allow a bus master to detect and respond to errors during a bus cycle.
Page 565 Freescale Semiconductor, Inc. Communication Processor Module U-BUS TX / RX ROUTE MODE COMMAND STATUS CLOCK REGISTER REGISTER REGISTER ROUTE CONTROL TO SMC2 TO SCC2 TO SCC3 TO SMC1 USB CLOCKS TIME-SLOT ASSIGNER TDMA SCC2 SCC3 TDMA SMC1 PINS STROBE PINS...
Page 566 Freescale Semiconductor, Inc. Communication Processor Module 16.7.1 Features The top-level features of the serial interface are the time-slot assigner and NMSI. The time-slot assigner has the following main features: • Ability to connect to an independent TDMA channel • Independent, programmable transmit and receive routing paths •...
Page 567 Freescale Semiconductor, Inc. Communication Processor Module Time-slot assigner programming is completely independent of the protocol used by the serial communication controller or serial management controller. For instance, the fact that serial communication controller can be programmed for the HDLC protocol has no impact on time-slot assigner programming.
Page 568 Freescale Semiconductor, Inc. Communication Processor Module Simplest TDM Example MPC82x 1 TDM SYNC 1 TDM CLOCK SCC2 SMC1 TDM TX SLOT 3 SLOT N TDM RX SLOT 3 SLOT N SMC1 SCC2 More Complex TDM Example—Unique Routing MPC82x 1 TDM SYNC...
Page 569 Freescale Semiconductor, Inc. Communication Processor Module 16.7.3 Enabling Connections to the Time-Slot Assigner Each serial communication controller and serial management controller can be independently enabled to connect to the time-slot assigner. A serial communication controller is connected to the time-slot assigner by setting the SC2 bit in the SICR. The serial management controllers are connected to the time-slot assigner by setting the SMCx field of the SIMODE register.
Page 570 Freescale Semiconductor, Inc. Communication Processor Module 16.7.4.1 ONE MULTIPLEXED CHANNEL WITH STATIC FRAMES. In this configuration, there are 64 entries in the serial interface RAM for transmit data and strobe routing and 64 entries for receive data and strobe routing. This configuration must be chosen when the TDM routing does not need to be dynamically changed.
Page 571 Freescale Semiconductor, Inc. Communication Processor Module 16.7.4.2 ONE MULTIPLEXED CHANNEL WITH DYNAMIC FRAMES. In this configuration, there is one multiplexed channel and it has 32 entries for transmit data and strobe routing and 32 entries for receive data and strobe routing. In each RAM, one of the partitions is the current-route RAM and the other is a shadow RAM that allows you to change the serial routing.
Page 572 Freescale Semiconductor, Inc. Communication Processor Module 16.7.4.3 PROGRAMMING THE SERIAL INTERFACE RAM ENTRIES. The programming of each word within the RAM determines the routing of the serial bits and assertion of strobe outputs. The RAM programming codes are shown in the following table.
Page 573 Freescale Semiconductor, Inc. Communication Processor Module The SWTR option gives station B the opportunity to listen to transmissions from station A and transmit data to station A. To do this, station B would set the SWTR bit in its receive route RAM.
Page 574 Freescale Semiconductor, Inc. Communication Processor Module CSEL—Channel Select 000 = The bit/byte group is not supported by the MPC823. The transmit data pin is three-stated and the receive data pin is ignored. 001 = Reserved. 010 = The bit/byte group is routed to SCC2.
Page 575 Freescale Semiconductor, Inc. Communication Processor Module 16.7.4.4 SERIAL INTERFACE RAM DYNAMIC CHANGES. The serial interface RAM has two operating modes: • A time-division mulitplex channel with a static routing definition. The serial interface RAM is divided into two parts—transmit (TX) and receive (RX).
Page 576 Freescale Semiconductor, Inc. Communication Processor Module You can read any RAM at any time, but for proper serial interface operation you must not try to write the current-route RAM. You can, however, read the serial interface status register (SISTR) to find out which part of the RAM is the current-route RAM.
Page 577 Freescale Semiconductor, Inc. Communication Processor Module INITIAL STATE RAM ADDRESS: 63 64 16 RXA 16 RXA THE TSA USES THE FIRST PART OF ROUTE SHADOW THE RAM, AND THE SHADOW IS THE SECOND PART OF THE RAM. N = 0...
Page 578 Freescale Semiconductor, Inc. Communication Processor Module 16.7.5 Serial Interface Programming Model 16.7.5.1 SERIAL INTERFACE GLOBAL MODE REGISTER. The 8-bit, memory-mapped, read/write serial interface global mode register (SIGMR) defines the RAM division modes. SIGMR FIELD RESERVED RESET ADDR (IMMR & 0xFFFF0000) + 0xAE4 Bits 0–4—Reserved...
Page 579 Freescale Semiconductor, Inc. Communication Processor Module 16.7.5.2 SERIAL INTERFACE MODE REGISTER. The 32-bit, memory-mapped, read/write serial interface mode register (SIMODE) defines the serial interface operation modes and with serial interface RAM allows you to support any or all of the ISDN channels independently when in IDL or GCI mode.
Page 580 Freescale Semiconductor, Inc. Communication Processor Module SMC1CS—SMC1 Clock Source (NMSI mode) SMC1 can take its clocks from one of the baud rate generators or one of four pins from the bank of clocks. The SMC1 transmit and receive clocks must be the same when it is connected to the NMSI.
Page 581 Freescale Semiconductor, Inc. Communication Processor Module DSCA—Double Speed Clock for TDMA This bit controls how some time-division multiplex channels, such as GCI, define the input clock to be two times faster than the data rate. 0 = The channel clock (L1RCLKA and/or L1TCLKA) is equal to the data clock. Use for IDL and most TDM formats.
Page 582 Freescale Semiconductor, Inc. Communication Processor Module TFSDA—Transmit Frame Sync Delay for TDMA This field determines the number of clock delays between the transmit sync and the first bit of the transmit frame. 00 = No bit delay. The first bit of the frame is transmitted/received on the same clock as the sync.
Page 583 Freescale Semiconductor, Inc. Communication Processor Module CE=0 L1xCLK L1xSYNC (FE=0) L1xSYNC (FE=1) L1TXDx (BIT 0) L1STx IS DRIVEN FROM CLOCK LOW IN BOTH THE FEx SETTINGS L1STx (ON BIT 0) RX SAMPLED HERE Figure 16-52. Example of Clock Edge (CE) Effect When DSC = 0...
Page 584 Freescale Semiconductor, Inc. Communication Processor Module CEx=1 tFSDx=0 L1xCLK L1xSYNC (FEx=0) L1TXDx (BIT 0) THE L1STx IS DRIVEN FROM SYNC. DATA IS DRIVEN FROM CLOCK LOW. L1STx (ON BIT 0) RX SAMPLED HERE (FEx=0) L1xSYNC L1TXDx (BIT 0) L1STx IS DRIVEN FROM CLOCK HIGH...
Page 585 Freescale Semiconductor, Inc. Communication Processor Module CEx=0 tFSDx=0 L1xCLK (FEx=1) L1xSYNC L1TXDx (BIT 0) L1STx DRIVEN FROM SYNC DATA DRIVEN FROM CLOCK HIGH L1STx (ON BIT 0) RX SAMPLED HERE (FEx=1) L1xSYNC L1TXDx (BIT 0) L1STx (ON BIT 0) L1STx DRIVEN FROM CLOCK LOW...
Page 586 Freescale Semiconductor, Inc. Communication Processor Module 16.7.5.3 SERIAL INTERFACE CLOCK ROUTE REGISTER. The 32-bit, read/write, memory-mapped serial interface clock route (SICR) register is used to define the universal serial bus and serial communication controller clock sources that can be one of the four baud rate generators or an input from a bank of clock pins.
Page 587 Freescale Semiconductor, Inc. Communication Processor Module R3CS—Receive Clock Source for SCC3 This field is ignored when the SCC3 is connected to the time-slot assigner (SC3 = 1). 000 = SCC3 receive clock is BRG1. 001 = SCC3 receive clock is BRG2.
Page 588 Freescale Semiconductor, Inc. Communication Processor Module R2CS—Receive Clock Source for SCC2 This field is ignored when the SCC2 is connected to the time-slot assigner (SC2 = 1). 000 = SCC2 receive clock is BRG1. 001 = SCC2 receive clock is BRG2.
Page 589 Freescale Semiconductor, Inc. Communication Processor Module 16.7.5.4 SERIAL INTERFACE COMMAND REGISTER. The 8-bit serial interface command register (SICMR) allows you to dynamically program the serial interface RAM. The contents of this register are only valid in the RAM division mode. For more information about dynamic programming, refer to Section 16.7.4.4 Serial Interface RAM Dynamic...
Page 590 Freescale Semiconductor, Inc. Communication Processor Module 16.7.5.5 SERIAL INTERFACE STATUS REGISTER. The 8-bit serial interface status register (SISTR) lets you know which part of the serial interface RAM is the current-route RAM. The value of this register is only valid when the corresponding bit in the SICMR is cleared.
Page 591 Freescale Semiconductor, Inc. Communication Processor Module 16.7.5.6 SERIAL INTERFACE RAM POINTER REGISTER. The 32-bit, read-only serial interface RAM pointer (SIRP) register indicates the RAM entry that is currently being serviced. It contains the real-time status location of the serial interface that is currently inside the TDM frame.
Page 592 Freescale Semiconductor, Inc. Communication Processor Module Bits 0–1 and 8–9—Reserved These bits are reserved and must be set to 0. VT1, VT2, VR1, and VR2—Time-Slot Valid Bits for Serial Interface RAM Entries The VTx or VRx bit in each entry shows that the entry is valid, which is helpful when the corresponding pointer entry value is zero.
Page 593 Freescale Semiconductor, Inc. Communication Processor Module 16.7.5.6.2 SIRP Indication When RDM = 01. For the receiver, RAPTRx is used, depending on the portion of the serial interface RX RAM that is currently active. For the transmitter, TAPTRx is used, depending on the portion of the serial interface TX RAM that is currently active.
Page 594 Freescale Semiconductor, Inc. Communication Processor Module 16.7.6.1 IDL INTERFACE IMPLEMENTATION. The MPC823 can identify and support each IDL channel or it can output strobe lines for interfacing with devices that do not support the IDL bus. The IDL signals for each transmit and receive channel are as follows: •...
Page 595 Freescale Semiconductor, Inc. Communication Processor Module There are two definitions of the IDL bus frame structure—8 and 10 bits. The only difference between them is the channel order within the frame. Figure 16-57. IDL Terminal Adaptor MPC823 REFERENCE MANUAL 16-143 For More Information On This Product, Go to: www.freescale.com...
Page 596 Freescale Semiconductor, Inc. Communication Processor Module 10-BIT IDL L1xCLK (CLOCK IS NOT TO SCALE) L1xSYNC L1RXDx L1TXD x 8-BIT IDL L1 x CLK (CLOCK IS NOT TO SCALE) L1 x SYNC L1RXD x D1 D2 L1TXD D1 D2 NOTE: L1RQ x AND L1GR x ARE NOT SHOWN.
Page 597 Freescale Semiconductor, Inc. Communication Processor Module The MPC823 supports all channels of the IDL bus in the basic rate. Each bit in the IDL frame can be routed to every serial communication controller and serial management controller or they can assert a strobe output that supports an external device.
Page 598 Freescale Semiconductor, Inc. Communication Processor Module 16.7.6.2.1 IDL Interface Programming Example. Using the example in Section 16.7.6.1 IDL Interface Implementation as a base model, the initialization sequence is as follows: 1. Assuming SMC1 is connected to the B1 channel, SMC2 is connected to the B2 channel, and SCC2 is connected to the D channel, program the serial interface RAM.
Page 599 Freescale Semiconductor, Inc. Communication Processor Module 11. SISTR and SIRP do not need to be read, but can be used for debugging information once the channels are enabled. 12. Enable SCC2 to HDLC operation (to handle the LAPD protocol of the D channel). Set SCC2 and SMC1 to transparent operation.
Page 600 Freescale Semiconductor, Inc. Communication Processor Module In addition to the 144kbps ISDN 2B+D channels, the GCI provides five channels for maintenance and control functions: • B1 is a 64kbps bearer channel • B2 is a 64kbps bearer channel • M is a 64kbps monitor (M) channel •...
Page 601 Freescale Semiconductor, Inc. Communication Processor Module 16.7.7.2 PROGRAMMING THE GCI INTERFACE. There are two modes of the GCI interface—normal and SCIT. 16.7.7.2.1 Normal Mode. You can program and configure the channels used for the GCI bus interface. First, program the SIMODE register to the GCI/SCIT mode for that channel.
Page 602 Freescale Semiconductor, Inc. Communication Processor Module 16.7.7.3 GCI INTERFACE PROGRAMMING EXAMPLE. Assuming SCC2 is connected to the D channel, SMC2 to the B1 channel, and SMC1 to the C/I channels, the initialization sequence is as follows: 1. Program the serial interface RAM. Write all entries that are not used with 0x0001, set the LST bit, and disable the routing function.
Page 603 Freescale Semiconductor, Inc. Communication Processor Module 10. SISTR and SIRP do not need to be read, but can be used for debugging information once the channels are enabled. 11. Enable SCC2 for HDLC operation (to handle the LAPD protocol of the D channel). Set SMC1 for SCIT operation.
Page 604 Freescale Semiconductor, Inc. Communication Processor Module The pins available to the universal serial bus, serial communication controllers, and serial management controllers in NMSI mode are illustrated in Figure 16-60. BRG1 BRG2 BRG3 BRG4 BRGO1 BRGO2 BRGO3 SCC3 RCLK3 SCC3 TCLK3...
Page 605 Freescale Semiconductor, Inc. Communication Processor Module The modem control pins for the SCC2 in NMSI mode are as follows: • TXD2 • RXD2 • TCLK2 ← BRG1–BRG4, CLK1–4 • RCLK2 ← BRG1–BRG4, CLK1–4 • RTS2 • CTS2 • CD2 The modem control pins for the SCC3 in NMSI mode are as follows: •...
Page 606 Freescale Semiconductor, Inc. Communication Processor Module 16.8 THE BAUD RATE GENERATORS The communication processor module contains four independent, yet identical, baud rate generators (BRGs) that can be used with the universal serial bus, serial communication controllers, and serial management controllers. The clocks produced in the baud rate generator are sent to the bank-of-clocks selection logic, where they can be routed to the universal serial bus, serial communication controllers, or serial management controllers.
Page 607 Freescale Semiconductor, Inc. Communication Processor Module The clock input to the prescaler can be selected by the EXTC field in the baud rate generator configuration registers to originate in one of three sources—BRGCLK, CLK2 or CLK4. The BRGCLK is generated in the MPC823 clock synthesizer specifically for the four baud rate generators, serial peripheral interface, and I C internal baud rate generator.
Page 608 Freescale Semiconductor, Inc. Communication Processor Module 16.8.1 Autobaud Operation Using the autobaud process, a UART determines the baud rate of its received character stream by examining the pattern received and the timing information of that pattern. The MPC823 baud rate generators have a built-in autobaud control function that automatically measures the length of a start bit and modifies the baud rate accordingly.
Page 609 Freescale Semiconductor, Inc. Communication Processor Module 16.8.2 Baud Rate Generator Configuration Registers The 32-bit, memory-mapped baud rate generator configuration (BRGC1–4) registers are used to configure the baud rate generators. At reset, the baud rate generators are disabled and the BRGOx output clock is high. These registers can be written at any time and you do not need to disable any internal or external devices connected to the BRGOx output clock.
Page 610 Freescale Semiconductor, Inc. Communication Processor Module EXTC—External Clock Source This field selects the baud rate generator input clock from the internal BRGCLK or one of three external pins. 00 = The baud rate generator input clock comes from the BRGCLK (internal clock generated by the clock synthesizer in the system interface unit).
Page 611 Freescale Semiconductor, Inc. Communication Processor Module 16.8.3 UART Baud Rate Examples For synchronous communication using the internal baud rate generator, the BRGOx output clock must never be faster than the system frequency divided by 2. So, with a 25MHz system frequency, the maximum BRGOx output clock rate is 12.5MHz. You must program the UART to 16×...
Page 612 Freescale Semiconductor, Inc. Communication Processor Module For synchronous communication, the internal clock is identical to the baud rate output. To get the preferred rate, you can select the appropriate system clock according to the following equation: (BRGCLK, CLK2 or CLK4) ÷ (clock divider + 1) ÷...
Page 613 Freescale Semiconductor, Inc. Communication Processor Module Each internal clock of a serial communication controller can be programmed with either an external or internal source. The internal clocks originate from one of four baud rate generators or one of four external clock pins. These clocks can be as fast as a 1:2 ratio of a 12.5MHz system clock.
Page 614 Freescale Semiconductor, Inc. Communication Processor Module 16.9.1 Features The following is a list of the serial communication controllers’ main features: • Implements the HDLC, HDLC bus, asynchronous HDLC, synchronous start/stop, asynchronous start/stop, AppleTalk, Transparent, and Ethernet protocols • Supports full 10Mbps Ethernet/IEEE 802.3 •...
Page 615 Freescale Semiconductor, Inc. Communication Processor Module 16.9.2 The General SCCx Mode Registers The serial communication controllers contain two high and low read/write general SCCx mode registers (GSMR_H and GSMR_L) that define all the options common to each serial communication controller, regardless of the protocol. These registers are cleared at reset and since they are 64 bits in length, they are accessed as GSMR_L and GSMR_H.
Page 616 Freescale Semiconductor, Inc. Communication Processor Module TCRC—Transparent CRC (Totally Transparent Mode Only) This field selects the type of frame checking that is provided on the transparent channels of a serial communication controller (either the receiver, transmitter, or both, as defined by the TTX and TRX bits).
Page 617 Freescale Semiconductor, Inc. Communication Processor Module TTX—Transparent Transmitter The serial communication controllers offer totally transparent operation. However, to increase flexibility, totally transparent operation is not configured with the MODE field of the GSMR_L, but with the TTX and TRX bits. This allows you to implement unique applications, such as configuring an SCCx receiver for HDLC operation and configuring a transmitter for totally transparent operation.
Page 618 Freescale Semiconductor, Inc. Communication Processor Module CTSS—CTS Sampling 0 = The CTSx signal is assumed to be asynchronous with the data. It is internally synchronized by a serial communication controller and data is then transmitted after several serial clock delays.
Page 619 Freescale Semiconductor, Inc. Communication Processor Module SYNL—Sync Length (Transparent Mode Only) This field determines the operation of the SCCx receiver that is configured for totally transparent operation. 00 = The sync pattern in the DSR (described in Section 16.9.4 Data Synchronization Register ) is not used.
Page 620 Freescale Semiconductor, Inc. Communication Processor Module Bit 0—Reserved This bit is reserved and must be set to 0. EDGE—Clock Edge This field determines the clock edge the DPLL uses to adjust the received sample point after a jitter occurs in the received signal. These bits are ignored in the UART protocol or the x1 mode of the RDCR field.
Page 621 Freescale Semiconductor, Inc. Communication Processor Module RINV—DPLL Receive Input Invert Data This bit must be zero in HDLC bus mode. 0 = Do not invert. 1 = Invert the data before sending it to the on-chip DPLL for reception. This setting is used to produce FM1 from FM0 and NRZI space from NRZI mark.
Page 622 Freescale Semiconductor, Inc. Communication Processor Module TEND—Transmitter Frame Ending This bit is specifically intended for NMSI transmitter encoding of the DPLL. This bit determines whether the TXDx signal must idle in a high state or in an encoded ones state (high or low).
Page 623 Freescale Semiconductor, Inc. Communication Processor Module RENC—Receiver Decoding Method 000 = NRZ (default setting if DPLL is not used). 001 = NRZI Mark (also set RINV for NRZI space). 010 = FM0 (also set RINV for FM1). 011 = Reserved.
Page 624 Freescale Semiconductor, Inc. Communication Processor Module When using local loopback mode, the clock source for the transmitter and receiver must be the same. Thus, the same baud rate generator or external CLKx pin can be used for both the transmitter and receiver. Separate CLKx pins can be used with the transmitter and receiver as long as the CLKx pins are connected to the same external clock signal source.
Page 625 Freescale Semiconductor, Inc. Communication Processor Module ENT—Enable Transmit This bit enables the transmitter hardware state machine for a serial communication controller. When ENT is cleared, the transmitter is disabled. If ENT is cleared during transmission, the transmitter aborts the current character and the TXDx pin returns to the idle state.
Page 626 Freescale Semiconductor, Inc. Communication Processor Module 16.9.4 Data Synchronization Register Each serial communication controller has a 16-bit, memory-mapped, read/write data synchronization register (DSR) that specifies the pattern used in the frame synchronization procedure of the synchronous protocols. In the UART protocol, it is used to configure fractional stop bit transmission.
Page 627 Freescale Semiconductor, Inc. Communication Processor Module The TOD bit does not need to be set if a new TX buffer descriptor is added to the circular queue or if other TX buffer descriptors in that queue have not finished transmitting. Once they are finished, however, the new TX buffer descriptors are processed.
Page 628 Freescale Semiconductor, Inc. Communication Processor Module The format of the buffer descriptors is the same for each serial communication controller mode of operation and for transmit and receive. The first word in each buffer descriptor contains a status and control word that determines the buffer descriptor’s table length. Only this first field, which contains the status and control bits, differs for each protocol.
Page 629 Freescale Semiconductor, Inc. Communication Processor Module I—Interrupt 0 = No interrupt is generated after this buffer is serviced. 1 = The specific RX or TX bit in the protocol event register is set when this buffer is serviced by the communication processor module. These bits can cause an interrupt when enabled by the mask register.
Page 630 Freescale Semiconductor, Inc. Communication Processor Module All protocols can have their buffer descriptors point to data buffers that are located in the internal dual-port RAM. However, because the internal RAM is being used for buffer descriptors, it is customary for the data buffers to be located in external RAM, especially if the data buffers are large.
Page 631 Freescale Semiconductor, Inc. Communication Processor Module 16.9.7 SCCx Parameter RAM Memory Map The serial communication controller parameter RAM area begins at an offset from the SCCx base area. The protocol-specific portions of the SCCx parameter RAM are discussed in the specific protocol descriptions and the part that is common to all serial communication controller protocols is shown in Table 16-24.
Page 632 Freescale Semiconductor, Inc. Communication Processor Module Table 16-24. SCCx Parameter RAM Memory Map For All Protocols ADDRESS NAME WIDTH DESCRIPTION SCCx Base + 00 RBASE Half-word RX Buffer Descriptor Base Address SCCx Base + 02 TBASE Half-word TX Buffer Descriptor Base Address...
Page 633 Freescale Semiconductor, Inc. Communication Processor Module • RFCR and TFCR—There are two function code registers for the SCCx channel—one for receive data buffers and one for transmit data buffers. The function code entry contains the value that you want to appear on the AT pins when the associated SDMA channel accesses memory.
Page 634 Freescale Semiconductor, Inc. Communication Processor Module Bits 0–2—Reserved These bits are reserved and must be set to 0. BO—Byte Ordering You must set these bits to select the required byte ordering of the data buffer. If this field is modified on-the-fly, it takes effect at the beginning of the next frame or the next buffer descriptor.
Page 635 Freescale Semiconductor, Inc. Communication Processor Module Note: MRBLR is not intended to be dynamically changed while a serial communication controller is operating. However, if it is modified in a single bus cycle with one 16-bit move, then a dynamic change in the receive buffer length can be successfully achieved.
Page 636 Freescale Semiconductor, Inc. Communication Processor Module 16.9.8 Handling Interrupts In the SCCs Interrupt handling for the SCCx channel is configured on a global basis in the CPM interrupt pending register, CPM interrupt mask register, and CPM in-service register. In each of these registers, a bit is used to mask, enable, or report the presence of an interrupt from SCCx.
Page 637 Freescale Semiconductor, Inc. Communication Processor Module 16.9.9 Initializing the Serial Communication Controllers The serial communication controllers require that a number of registers and parameters be configured after power-on reset. To initialize SCC2, regardless of the protocol you are using, follow these steps: 1.
Page 638 Freescale Semiconductor, Inc. Communication Processor Module receive buffer may have been received by a serial communication controller. Thus, it is important to check more than just one RX buffer descriptor during interrupt handling. One common practice is to process all RX buffer descriptors in the interrupt handler until one is found with its E bit set.
Page 639 Freescale Semiconductor, Inc. Communication Processor Module If the CTSx pin is not already asserted when the RTSx pin is asserted, then the delays to the first bit of data depend on when CTSx is asserted. Figure 16-65 illustrates that the delay between CTSx and the data can be approximately 0.5- to 1-bit time or 0-bit times, depending...
Page 640 Freescale Semiconductor, Inc. Communication Processor Module If the CTSx pin is programmed to envelope the data, it must remain asserted during frame transmission or a CTSx lost error occurs. Negation of the CTSx pin forces the RTSx pin high and the transmit data to an idle state. If the CTSS bit in the GSMR_H is zero, the CTSx pin must be sampled by a serial communication controller before a CTSx lost is recognized.
Page 641 Freescale Semiconductor, Inc. Communication Processor Module Reception delays are determined by the CDx pin as illustrated in Figure 16-67. If the CDS bit in the GSMR_H is zero, then the CDx pin is sampled on the rising receive clock edge prior to data being received.
Page 642 Freescale Semiconductor, Inc. Communication Processor Module 16.9.10.2 ASYNCHRONOUS PROTOCOLS. In asynchronous protocols, the RTSx pin is asserted when SCCx data is loaded into the transmit FIFO and a falling transmit clock occurs. The CDx and CTSx pins can be used to control reception and transmission in the same manner as the synchronous protocols.
Page 643 Freescale Semiconductor, Inc. Communication Processor Module RENC RDCR RCLK HSRCLK EDGE DPLL CARRIER SNC TSNC RECEIVER NOISE RINV HUNTING X1 MODE RXDx DECODED DATA HSRCLK SCCRDATA RINV RXDx RENC π NRZI X1 MODE HSRCLK Figure 16-68. DPLL Receiver Block Diagram...
Page 644 Freescale Semiconductor, Inc. Communication Processor Module The DPLL has a carrier-sense signal that indicates when there are data transfers on the RXDx signal. Using the TSNC field of the GSMR_L, this signal is asserted as soon as a transition is detected on RXDx and it is negated after a programmable number of clocks have been detected with no transitions.
Page 645 Freescale Semiconductor, Inc. Communication Processor Module 16.9.11.1 ENCODING AND DECODING DATA WITH A DPLL. Each serial communication controller contains a digital phase-locked loop unit that can be programmed to encode and decode SCCx data as NRZ, NRZI Mark, NRZI Space, FM0, FM1, Manchester, and Differential Manchester.
Page 646 Freescale Semiconductor, Inc. Communication Processor Module • Manchester—A one is represented by a high to low transition at the center of the bit. A zero is represented by a low to high transition at the center of the bit. In both cases there may be a transition at the beginning of the bit to set up the level required to make the correct center transition.
Page 647 Freescale Semiconductor, Inc. Communication Processor Module 16.9.13 DPLL and Serial Infrared Encoder/Decoder IrDA is a family of specifications intended to facilitate the interconnection of computers and peripherals using a directed half-duplex serial infrared physical communications medium. The infrared data association (IrDA) physical layer standard version 1.1 specifies three modes of operation, each one with a distinct modulation scheme and signaling rate.
Page 648 Freescale Semiconductor, Inc. Communication Processor Module 16.9.14 Disabling the SCCs On-the-Fly If you are not using the serial communication controllers, you can disable them and reenable them later by following a sequence of steps to ensure that any buffers currently in use are properly closed and that new data is transferred to or from a new buffer.
Page 649 Freescale Semiconductor, Inc. Communication Processor Module 16.9.14.3 DISABLING THE ENTIRE SCCx RECEIVER. The SCCx receiver can be fully disabled or enabled by following these steps: 1. Clear the ENR bit in the GSMR_L to disable the SCCx receiver and put it in a reset state.
Page 650 Freescale Semiconductor, Inc. Communication Processor Module 16.9.15 The SCCs in UART Mode Many applications need a simple method of sending low-speed data between pieces of equipment. The universal asynchronous receiver transmitter (UART) protocol is the de-facto standard for such communication. The term asynchronous is used because it is not necessary to send clocking information along with the data being sent.
Page 651 Freescale Semiconductor, Inc. Communication Processor Module All the standards provide handshaking signals, but some systems require just three physical lines—transmit data, receive data, and ground. Many proprietary standards have been built around the asynchronous character frame and some even implement a multidrop configuration.
Page 652 Freescale Semiconductor, Inc. Communication Processor Module • Even, odd, force, or no parity generation • Even, odd, force, or no parity check • Frame error, noise error, break, and idle detection • Transmit preamble and break sequences • Freeze transmission option with low-latency stop 16.9.15.2 NORMAL ASYNCHRONOUS MODE.
Page 653 Freescale Semiconductor, Inc. Communication Processor Module The UART transmit shift register transmits the outgoing data on the TXDx pin. Data is then clocked synchronously with the transmit clock, which can have an internal or external source. The RFW bit in the GSMR_H must be set for an 8-bit receive FIFO.
Page 654 Freescale Semiconductor, Inc. Communication Processor Module • MAX_IDL—Once a character is received, the SCCx UART controller begins counting any idle characters that are received. If a MAX_IDL number of idle characters is received before the next data character, an idle timeout occurs and the buffer is closed.
Page 655 Freescale Semiconductor, Inc. Communication Processor Module • RCCRP—This value is used to hold the value of any control character that is not written to the data buffer. • RLBC—This entry is used in synchronous UART when the RZS bit is set in the PSMR–UART and contains the actual pattern of the last break character.
Page 656 Freescale Semiconductor, Inc. Communication Processor Module 16.9.15.6 SCCx UART COMMANDS. You can program the CPM command register (CPCR) with the following commands to transmit data. • STOP TRANSMIT—After the hardware or software is reset and a channel is enabled in the PSMR–SCC UART register, the channel is in transmit enable mode and starts polling the first buffer descriptor in the table every eight transmit clocks.
Page 657 Freescale Semiconductor, Inc. Communication Processor Module • CLOSE RX BD—This command forces a serial communication controller to close the RX buffer descriptor if it is currently being used and it uses the next buffer descriptor for any subsequently received data. If a serial communication controller is not in the process of receiving data, no action is taken.
Page 658 Freescale Semiconductor, Inc. Communication Processor Module MASTER SLAVE 1 SLAVE 2 SLAVE 3 CHOOSE WIRED-OR TWO 8-BIT ADDRESSES UADDR1 PAODR OPERATION IN THE PORT A CAN BE AUTOMATICALLY OPEN-DRAIN REGISTER TO RECOGNIZED IN EITHER UADDR2 ALLOW MULTIPLE TRANSMIT CONFIGURATION. PINS TO BE DIRECTLY CONNECTED.
Page 659 Freescale Semiconductor, Inc. Communication Processor Module E—End of Table In tables with eight control characters, this bit is always zero. 0 = This entry is valid. The lower eight bits are checked against the incoming character. 1 = This entry is invalid and must be the last entry in the control characters table.
Page 660 Freescale Semiconductor, Inc. Communication Processor Module 16.9.15.9 WAKE-UP TIMER. By issuing the ENTER HUNT MODE command, you can temporarily disable the UART receiver and make it inactive until an idle or address character is recognized, depending on how the UM field is set in the PSMR–SCC UART register. See Section 16.9.15.15 SCCx UART Mode Register for more information.
Page 661 Freescale Semiconductor, Inc. Communication Processor Module I—Interrupt If this bit is set, the character in the CHARSEND field is transmitted. The TX bit is then set in the SCCE–UART register and the core may be interrupted. CT—Clear-to-Send Lost This status bit indicates that the CTSx signal was negated when this character was transmitted.
Page 662 Freescale Semiconductor, Inc. Communication Processor Module 16.9.15.13 FRACTIONAL STOP BITS. You can program the asynchronous UART transmitter to transmit fractional stop bits. Using four bits in the SCCx UART data synchronization register (DSR–SCC UART), you can program the length of the last stop bit to be transmitted.
Page 663 Freescale Semiconductor, Inc. Communication Processor Module For 16x oversampling, the FSB field is decoded as follows: 1111 = Last transmitted stop bit 16/16. Default value after reset. 1110 = Last transmitted stop bit 15/16. 1101 = Last transmitted stop bit 14/16.
Page 664 Freescale Semiconductor, Inc. Communication Processor Module The following reception errors can be detected by the SCCx UART controller: • Overrun Error—This error occurs when data is moved from the receiver FIFO to the data buffer after the first byte is received. If a receiver FIFO overrun occurs, the channel writes the received character into the internal FIFO and over the previously received character.
Page 665 Freescale Semiconductor, Inc. Communication Processor Module • Framing Error — The SCCx UART controller gets this error when it receives a character with no stop bit. All framing errors are reported by the SCCx UART controller, regardless of its mode. When this error occurs, the channel writes the received character to the buffer, closes it, sets the FR bit in the RX buffer descriptor, and generates the RX interrupt if it is enabled.
Page 666 Freescale Semiconductor, Inc. Communication Processor Module 16.9.15.15 SCCx UART MODE REGISTER. When a serial communication controller is in UART mode, the 16-bit, memory-mapped, read/write protocol-specific mode register is referred to as the SCCx UART mode register (PSMR–SCC UART). Since each protocol has specific requirements, the PSMR bits are different for each implementation.
Page 667 Freescale Semiconductor, Inc. Communication Processor Module UM—UART Mode This field selects the protocol that is implemented over the ASYNC channel and it can be modified on-the-fly. 00 = Normal UART operation. Multidrop mode is disabled and an idle-line wake-up is selected.
Page 668 Freescale Semiconductor, Inc. Communication Processor Module SYN—Synchronous Mode 0 = Normal asynchronous operation. Normally, you program the TENC and RENC fields in the GSMR_L to NRZ and select either 8 × , 16 × , or 32 × in the RDCR and TDCR fields of the GSMR_L.
Page 669 Freescale Semiconductor, Inc. Communication Processor Module Note: The receive parity errors can be ignored, but not disabled. TPM—Transmitter Parity Mode This field selects the type of parity that the transmitter performs. It can be modified on-the-fly. 00 = Odd parity.
Page 670 Freescale Semiconductor, Inc. Communication Processor Module MRBLR = 8 BYTES FOR SCC2 RECEIVE BD 0 BUFFER BYTE 1 STATUS BYTE 2 LENGTH 0008 8 BYTES BUFFER ETC. FULL POINTER 32-BIT BUFFER POINTER BYTE 8 RECEIVE BD 1 BUFFER BYTE 9...
Page 671 Freescale Semiconductor, Inc. Communication Processor Module OFFSET + 0 DATA LENGTH OFFSET + 2 OFFSET + 4 RX DATA BUFFER POINTER OFFSET + 6 NOTE: You are only responsible for initializing the items in bold. E—Empty 0 = The data buffer associated with this RX buffer descriptor has been filled with data or reception has been aborted because of an error condition.
Page 672 Freescale Semiconductor, Inc. Communication Processor Module A—Address 0 = The buffer only contains data. 1 = When operating in manual multidrop mode, this bit indicates that the first byte of this buffer contains an address byte. The address comparison must be implemented in the software.
Page 673 Freescale Semiconductor, Inc. Communication Processor Module CD—Carrier Detect Lost This bit indicates that the carrier detect signal has been negated while the SCCx UART controller was receiving a message. DATA LENGTH This field represents the number of octets that the communication processor module writes into this buffer descriptor’s data buffer.
Page 674 Freescale Semiconductor, Inc. Communication Processor Module R—Ready 0 = The data buffer associated with this buffer descriptor is not ready to be transmitted. You are free to manipulate this buffer descriptor or its associated data buffer. The communication processor module clears this bit after the buffer is transmitted or after an error condition is encountered.
Page 675 Freescale Semiconductor, Inc. Communication Processor Module CM—Continuous Mode 0 = Normal operation. 1 = The communication processor module does not clear the R bit after this buffer descriptor is closed, thus allowing the associated data buffer to be automatically retransmitted next time the communication processor module accesses this buffer descriptor.
Page 676 Freescale Semiconductor, Inc. Communication Processor Module 16.9.15.18 SCCx UART EVENT REGISTER. When a serial communication controller is in UART mode, the 16-bit memory-mapped SCCx event register is referred to as the SCCx UART event register (SCCE–UART). Since each protocol has specific requirements, the SCCE bits are different for each implementation.
Page 677 Freescale Semiconductor, Inc. Communication Processor Module A bit is cleared by writing a 1 (writing a zero has no effect) and more than one bit can be cleared at a time. All unmasked bits must be cleared before the communication processor module clears the internal interrupt request.
Page 678 Freescale Semiconductor, Inc. Communication Processor Module BRKS—Break Start If set, this bit indicates when a break character is received. It is the first break of a break sequence. You do not receive multiple BRKS events if a long break sequence is received.
Page 679 Freescale Semiconductor, Inc. Communication Processor Module 16.9.15.20 SCCx UART STATUS REGISTER.When a serial communication controller is in UART mode, the 8-bit read-only SCCx status register is referred to as the SCCx UART status register (SCCS–UART). Since each protocol has specific requirements, the SCCS bits are different for each implementation.
Page 680 Freescale Semiconductor, Inc. Communication Processor Module 7. Write to RBASE and TBASE in the SCC2 parameter RAM to point to the RX and TX buffer descriptors in the dual-port RAM. Assuming one RX buffer descriptor at the beginning of dual-port RAM and one TX buffer descriptor following that RX buffer descriptor, write 0x2000 to RBASE and 0x2008 to TBASE.
Page 681 Freescale Semiconductor, Inc. Communication Processor Module Note: After 16 bytes are transmitted, the TX buffer descriptor is closed. Additionally, the receive buffer is closed after 16 bytes are received. Any data received after 16 bytes causes a busy (out-of-buffers) condition since only one RX buffer descriptor is prepared.
Page 682 Freescale Semiconductor, Inc. Communication Processor Module 16.9.16 The SCCs In HDLC Mode Layer 2 of the seven-layer open systems interconnection model from ISO is the data link layer and one of the most common protocols in this layer is high-level data link control (HDLC).
Page 683 Freescale Semiconductor, Inc. Communication Processor Module 16.9.16.1 FEATURES.The following list summarizes the main features of the SCCx in HDLC mode: • Flexible data buffers with multiple buffers per frame • Separate interrupts for frames and buffers (receive and transmit) • Received frames threshold to reduce interrupt overhead •...
Page 684 Freescale Semiconductor, Inc. Communication Processor Module To rearrange the transmit queue before the communication processor module finishes transmitting all of the buffers, issue the STOP TRANSMIT command. This can be useful for transmitting expedited data before previously linked buffers or when an error occurs. When receiving the STOP TRANSMIT command, the SCCx HDLC controller stops transmitting the current frame and starts transmitting idles or flags.
Page 685 Freescale Semiconductor, Inc. Communication Processor Module Note: The SCCx HDLC controller must receive a maximum of eight clocks (after a frame is received) to complete the reception. 16.9.16.4 SCCx HDLC PARAMETER RAM MEMORY MAP.When configured to operate in HDLC mode, the serial communication controllers overlay the structure used in Table 16- 24 with the HDLC parameters that are described in Table 16-27 below.
Page 686 Freescale Semiconductor, Inc. Communication Processor Module • C_MASK—For the 16-bit CRC-CCITT, C_MASK must be initialized with 0x0000F0B8. For the 32-bit CRC-CCITT, C_MASK must be initialized with 0xDEBB20E3. • C_PRES—For the 16-bit CRC-CCITT, C_PRES must be initialized with 0x0000FFFF. For the 32-bit CRC-CCITT, C_PRES must be initialized with 0xFFFFFFFF.
Page 687 Freescale Semiconductor, Inc. Communication Processor Module • TMP—A temporary register that is only used by the communication processor module. • TMP_MB—A temporary register that is only used by the communication processor module. Note: For 8-bit addresses, the eight high-order bits in HMASK must be masked out (cleared).
Page 688 Freescale Semiconductor, Inc. Communication Processor Module 16.9.16.6 SCCx HDLC COMMANDS.You can program the CPM command register (CPCR) with the following commands to transmit data. • STOP TRANSMIT—After the hardware or software is reset and the channel is enabled in the PSMR–SCC HDLC register, the channel is in transmit enable mode and starts polling the first buffer descriptor in the table every 64 transmit clocks or immediately if the TOD bit is set in the transmit-on-demand register (TODR).
Page 689 Freescale Semiconductor, Inc. Communication Processor Module You can program the CPM command register with the following commands to receive data. • ENTER HUNT MODE—After the hardware or software is reset and the channel is enabled in the PSMR–SCC HDLC register, the channel is in receive enable mode and uses the first buffer descriptor in the table.
Page 690 Freescale Semiconductor, Inc. Communication Processor Module The following reception errors can be detected by the SCCx HDLC controller. • Overrun Error—The SCCx HDLC controller maintains an internal FIFO for receiving data. The communication processor module begins programming the SDMA channel and updating the CRC when 8 or 32 bits are received in the FIFO.
Page 691 Freescale Semiconductor, Inc. Communication Processor Module • CRC—When this error occurs, the channel writes the received CRC to the data buffer, closes the buffer, sets the CR bit in the RX buffer descriptor, and generates the RXF interrupt if it is enabled. The channel also increments the CRC error counter. After receiving a frame with a CRC error, the receiver enters hunt mode.
Page 692 Freescale Semiconductor, Inc. Communication Processor Module FSE—Flag Sharing Enable. This bit is only valid if the RTSM bit is set in the GSMR_H. This bit can be modified on-the-fly. 0 = Normal operation. 1 = If the NOF0–NOF3 field is set to 0000, then a single shared flag is transmitted between back-to-back frames.
Page 693 Freescale Semiconductor, Inc. Communication Processor Module 16.9.16.9 SCCx HDLC RECEIVE BUFFER DESCRIPTOR.The SCCx HDLC controller uses the receive (RX) buffer descriptor to report information about the data received for each buffer. An example of the RX buffer descriptor process is illustrated in Figure 16-78.
Page 694 Freescale Semiconductor, Inc. Communication Processor Module MRBLR = 8 BYTES FOR SCC2 RECEIVE BD 0 BUFFER ADDRESS 1 STATUS ADDRESS 2 0008 CONTROL BYTE LENGTH 8 BYTES BUFFER FULL INFORMATION POINTER 32-BIT BUFFER POINTER (I-FIELD) BYTES RECEIVE BD 1 BUFFER...
Page 695 Freescale Semiconductor, Inc. Communication Processor Module OFFSET + 0 DATA LENGTH OFFSET + 2 OFFSET + 4 RX DATA BUFFER POINTER OFFSET + 6 NOTE: You are only responsible for initializing the items in bold. E—Empty 0 = The data buffer associated with this RX buffer descriptor has been filled with data or reception has been aborted because of an error condition.
Page 696 Freescale Semiconductor, Inc. Communication Processor Module F—First in Frame This bit is set by the SCCx HDLC controller when this buffer is the first in a frame. 0 = The buffer is not the first one in a frame. 1 = The buffer is the first one in a frame.
Page 697 Freescale Semiconductor, Inc. Communication Processor Module DATA LENGTH This field represents the number of octets the communication processor module writes into this buffer descriptor data buffer. It is written by the communication processor module once the buffer descriptor is closed. When this buffer descriptor is the last buffer descriptor in the frame (L = 1), the data length contains the total number of frame octets, including 2 or 4 bytes for CRC.
Page 698 Freescale Semiconductor, Inc. Communication Processor Module W—Wrap (Final Buffer Descriptor in Table) 0 = This is not the last buffer descriptor in the TX buffer descriptor table. 1 = This is the last buffer descriptor in the TX buffer descriptor table. After this buffer has been used, the communication processor module transmits data from the first buffer descriptor that TBASE points to in the table.
Page 699 Freescale Semiconductor, Inc. Communication Processor Module DATA LENGTH This field represents the number of bytes the SCCx HDLC controller transmits from this buffer descriptor data buffer. It is never modified by the communication processor module. The value of this field must be greater than zero. The SCCx HDLC controller writes these bits after it finishes transmitting the associated data buffer.
Page 700 Freescale Semiconductor, Inc. Communication Processor Module FRAME RECEIVED IN HDLC STORED IN RX BUFFER TIME LINE IDLE CR CR LINE IDLE RXDx HDLC SCCE EVENTS NOTES: 1. RXB event assumes receive buffers are 6 bytes each. 2. The second IDL event occurs after 15 ones are received in a row.
Page 701 Freescale Semiconductor, Inc. Communication Processor Module A bit is cleared by writing a 1 (writing a zero has no effect) and more than one bit can be cleared at a time. Also, all unmasked bits must be cleared before the communication processor module clears the internal interrupt request.
Page 702 Freescale Semiconductor, Inc. Communication Processor Module RXF—RX Frame This bit indicates when a complete frame is received on the HDLC channel. This bit is set no sooner than two clocks after the last bit of the closing flag is received.
Page 703 Freescale Semiconductor, Inc. Communication Processor Module 16.9.16.13 SCCx HDLC STATUS REGISTER.When a serial communication controller is in HDLC mode, the 8-bit read-only SCCx status register is referred to as the SCCx HDLC status register (SCCS–HDLC). Since each protocol has specific requirements, the SCCS bits are different for each implementation.
Page 704 Freescale Semiconductor, Inc. Communication Processor Module 16.9.16.14 SCC2 HDLC PROGRAMMING EXAMPLE #1.The following initialization sequence is for an SCC2 HDLC channel with an external clock. The SCC2 in HDLC mode is configured with the RTS2, CTS2, and CD2 pins active and the CLK3 pin is used for both the HDLC receiver and transmitter.
Page 705 Freescale Semiconductor, Inc. Communication Processor Module 21. Write 0x001A to the SCCM–HDLC to enable the TXE, RXF, and TXB interrupts. 22. Write 0x20000000 to the CIMR so the SCC2 can generate a system interrupt. The CICR must also be initialized.
Page 706 Freescale Semiconductor, Inc. Communication Processor Module Note: After 5 bytes in the preamble have been transmitted, the TX buffer descriptor is automatically closed. Once 16 bytes have been received, the RX buffer descriptor is closed. Any data received after 16 bytes causes a busy (out-of-buffers) condition since only one RX buffer descriptor is prepared.
Page 707 Freescale Semiconductor, Inc. Communication Processor Module The HDLC bus does not use the echo bit, but rather a separate pin to monitor the data that is transmitted. The transmitted data is simply connected to the CTSx input. Second, the HDLC bus is a synchronous digital open-drain connection for short-distance configurations, rather than the more complex configurations of an S/T interface.
Page 708 Freescale Semiconductor, Inc. Communication Processor Module In single-master configuration, a master station transmits to any slave station without any collisions. The slaves only communicate with the master, but can experience collisions in their access over the bus. In this configuration, a slave that communicates with another slave must first transmit its data to the master, where the data is buffered in RAM and then retransmitted to the other slave.
Page 709 Freescale Semiconductor, Inc. Communication Processor Module 16.9.17.2 ACCESSING THE HDLC BUS.The HDLC bus ensures an orderly access to the bus when two or more transmitters attempt to access it simultaneously. One transmitter is always successful in completing its transmission. While in the active condition, the HDLC bus controller monitors the bus using the CTSx pin.
Page 710 Freescale Semiconductor, Inc. Communication Processor Module To ensure that all stations gain an equal share of the bus, a priority mechanism is implemented on the HDLC bus. Once an HDLC bus node has finished transmitting a frame, it waits 10 consecutive one bits, instead of eight, before beginning the next transmission.
Page 711 Freescale Semiconductor, Inc. Communication Processor Module 16.9.17.2.2 Delaying RTS Mode. Sometimes the HDLC bus can be used in a configuration with a local HDLC bus and a standard transmission line that is not an HDLC bus. This situation is illustrated in Figure 16-84. The local HDLC bus controllers do not communicate with each other, but with a station on the transmission line;...
Page 712 Freescale Semiconductor, Inc. Communication Processor Module COLLISION TCLK 2ND BIT 1ST BIT 3RD BIT TXDx CTSx RTSx RTSx ACTIVE FOR ONLY 2 BIT TIMES Figure 16-85. Delayed RTSx Mode 16.9.17.2.3 Using the Time-Slot Assigner. Sometimes the HDLC bus can be used in a configuration that has a local HDLC bus and a time-division multiplex transmission line that is not an HDLC bus.
Page 713 Freescale Semiconductor, Inc. Communication Processor Module If a serial communication controller is configured to operate using the time-slot assigner of the serial interface, then the data is received and transmitted using the L1TXDA and L1RXDA pins. The collision sensing is still obtained from the individual serial communication controller CTSx pin, so the CTSx pin must be configured in port C to connect to the preferred serial communication controller.
Page 714 Freescale Semiconductor, Inc. Communication Processor Module 16.9.18 The SCCs in AppleTalk Mode ® AppleTalk is a set of protocols developed by Apple Computer Inc. to provide a LAN service between Macintosh computers and printers. Although AppleTalk can be implemented over...
Page 715 Freescale Semiconductor, Inc. Communication Processor Module Frames are sent in groups called dialogs, which are handled by the software. For instance, to transfer a data frame, three frames are actually sent over the network. An RTS frame (not to be confused with the RS-232 RTSx pin) is sent to request the network, then a CTS frame is sent by the destination node, and the data frame is sent by the requesting node.
Page 716 Freescale Semiconductor, Inc. Communication Processor Module 16.9.18.3 CONNECTING TO APPLETALK. The MPC823 connects to LocalTalk and, using the TXDx, RTSx, and RXDx pins, is an interface for the RS-422 transceiver. The RS-422, in turn, is an interface for the LocalTalk connector. Although it is not shown, a passive RC circuit is recommended between the transceiver and connector.
Page 717 Freescale Semiconductor, Inc. Communication Processor Module 16.9.18.4 PROGRAMMING THE SCCS IN APPLETALK MODE. You can implement the SCCx AppleTalk controller by setting certain bits in the SCCx HDLC controller. Otherwise, you must consult Section 16.9.17 The HDLC Bus Controller for detailed information about how to program the SCCx HDLC controller.
Page 718 Freescale Semiconductor, Inc. Communication Processor Module 16.9.18.5 SCCx APPLETALK PROGRAMMING EXAMPLE. Except for the previously discussed register programming, use the example in Section 16.9.16.14 SCC2 HDLC Programming Example #1. 16.9.19 The SCCx in Asynchronous HDLC Mode Asynchronous HDLC is a frame-based protocol that uses HDLC framing techniques in conjunction with UART-type characters.
Page 719 Freescale Semiconductor, Inc. Communication Processor Module If the CM bit in the TX buffer descriptor is set, the SCCx ASYNC HDLC controller writes the signal unit status bits into the buffer descriptor after transmission, but it does not clear the R bit.
Page 720 Freescale Semiconductor, Inc. Communication Processor Module 16.9.19.4 TRANSMITTER TRANSPARENCY ENCODING. The SCCx ASYNC HDLC controller maps characters according to the RFC 1549 standard. It examines the outgoing data bytes and performs a transparency algorithm on a given byte if one of the following conditions apply: •...
Page 721 Freescale Semiconductor, Inc. Communication Processor Module Figure 16-90 illustrates the algorithms, since some cases are not addressed in RFC 1549. RX CHAR CHAR ≥≤ 0X20 MAPPED ? XOR_NEXT ? CHAR ≥= CLOSING CHAR ≥= CTRL ESC? FLAG ? XOR_NEXT=1 CHAR ⊕ 0X20 CHAR ≥= CLOSING...
Page 722 Freescale Semiconductor, Inc. Communication Processor Module 16.9.19.6 EXCEPTIONS TO RFC 1549. The following beheviors do not conform to RFC 1549. • If an 0x7D is followed by a control character and the control character is not mapped, the control character itself is “modified” by the XOR process. The CRC check must catch this exception.
Page 723 Freescale Semiconductor, Inc. Communication Processor Module 16.9.19.8 SCCx ASYNC HDLC PARAMETER RAM MEMORY MAP. When configured as an SCCx ASYNC HDLC controller, a serial communication controller overlays the structure used in Table 16-24 with the SCCx ASYNC HDLC parameters described in Table 16-28.
Page 724 Freescale Semiconductor, Inc. Communication Processor Module • TXCTL_TBL—The transmit control character table stores the bit array used for the TX control character table. Each bit corresponds to a character that must be mapped according to RFC 1549. If the bit is set, the character corresponding to that bit is mapped and if the bit is not set, the corresponding character is not mapped.
Page 725 Freescale Semiconductor, Inc. Communication Processor Module 16.9.19.9 CONFIGURING THE SCCx ASYNC HDLC PARAMETERS. The SCCx ASYNC HDLC parameters can be configured as described in Section 16.9 The Serial Communication Controllers through Section 16.9.8 Handling Interrupts In the SCCs , except for the changes in the following registers. When you are in asynchronous HDLC mode, some of the bits in the GSMR_x and general DSR have different meanings.
Page 726 Freescale Semiconductor, Inc. Communication Processor Module 16.9.19.10 SCCx ASYNC HDLC COMMANDS. You can program the CPM command register (CPCR) with the following commands to transmit data. See Section 16.2.6.1 CPM Command Register for additional information. After the hardware or software is reset and the channel is enabled by the SCCM–ASYNC HDLC register, the channel is in transmit...
Page 727 Freescale Semiconductor, Inc. Communication Processor Module You can program the CPM command register (CPCR) with the following commands to receive data. After the hardware or software is reset and the channel is enabled by its SCCM–ASYNC HDLC register, the channel is in receive enable mode and uses the first buffer descriptor in the table.
Page 728 Freescale Semiconductor, Inc. Communication Processor Module • CRC Error—When this error occurs, the channel writes the received cyclic redundancy check to the data buffer, closes the buffer, and sets the CR bit in the RX buffer descriptor and the RXF bit in the SCCE–ASYNC HDLC register. After receiving a signal unit with this error, the receiver prepares to receive the next frame.
Page 729 Freescale Semiconductor, Inc. Communication Processor Module 16.9.19.12.2 SCCx ASYNC HDLC Receive Buffer Descriptor. The SCCx ASYNC HDLC controller uses the receive (RX) buffer descriptor to report information about each buffer’s received data. An example of the RX buffer descriptor process is illustrated in Figure 16-78.
Page 730 Freescale Semiconductor, Inc. Communication Processor Module I—Interrupt 0 = The RXB bit in the SCCE–ASYNC HDLC register is not set after this buffer is used, but RXF operation is unaffected. 1 = The RXB or RXF bit in the SCCE–ASYNC HDLC register is set when this buffer is used by the SCCx ASYNC HDLC controller.
Page 731 Freescale Semiconductor, Inc. Communication Processor Module CD—Carrier Detect Lost This bit indicates that the carrier detect signal is negated during frame reception. DATA LENGTH This field represents the number of octets the communication processor module writes into this buffer descriptor data buffer once the buffer descriptor is closed. When this buffer descriptor is the last one in the frame, DATA LENGTH contains the total number of frame octets.
Page 732 Freescale Semiconductor, Inc. Communication Processor Module R—Ready 0 = The data buffer associated with this buffer descriptor is not ready for transmission. You are free to manipulate this buffer descriptor or its associated data buffer. The communication processor module clears this bit after the buffer is transmitted or after an error condition is encountered.
Page 733 Freescale Semiconductor, Inc. Communication Processor Module DATA LENGTH This field represents the number of bytes the SCCx ASYNC HDLC controller must transmit from this buffer descriptor data buffer. It is never modified by the communication processor module. The value of this field must be greater than zero. These bits are written by the SCCx ASYNC HDLC controller after it finishes transmitting the associated data buffer.
Page 734 Freescale Semiconductor, Inc. Communication Processor Module IDL—Idle Sequence Status Changed This bit indicates that a change in the status of the serial line has occurred. The real-time status of the line can be read in the SCCS–ASYNC HDLC register. TXE—TX Error This bit indicates that an error has occurred on the transmitter channel.
Page 735 Freescale Semiconductor, Inc. Communication Processor Module 16.9.19.12.5 Differences Between HDLC and ASYNC HDLC. There are four main differences between the HDLC and ASYNC HDLC modes of operation: • There is no maximum received frame length counter in the ASYNC HDLC controller.
Page 736 Freescale Semiconductor, Inc. Communication Processor Module 13. Program the transmit and receive control character tables. 14. Initialize all RX buffer descriptors. 15. Initialize all TX buffer descriptors. 16. Clear the SCCE–ASYNC HDLC register by writing 0xFFFF to it. 17. Program the SCCM–ASYNC HDLC register with the proper mask to allow all preferred interrupts.
Page 737 Freescale Semiconductor, Inc. Communication Processor Module 16.9.20.1 LOW-SPEED IRDA PROTOCOL. The low-speed IrDA protocol consists of a data link layer and a physical layer. • The data link layer is based on a preexisting ASYNC HDLC protocol standard. See Section 16.9.19 The SCCx in Asynchronous HDLC Mode for more details. 0xC0 is used as a start flag and 0xC1 is used as an end flag.
Page 738 Freescale Semiconductor, Inc. Communication Processor Module 16.9.20.2 MIDDLE-SPEED IRDA PROTOCOL. The middle-speed IrDA protocol consists of a data link layer and a physical layer. • The data link layer is derived from the preexisting synchronous HDLC protocol standard. The frame format follows the standard HDLC format except that it requires two start flags.
Page 739 Freescale Semiconductor, Inc. Communication Processor Module 16.9.20.3 HIGH-SPEED IRDA PROTOCOL. The high-speed IrDA protocol is derived from the preexisting SCCx Transparent protocol standard. 16.9.20.3.1 4PPM Data Encoding. Pulse position modulation (PPM) encoding is achieved by defining a data symbol duration (Dt) and subsequently subdividing Dt into a set of equal time slices called “chips”.
Page 740 Freescale Semiconductor, Inc. Communication Processor Module Logical “1” represents a chip duration when the transmitting LED is emitting light, while logical “0” represents a chip duration when the LED is off. Data encoding for transmission is done LSB first. The 4PPM data encoding defines only the legal encoded payload data symbols.
Page 741 Freescale Semiconductor, Inc. Communication Processor Module The link layer frame generally consists of the address, control, data and CRC32 fields. The IrDA transmitter decodes the packet bits into 4PPM format. The 4PPM encoding will be described later. The receiver is responsible to decode the incoming data frame into the regular bit format and to deliver it to the software.
Page 742 Freescale Semiconductor, Inc. Communication Processor Module 16.9.20.4 SERIAL INFRARED INTERACTION PULSES. To guarantee nondisruptive coexistence with slower (a maximum of 115.2Kb/s) systems, once a high-speed (above 115.2Kb/s) connection has been established the high-speed system must emit a serial infrared interaction pulse (SIP) at least once every 500ms. This continues for the duration of the connection to quiet slower systems that might interfere with the link.
Page 743 Freescale Semiconductor, Inc. Communication Processor Module 16.9.20.5 PROGRAMMING MODEL 16.9.20.5.1 SCC2 Infrared Mode Register. The SCC2 serial infrared mode (IRMODE) register controls the infrared operation mode (low-, middle-, or high speed), the number of preambles, the loop mode, the full-duplex operation, and the DPLL clock rate.
Page 744 Freescale Semiconductor, Inc. Communication Processor Module DCR—IrDA DPLL Clock Ratio This field determines the clock ratio between the IrDA DPLL clock and the bit rate clock. This field is valid only in high-speed mode. 00 = 12x bit rate clock.
Page 745 Freescale Semiconductor, Inc. Communication Processor Module 16.9.20.5.2 SCC2 Infrared Serial Interaction Pulse Control Register. The SCC2 infrared serial interaction pulse control (IRSIP) register controls the initiation of the serial infrared interaction pulse. IRSIP FIELD RESET ADDR (IMMR & 0xFFF0000) + 0xA3A Bits 0 and 3—Reserved...
Page 746 Freescale Semiconductor, Inc. Communication Processor Module 16.9.20.5.3 Low-Speed IrDA Programming Guide. Low-speed infrared programming is very similar to SCC2 ASYNC HDLC programming. The only difference is the value of EOF and BOF in the SCC2 parameter RAM and the programming of the IRMODE register. Use the following initialization sequence for low-speed infrared.
Page 747 Freescale Semiconductor, Inc. Communication Processor Module 16.9.20.5.4 Middle-Speed IrDA Programming Example. Middle-speed infrared programming is very similar to SCC2 synchronous HDLC programming. The parameter RAM programming and the RX and TX buffer descriptors are the same as in the SCC2 HDLC.
Page 748 Freescale Semiconductor, Inc. Communication Processor Module 20. Write 0x001A to the SCCM–HDLC to enable the TXE, RXF, and TXB interrupts. 21. Write 0x20000000 to the CIMR to allow the SCC2 to generate a system interrupt. The CICR must also be initialized.
Page 749 Freescale Semiconductor, Inc. Communication Processor Module 16.9.20.5.5 High-Speed IrDA Programming Example. High-speed infrared programming is very similar to SCC2 Transparent programming. The parameter RAM programming and the RX buffer descriptor and TX buffer descriptor are the same as in the SCCx transparent mode, which is described in Section 16.9.21 The SCCx in Transparent...
Page 750 Freescale Semiconductor, Inc. Communication Processor Module 17. Write 0x00009980 to the GSMR_H to configure the transparent channel. The CDS and CTSS bits must be set to one. The TDCR, RDCR, RENC, and TENC fields must be set to zero. 18. Write 0x00000000 to the GSMR_L. Normal operation of the transmit clock is used (TCI bit is cleared).
Page 751 Freescale Semiconductor, Inc. Communication Processor Module If just one of the TTX or TRX bits is set, the other half of a serial communication controller operates with another protocol as programmed in the MODE field of the GSMR_L. This allows loopback modes to DMA data from one memory location to another while converting the data to a specific serial format.
Page 752 Freescale Semiconductor, Inc. Communication Processor Module In both cases, an interrupt is issued according to the I bit in the RX or TX buffer descriptor. By appropriately setting the I bit in each buffer descriptor, interrupts are generated after each buffer or group of buffers is transmitted.
Page 753 Freescale Semiconductor, Inc. Communication Processor Module 16.9.21.4.1 Inline Synchronization Pattern. The transparent channel can be programmed to transmit and receive a synchronization pattern if the SYNL field in the GSMR_H are not zero. This pattern is defined in the data synchronization register and the length of the Sync pattern is defined in the SYNL field.
Page 754 Freescale Semiconductor, Inc. Communication Processor Module The receiver synchronizes on the synchronization pattern that is located in the DSR. For instance, if 4-BIT SYNC is selected, reception begins as soon as these four bits are received, beginning with the first bit following the 4-BIT SYNC field. The transmitter synchronizes on the receiver pattern if the RSYN bit of the GSMR_H is set.
Page 755 Freescale Semiconductor, Inc. Communication Processor Module 16.9.21.4.3 Transparent Synchronization Example. Figure 16-103 illustrates an example of synchronization using the external signals. MPC823 (A) MPC823 (B) TXDx RXDx RTSx BRGOx CLKx RXDx TXDx RTSx CLKx BRGOx NOTES: 1. Each MPC82x generates its own transmit clocks. If the transmit and receive clocks are the same, one MPC82x can generate transmit and receive clocks for the other MPC82x.
Page 756 Freescale Semiconductor, Inc. Communication Processor Module 16.9.21.5 SCCx TRANSPARENT PARAMETER RAM MEMORY MAP. In totally Transparent mode, a serial communication controller overlays the structure used in Table 16-24 with the transparent parameters described in Table 16-29. Table 16-29. SCCx Transparent Parameter RAM Memory Map...
Page 757 Freescale Semiconductor, Inc. Communication Processor Module • GRACEFUL STOP TRANSMIT—This command is used to stop transmission smoothly, rather than abruptly, in much the same way that the regular STOP TRANSMIT command stops. It stops transmission after the current frame finishes or immediately if there is no frame being transmitted.
Page 758 Freescale Semiconductor, Inc. Communication Processor Module 16.9.21.7 SCCx TRANSPARENT CONTROLLER ERRORS. The serial communication controllers report message reception and transmission errors using the channel buffer descriptors, the error counters, and the SCCE–Transparent register. The following transmission errors can be detected by the SCCx Transparent controller.
Page 759 Freescale Semiconductor, Inc. Communication Processor Module 16.9.21.9 SCCx TRANSPARENT RECEIVE BUFFER DESCRIPTOR. The communication processor module reports information about the received data for each buffer using a channel’s receive (RX) buffer descriptor, closes the current buffer, generates a maskable interrupt, and starts receiving data into the next buffer after one of the following events occurs: •...
Page 760 Freescale Semiconductor, Inc. Communication Processor Module W—Wrap (Final Buffer Descriptor in Table) 0 = This is not the last buffer descriptor in the RX buffer descriptor table. 1 = This is the last buffer descriptor in the RX buffer descriptor table. After this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that RBASE points to in the table.
Page 761 Freescale Semiconductor, Inc. Communication Processor Module CR—CRC Error indication bits This bit indicates that this frame contains a CRC error. The received CRC bytes are always written to the receive buffer. OV—Overrun This bit indicates that a receiver overrun has occurred during buffer reception.
Page 762 Freescale Semiconductor, Inc. Communication Processor Module R—Ready 0 = The data buffer associated with this buffer descriptor is not ready for transmission. You are free to manipulate this buffer descriptor or its associated data buffer. The communication processor module clears this bit after the buffer is transmitted or after an error condition is encountered.
Page 763 Freescale Semiconductor, Inc. Communication Processor Module UN—Underrun This bit indicates that a serial communication controller has encountered a transmitter underrun condition while transmitting the associated data buffer. CT—CTS Lost This bit indicates the CTSx signal has been lost during frame transmission.
Page 764 Freescale Semiconductor, Inc. Communication Processor Module GLT—Glitch on TX If set, this bit indicates that a serial communication controller has found a glitch on the transmit clock. DCC—DPLL CS Changed This bit indicates when the carrier sense status, which is generated by the DPLL, changes state.
Page 765 Freescale Semiconductor, Inc. Communication Processor Module 16.9.21.12 SCCx TRANSPARENT MASK REGISTER. When a serial communication controller is in transparent mode, the 16-bit read/write SCCx mask register is referred to as the SCCx transparent mask (SCCM–Transparent) register. Since each protocol has specific requirements, the SCCM bits are different for each implementation.
Page 766 Freescale Semiconductor, Inc. Communication Processor Module 16.9.21.14 SCC2 TRANSPARENT PROGRAMMING EXAMPLE. The following is an example initialization sequence for SCC2 in transparent mode. The transmitter and receiver are both enabled, but operate independently of each other. They implement the connection illustrated on MPC823 (B) in Figure 16-103.
Page 767 Freescale Semiconductor, Inc. Communication Processor Module 19. Write 0x00000000 to the GSMR_L to configure the CTS2 and CD2 pins to automatically control transmission and reception (DIAG field). Normal operation of the transmit clock is used. Notice that the transmitter (ENT) and receiver (ENR) are not enabled yet.
Page 768 Freescale Semiconductor, Inc. Communication Processor Module When a station needs to transmit, it checks for activity on the LAN and when the LAN becomes silent for a specified period, the station starts transmitting. At that time, the station continually checks for collision on the LAN and if one is found, the station forces a jam of all ones on its frame and stops transmitting.
Page 769 Freescale Semiconductor, Inc. Communication Processor Module 16.9.22.2 ETHERNET ON THE MPC823. When the MODE field in the general SCCx mode low register (GSMR_L) selects an SCCx to be in Ethernet mode, the serial communication controllers perform the full set of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface functions.
Page 770 Freescale Semiconductor, Inc. Communication Processor Module 16.9.22.3 UNDERSTANDING ETHERNET ON THE MPC823. You are encouraged to learn about the basic functionality of the serial communication controllers and the overall architecture of the communication processor module before delving into the functionality of the SCCs in Ethernet mode.
Page 771 Freescale Semiconductor, Inc. Communication Processor Module Figure 16-106 illustrates the basic components and pins required to make the Ethernet connection between the MPC823 and EEST. MPC823 MPC823 EEST MC68160 RJ-45 SCCx TXDx TWISTED PAIR TENA (RTSx) TENA TCLK (CLKx) TCLK...
Page 772 Freescale Semiconductor, Inc. Communication Processor Module The EEST has similar names for its connection to the seven MPC823 pins mentioned above and contains a loopback pin so the MPC823 can perform external loopback testing. This can be controlled by any available parallel I/O pin on the MPC823. The passive components that are needed to connect to AUI or twisted-pair media are external to the EEST.
Page 773 Freescale Semiconductor, Inc. Communication Processor Module When the end of the current buffer descriptor is reached and the L bit in the TX buffer descriptor is set, the frame collision support bytes of the Ethernet frame are appended (if the TC bit is set in the TX buffer descriptor), and TENA is negated.
Page 774 Freescale Semiconductor, Inc. Communication Processor Module If a match is found, the SCCx Ethernet controller fetches the next RX buffer descriptor and, if it is empty, starts transferring the incoming frame to the RX buffer descriptor associated data buffer. If a collision is detected during the frame, the RX buffer descriptors associated with this frame are reused.
Page 775 Freescale Semiconductor, Inc. Communication Processor Module 16.9.22.7 SCCx ETHERNET PARAMETER RAM MEMORY MAP. When a serial communication controller is configured to operate in Ethernet mode, it overlays the structure used in Table 16-24 onto the parameters described in Table 16-30.
Page 776 Freescale Semiconductor, Inc. Communication Processor Module Table 16-30. SCCx Ethernet Parameter RAM Memory Map (Continued) ADDRESS NAME WIDTH DESCRIPTION SCCx Base + 80 TBUF1_DATA0 Word Save Area 0–Next Frame SCCx Base + 84 TBUF1_DATA1 Word Save Area 1–Next Frame SCCx Base + 88...
Page 777 Freescale Semiconductor, Inc. Communication Processor Module • MFLR—The SCCx Ethernet controller checks the length of an incoming Ethernet frame against the user-defined value given in this 16-bit register. Typically this register is set to 0x5EE. If this limit is exceeded, the remainder of the incoming frame is discarded and the LG bit is set in the last RX buffer descriptor belonging to that frame.
Page 778 Freescale Semiconductor, Inc. Communication Processor Module • TBUF0_CRC—For internal use only. • TBUF0_BCNT—For internal use only. • PADDR1—You must write the 48-bit individual address of the station into this location. PADDR1_L is the lowest order half-word, PADDR1_H is the highest order half-word and PADDR_M is the middle half-word.
Page 779 Freescale Semiconductor, Inc. Communication Processor Module 16.9.22.8 CONFIGURING THE SCCx ETHERNET PARAMETERS. You can configure a serial communication controller to operate in Ethernet mode by setting the MODE field in the general SCCx mode low register (GSMR_L). The receive errors are reported in the RX buffer descriptor and the transmit errors are reported in the TX buffer descriptor.
Page 780 Freescale Semiconductor, Inc. Communication Processor Module • GRACEFUL STOP TRANSMIT —This command is used to ensure that transmission stops smoothly after the current frame finishes or undergoes a collision. The GRA bit in the SCCE–Ethernet register is set once transmission stops. Then you can modify the Ethernet transmit parameters and their buffer descriptors.
Page 781 Freescale Semiconductor, Inc. Communication Processor Module • SET GROUP ADDRESS—This command is used to set a bit in one of the 64 bits of the four individual/group address hash filter registers. The individual or group address to be added to the hash table must be written to TADDR_L, TADDR_M, and TADDR_H in the parameter RAM before executing this command.
Page 782 Freescale Semiconductor, Inc. Communication Processor Module CHECK ADDRESS I/G ADDRESS MULTIPLE MULTIPLE INDIVIDUAL BROADCAST ADDRESSES ADDR HASH SEARCH HASH_SEARCH BROADCAST USE GROUP USE INDICATED ENABLED TABLE TABLE MATCH ? MATCH ? RECEIVE FRAME IGNORE RRJCT PIN RECEIVE FRAME IGNORE MATCH ?
Page 783 Freescale Semiconductor, Inc. Communication Processor Module In group address recognition, the SCCx Ethernet controller determines whether or not the group address is a broadcast address. If broadcast addresses are enabled, then the frame is accepted, but if the group address is not a broadcast address, then you can perform address recognition on multiple group addresses using the GADDR1–4 hash table.
Page 784 Freescale Semiconductor, Inc. Communication Processor Module 16.9.22.12 INTERPACKET GAP TIME. The minimum interpacket gap time for back-to-back transmission is 9.6µs. The receiver receives back-to-back frames with this minimum spacing. In addition, after the backoff algorithm, the transmitter waits for carrier sense to be negated before retransmitting the frame.
Page 785 Freescale Semiconductor, Inc. Communication Processor Module 16.9.22.15 SCCx ETHERNET CONTROLLER ERRORS. The SCCx Ethernet controller reports frame reception and transmission error conditions using the channel buffer descriptors, the error counters, and the SCCE–Ethernet register. The following transmission errors can be detected by the SCCx Ethernet controller.
Page 786 Freescale Semiconductor, Inc. Communication Processor Module • Non-Octet Error (Dribbling Bits) — The SCCx Ethernet controller handles up to seven dribbling bits when the receive frame terminates nonoctet aligned and it checks the CRC of the frame on the last octet boundary. If there is a CRC error, then the frame nonoctet aligned error is reported, the RXF bit is set, and the alignment error counter is incremented.
Page 787 Freescale Semiconductor, Inc. Communication Processor Module IAM—Individual Address Mode 0 = Normal operation. A single 48-bit physical address that is stored in PADDR1_x is checked when it is received. 1 = The individual hash table is used to check all individual addresses that are received.
Page 788 Freescale Semiconductor, Inc. Communication Processor Module NIB—Number of Ignored Bits This parameter determines how soon after RENA assertion the SCCx Ethernet controller must begin looking for the start frame delimiter. In most situations, it is recommended that you select 22 bits.
Page 789 Freescale Semiconductor, Inc. Communication Processor Module 16.9.23.2 SCCx ETHERNET RECEIVE BUFFER DESCRIPTOR. The SCCx Ethernet controller uses the receive (RX) buffer descriptor to report information about the received data for each buffer. Figure 16-107 illustrates an Ethernet receive buffer descriptor example.
Page 790 Freescale Semiconductor, Inc. Communication Processor Module OFFSET + 0 DATA LENGTH OFFSET + 2 OFFSET + 4 RX DATA BUFFER POINTER OFFSET + 6 NOTE: You are only responsible for initializing the items in bold. Note: The communication processor module sets all the status bits in this buffer descriptor, but you must clear them before submitting the buffer descriptor to the communication processor module.
Page 791 Freescale Semiconductor, Inc. Communication Processor Module L—Last in Frame The Ethernet controller sets this bit when this buffer is the last one in a frame. If the end of a frame is reached or an error is received, one or more of the CL, OV, CR, SH, NO, and LG bits are set.
Page 792 Freescale Semiconductor, Inc. Communication Processor Module DATA LENGTH This field represents the number of octets the communication processor module writes into this buffer descriptor data buffer. It is written by the communication processor module once the buffer is closed. When this buffer descriptor is the last buffer descriptor in the frame, the DATA LENGTH contains the total number of frame octets (including four bytes for CRC).
Page 793 Freescale Semiconductor, Inc. Communication Processor Module PAD—Short Frame Padding This bit is only valid when the L bit is set. Otherwise, it is ignored. 0 = Do not add pads to short frames. 1 = Add pads to short frames. Pad bytes are inserted until the length of the transmitted frame equals the MINFLR and they are stored in pads in the parameter RAM.
Page 794 Freescale Semiconductor, Inc. Communication Processor Module LC—Late Collision This bit indicates that a collision occurred after the number of bytes defined for the LCW bit in the PSMR–SCC Ethernet are transmitted. The SCCx Ethernet controller stops transmitting and writes this bit after it finishes transmitting the associated data buffer.
Page 795 Freescale Semiconductor, Inc. Communication Processor Module 16.9.23.4 SCCx ETHERNET EVENT REGISTER. When a serial communication controller is in Ethernet mode, the 16-bit memory-mapped SCCx event register is referred to as the SCCx Ethernet event register (SCCE–Ethernet). Since each protocol has specific requirements, the SCCE bits are different for each implementation.
Page 796 Freescale Semiconductor, Inc. Communication Processor Module TXB—TX Buffer This bit indicates that a buffer has been transmitted on the Ethernet channel. RXB—RX Buffer This bit indicates that a buffer that was not a complete frame was received on the Ethernet channel.
Page 797 Freescale Semiconductor, Inc. Communication Processor Module 16.9.23.5 SCCx ETHERNET MASK REGISTER. When a serial communication controller is in Ethernet mode, the 16-bit read/write SCCx mask register is referred to as the SCCx Ethernet mask register (SCCM–Ethernet). Since each protocol has specific requirements, the SCCM bits are different for each implementation.
Page 798 Freescale Semiconductor, Inc. Communication Processor Module 9. Program the CPCR to execute the INIT RX BD PARAMETER command for this channel. 10. Write RFCR and TFCR with 0x18 for normal operation. 11. Write MRBLR with the maximum number of bytes per receive buffer. For this case, assume 1,520 bytes, so MRBLR = 0x05F0.
Page 799 Freescale Semiconductor, Inc. Communication Processor Module 31. Write 0x1088000C to the GSMR_L to configure the CTS2 (CLSN) and CD2 (RENA) pins to automatically control transmission and reception (DIAG field) and the Ethernet mode. TCI is set to allow more setup time for the EEST to receive the MPC82 transmit data.
Page 800 Freescale Semiconductor, Inc. Communication Processor Module The USB transmitter contains four independent FIFOs, each containing 16 bytes. There is a dedicated FIFO for each of the four supported endpoints. The USB receiver has a single 16-byte FIFO. When the USB controller is not enabled in the USB mode register, it consumes minimal power.
Page 801 Freescale Semiconductor, Inc. Communication Processor Module 16.10.1 Features The following list summarizes the USB slave mode features: • Supports USB slave mode • Four independent endpoints support control, bulk, interrupt and isochronous data transfers • CRC16 generation and checking • NRZI encoding/decoding with bit stuffing •...
Page 802 Freescale Semiconductor, Inc. Communication Processor Module 16.10.3 USB Controller Pin Functions and Clocking The USB controller interfaces to the USB through a differential line driver and receiver. The OE signal enables the line driver when the USB controller transmits on the bus.
Page 803 Freescale Semiconductor, Inc. Communication Processor Module Table 16-31. USB Pin Functionality PIN SYMBOL FUNCTION USBTXN, USBTXP Outputs from the USB transmitter, inputs to the differential driver. RESULT single ended “0” logic “0” logic “1” USBOE Output Enable. Active low, enables the transceiver to transmit data on the bus.
Page 804 Freescale Semiconductor, Inc. Communication Processor Module 16.10.4 Transmission and Reception Process After reset, the USB controller is addressable at the default address (0x00). During the enumeration process, the host assigns a unique address to the USB controller. The software must program the USB address register with the assigned address. The USB controller...
Page 805 Freescale Semiconductor, Inc. Communication Processor Module 16.10.4.1 OUT TOKEN. When the USB controller receives an OUT token, data reception begins. The USB controller fetches the next buffer descriptor associated with the endpoint and if it is empty, it starts transferring the incoming packet to the buffer descriptor’s associated data buffer.
Page 806 Freescale Semiconductor, Inc. Communication Processor Module 16.10.4.2 IN TOKEN. To guarantee data transfer, the control software must preload the endpoint FIFO with a data packet prior to receiving an IN token. The software must set up the endpoint transmit buffer descriptor table and set the STR bit in the USB command register.
Page 807 Freescale Semiconductor, Inc. Communication Processor Module 16.10.4.4 SOF TOKEN. When a start of frame (SOF) token packet is received, the USB controller issues a SOF maskable interrupt and the frame number entry in the parameter RAM is updated. 16.10.4.5 PRE TOKEN. The PRE token signals the hub that a low-speed transaction is about to occur.
Page 808 Freescale Semiconductor, Inc. Communication Processor Module You must initialize certain parameter RAM values before the USB controller is enabled. Other values are initialized by the communication processor module. Once initialized, the parameter RAM values do not need to be accessed by your software. They must only be modified when there is no USB activity.
Page 809 Freescale Semiconductor, Inc. Communication Processor Module The V bit is set if the SOF token was received error-free. Table 16-35. Endpoint Parameters Block ADDRESS NAME WIDTH DESCRIPTION Base + 00 RBASE Half Word RX Buffer Descriptor Base Address Base + 02...
Page 810 Freescale Semiconductor, Inc. Communication Processor Module • RFCR and TFCR—The USB function code registers control the value that you want to appear on the AT pins when the associated SDMA channel accesses memory. It also controls the byte-ordering convention to be used in the transfers.
Page 811 Freescale Semiconductor, Inc. Communication Processor Module Note: MRBLR is not intended to be dynamically changed while the USB channel is operating. However, if it is modified in a single bus cycle with one 16-bit move (not two 8-bit bus cycles back-to-back), then a dynamic change in the receive buffer length can be successfully achieved.
Page 812 Freescale Semiconductor, Inc. Communication Processor Module 16.10.6 USB Commands You can program the CPM command register (CPCR) with the following commands to transmit data. USB COMMAND FORMAT (CPCR) FIELD USBCMD ENDPOINT RESET ADDR (IMMR & 0xFFFF0000) + 0x9C0 • RST—The reset bit is set by the core and cleared by the communication processor module and when this command is executed, RST and FLG are cleared within two general system clocks.
Page 813 Freescale Semiconductor, Inc. Communication Processor Module • FLG—The bit is set by the core and cleared by the communication processor module. 0 = The communication processor module is ready to receive a new command. 1 = The CPCR contains a command that the communication processor module is currently processing.
Page 814 Freescale Semiconductor, Inc. Communication Processor Module 16.10.8 USB Controller Programming Model 16.10.8.1 USB MODE REGISTER. The read/write USB mode (USMOD) register controls the USB controller’s operation mode. USMOD FIELD RESUME RESERVED TEST HOST RESET ADDR (IMMR & 0xFFFF0000) + 0xA00 LSS—Low-Speed Signaling...
Page 815 Freescale Semiconductor, Inc. Communication Processor Module EN—Enable USB This bit enables USB operation. When the EN bit is cleared, the USB is in a reset state and consumes minimal power. 0 = USB is disabled. 1 = USB is enabled.
Page 816 Freescale Semiconductor, Inc. Communication Processor Module E—Empty 0 = The data buffer associated with this RX buffer descriptor has been filled with received data or data reception has been aborted due to an error condition. The core is free to examine or write to any fields of this RX buffer descriptor. The communication processor module will not use this buffer descriptor again when the E bit is zero.
Page 817 Freescale Semiconductor, Inc. Communication Processor Module PID—Packet ID This field is set by the USB controller to indicate the type of the packet. It is only valid if the F bit is set. This field is written by the USB controller after the received data has been placed into the associated data buffer.
Page 818 Freescale Semiconductor, Inc. Communication Processor Module 16.10.8.3 USB TRANSMIT BUFFER DESCRIPTOR. Data to be transmitted with the USB is presented to the communication processor module by arranging it in buffers referenced by the transmit (TX) buffer descriptor ring. The first word of the TX buffer descriptor contains status and control bits.
Page 819 Freescale Semiconductor, Inc. Communication Processor Module L—Last 0 = This buffer does not contain the last character of the message. 1 = This buffer contains the last character of the message. TC—Transmit CRC This bit is only valid when the L bit is set. Otherwise, it is ignored.
Page 820 Freescale Semiconductor, Inc. Communication Processor Module STAL—STALL Handshake Received (Host) This bit indicates that the endpoint has responded with a STALL handshake. The endpoint needs attention through the control pipe. This bit is written by the USB controller after it has finished transmitting the associated data buffer.
Page 821 Freescale Semiconductor, Inc. Communication Processor Module 16.10.8.5 USB COMMAND REGISTER. The 8-bit, read/write USB command (USCOM) register is used to start USB transmit operation. USCOM FIELD FLUSH RESERVED RESET ADDR (IMMR & 0xFFFF0000) + 0xA02 STR—Start FIFO Fill When set, this bit causes the USB controller to start filling the corresponding endpoint transmit FIFO with data.
Page 822 Freescale Semiconductor, Inc. Communication Processor Module 16.10.8.6 USB ENDPOINT CONFIGURATION REGISTERS 0–3. There are four 16-bit, memory-mapped, read/write USB endpoint configuration (USEPx) registers. USEP0–USEP3 FIELD RESERVED RESERVED RESET ADDR (IMMR & 0xFFFF0000) + 0xA04 (USEP0), 0xA06 (USEP1), 0xA08 (USEP2), 0xA0A (USEP3) EPN—...
Page 823 Freescale Semiconductor, Inc. Communication Processor Module THS—Transmit Handshake (Slave Mode Only) 00 = Normal handshake. 01 = Ignore IN token. 10 = Force NAK handshake. Not allowed for control endpoint. 11 = Force STALL handshake. Not allowed for control endpoint.
Page 824 Freescale Semiconductor, Inc. Communication Processor Module DUAL- PORT RAM TX BUFFER DESCRIPTORS EXTERNAL MEMORY FRAME STATUS USB ENDPOINT 1 DATA LENGTH ENDPOINT 0 TX DATA BUFFER TX BD TABLE DATA POINTER TX BUFFER DESCRIPTORS ENDPOINT 3 TX BD TABLE FRAME STATUS...
Page 825 Freescale Semiconductor, Inc. Communication Processor Module 16.10.8.8 USB EVENT REGISTER. The 16-bit, memory-mapped USB event register (USBER) is used to generate interrupt events and report events recognized by the USB channel. When an event is recognized, the USB sets the corresponding bit in the USBER.
Page 826 Freescale Semiconductor, Inc. Communication Processor Module 16.10.8.9 USB MASK REGISTER. The 16-bit read/write USB mask register (USBMR) has the same bit formats as the USB event register. If a bit in the USBMR is one, the corresponding interrupt in the USBER is enabled. If the bit is zero, the corresponding interrupt in the USBER will be masked.
Page 827 Freescale Semiconductor, Inc. Communication Processor Module 16.10.8.11 USB CONTROLLER INITIALIZATION EXAMPLE (FUNCTION MODE). The following is an example initialization sequence for the USB controller operating in function mode. It can be used to set up four function endpoints (0–3) that fill up transmit FIFOs, so that data is ready for transmission when an IN token is received from the USB.
Page 828 Freescale Semiconductor, Inc. Communication Processor Module 20. Write 20002020 to DPRAM+500 to set up the RBASE and TBASE fields of the endpoint 0 parameter RAM. 21. Write 18180100 to DPRAM+504 to set up the RFCR, TFCR and MRBLR fields of the endpoint 0 parameter RAM.
Page 829 Freescale Semiconductor, Inc. Communication Processor Module 16.10.9 Using the USB Controller as a Host This section describes the full implementation of host mode, which is available for Revision B (and later) of the MPC823 silicon. Earlier revisions of the MPC823 only support high-speed (12Mbs) host mode operation.
Page 830 Freescale Semiconductor, Inc. Communication Processor Module 10. Write DPRAM+210 to DPRAM+2C to set up the TX DATA BUFFER POINTER field of the endpoint 1 TX buffer descriptor. 11. Write 0x698560 to DPRAM+200 to set up the endpoint 0 TX data pattern. This pattern consists of the IN token and the CRC5.
Page 831 Freescale Semiconductor, Inc. Communication Processor Module The expected results are as follows: • The TX buffer descriptor (Ep0) CONTROL/STATUS field must contain 0x3800. • The TX buffer descriptor (Ep0) DATA LENGTH field must contain 0x0003. • The TX buffer descriptor (Ep1) CONTROL/STATUS field must contain 0x3c80.
Page 832 Freescale Semiconductor, Inc. Communication Processor Module Each serial management controller supports the circuit interface and monitor channels of the GCI bus. In which case, the serial management controller is connected to the TDM channel in the serial interface. For testing purposes, the serial management controllers support loopback and echo modes.
Page 833 Freescale Semiconductor, Inc. Communication Processor Module If the serial management controllers are connected to the TDM, it gets its synchronization pulse from the time-slot assigner. Otherwise, if a serial management controller is connected to the NMSI and the Transparent protocol is selected, the serial management controller can use the SMSYNx pin as a synchronization pin to determine when it must start transmitting and receiving.
Page 834 Freescale Semiconductor, Inc. Communication Processor Module In UART and Transparent modes, the serial management controllers have a memory structure that is similar to the serial communication controllers. Each buffer is referenced by a buffer descriptor and organized in a buffer descriptor ring located in the dual-port RAM, as illustrated in Figure 16-114.
Page 835 Freescale Semiconductor, Inc. Communication Processor Module • The parameter RAM values that pertain to the SMCx transmitter can only be written when the TEN bit in the SMCMR is zero or after the STOP TRANSMIT command is issued, but before the RESTART TRANSMIT command is issued.
Page 836 Freescale Semiconductor, Inc. Communication Processor Module • RBASE and TBASE—These entries are used by the dual-port RAM starts the SMCx receive and transmit buffer descriptors. They provide a great deal of flexibility for partitioning the buffer descriptors for a serial management controller. By selecting...
Page 837 Freescale Semiconductor, Inc. Communication Processor Module 01 = PowerPC little-endian byte ordering. As data is transmitted onto the serial line from the data buffer, the least-significant byte of the buffer double-word contains data to be transmitted earlier than the most-significant byte of the same buffer double-word.
Page 838 Freescale Semiconductor, Inc. Communication Processor Module AT—Address Type 1–3 These bits contain the function code value used during this SDMA channel memory access. The AT0 pin is driven with a 1 to identify this SDMA channel access as a DMA type.
Page 839 Freescale Semiconductor, Inc. Communication Processor Module • Other General Parameters—You do not need to access these parameters during normal operation. They are only listed because they provide helpful debugging information. Additional parameters are listed in Table 16-33 (page 16-354). The RX and TX internal data pointers are updated by the SDMA channels to show the next address in the buffer to be accessed.
Page 840 Freescale Semiconductor, Inc. Communication Processor Module 16.11.5.1 DISABLING THE ENTIRE SMCx TRANSMITTER. Follow these steps to fully enable or disable the SMCx transmitter: 1. Issue the STOP TRANSMIT command. This command is recommended when a serial management controller is transmitting data since it stops transmission smoothly. This command is not required if a serial management controller is not transmitting, if you overwrite the TBPTR or if you execute the INIT TX PARAMETERS command.
Page 841 Freescale Semiconductor, Inc. Communication Processor Module 16.11.5.4 DISABLING PART OF THE SMCx RECEIVER. Follow this shorter sequence to reinitialize the receive parameters to the state they were in after reset. 1. Clear the REN bit in the SMCMR. 2. INIT RX PARAMETERS command and make any additional modifications.
Page 842 Freescale Semiconductor, Inc. Communication Processor Module A serial management controller in UART mode has one feature that an SCCx in UART mode does not. Data length on an SMCx can be a maximum of 14 bits, whereas, a serial communication controller only allows 8 bits. A serial management controller in UART mode is also referred to as a SMCx UART controller.
Page 843 Freescale Semiconductor, Inc. Communication Processor Module When the buffer descriptor data is completely written to the transmit FIFO, the SMCx UART controller writes the message status bits into the buffer descriptor and clears the R bit. An interrupt is issued if the I bit in the buffer descriptor is set. If the next TX buffer descriptor is ready, the data from its data buffer is appended to the previous data and transmitted out on the transmit pin, without any gaps between the buffers.
Page 844 Freescale Semiconductor, Inc. Communication Processor Module • MAX_IDL—Once a character of data is received on the line, the SMCx UART controller starts counting any idle characters received. If a MAX_IDL number of idle characters is received before the next data character, an idle timeout occurs and the buffer closes.
Page 845 Freescale Semiconductor, Inc. Communication Processor Module 16.11.6.6 SMCx UART COMMANDS. You can program the CPM command register (CPCR) with the following commands to transmit data. • STOP TRANSMIT—This command disables the transmission of characters on the transmit channel. If the SMCx UART controller receives this command while transmitting a message, it stops transmitting.
Page 846 Freescale Semiconductor, Inc. Communication Processor Module 16.11.6.8 SENDING A PREAMBLE. A preamble sequence provides a convenient way for you to ensure that the line is idle before you start a new message. The preamble sequence is constructed of consecutive ones that are one character long. If the preamble bit in a buffer descriptor is set, a serial management controller sends a preamble sequence before transmitting that data buffer.
Page 847 Freescale Semiconductor, Inc. Communication Processor Module 16.11.6.10 SMCx UART MODE REGISTER. When a serial management controller is in UART mode, the 16-bit, memory-mapped, read/write SMCx mode register is referred to as the SMCx UART mode register (SMCMR–UART). The functionality of bits 8-15 is common to each SMCx protocol, but bits 0-7 vary according to the protocol selected by the SM field.
Page 848 Freescale Semiconductor, Inc. Communication Processor Module PM—Parity Mode 0 = Odd parity. 1 = Even parity. SM—SMCx Mode 00 = GCI or SCIT support. 01 = Reserved. 10 = UART mode (must be selected for SMCx UART operation). 11 = Totally Transparent mode.
Page 849 Freescale Semiconductor, Inc. Communication Processor Module E—Empty 0 = The data buffer associated with this RX buffer descriptor is filled with received data or data reception is aborted due to an error condition. The core is free to examine or write to any fields of this RX buffer descriptor. The communication processor module does not use this buffer descriptor as long as the E bit is zero.
Page 850 Freescale Semiconductor, Inc. Communication Processor Module FR—Framing Error This bit indicates that a character with a framing error has been received and is located in the last byte of this buffer. A framing error is a character without a stop bit. A new receive buffer is used to receive additional data.
Page 851 Freescale Semiconductor, Inc. Communication Processor Module Figure 16-116 illustrates an example of the RX buffer descriptor process. It shows the resulting state of the RX buffer descriptors after they receive 10 characters, an idle period, and five characters (one with a framing error). The example assumes that MRBLR = 8 in the SMCx parameter RAM.
Page 852 Freescale Semiconductor, Inc. Communication Processor Module 16.11.6.12 SMCx UART TRANSMIT BUFFER DESCRIPTOR. Data is sent to the communication processor module for transmission on an SMCx channel by arranging it in buffers referenced by the channel’s transmit (TX) buffer descriptor ring. Using the buffer descriptors, the communication processor module confirms transmission or indicates error conditions so that the processor knows the buffers have been serviced.
Page 853 Freescale Semiconductor, Inc. Communication Processor Module CM—Continuous Mode 0 = Normal operation. 1 = The R bit is not cleared by the communication processor module after this buffer descriptor is closed, thus allowing the associated data buffer to be automatically retransmitted next time the communication processor module accesses this buffer descriptor.
Page 854 Freescale Semiconductor, Inc. Communication Processor Module 16.11.6.13 SMCx UART EVENT REGISTER. When a serial management controller is in UART mode, the 8-bit memory-mapped SMCx event register is referred to as the SMCx UART event (SMCE–UART) register. It is used to generate interrupts and report events recognized by the SMCx UART channel.
Page 855 Freescale Semiconductor, Inc. Communication Processor Module RX—Receive Buffer This bit indicates that a buffer has been received and its associated RX buffer descriptor is now closed. It is set in the middle of the last stop bit of the last character that is written to the receive buffer.
Page 856 Freescale Semiconductor, Inc. Communication Processor Module 16.11.6.14 SMCx UART MASK REGISTER. When a serial management controller is in UART mode, the 8-bit read/write SMCx mask register is referred to as the SMCx UART mask (SMCM–UART) register. It has the same bit format as the SMCE–UART register. If a bit in this register is a 1, the corresponding interrupt in the SMCE–UART register is enabled.
Page 857 Freescale Semiconductor, Inc. Communication Processor Module 12. Initialize the RX buffer descriptor. Assume the RX data buffer is at 0x00001000 in main memory. Write 0xB000 to RX_BD_Status, 0x0000 to RX_BD_Length (not required), and 0x00001000 to RX_BD_Pointer. 13. Initialize the TX buffer descriptor. Assume the TX data buffer is at 0x00002000 in main memory and contains five 8-bit characters.
Page 858 Freescale Semiconductor, Inc. Communication Processor Module 16.11.7 The SMCx in Transparent Mode A serial managment controller in Transparent mode is also referred to as the SMCx Transparent controller. The following is a list of the features that the SMCx Transparent controller does not support: •...
Page 859 Freescale Semiconductor, Inc. Communication Processor Module Synchronization can be achieved in two ways. First, when the transmitter is connected to the TDM channel, it can be synchronized to a time-slot. Once the frame sync is received, the transmitter waits for the first bit of its time-slot to occur before it starts transmitting. Data is only transmitted during the time-slots defined by the time-slot assigner.
Page 860 Freescale Semiconductor, Inc. Communication Processor Module 16.11.7.4 USING THE SMSYNx PIN FOR SYNCHRONIZATION. The SMSYNx pin offers a method to externally synchronize a SMCx Transparent channel. This method differs somewhat from the synchronization options available in the serial communication controllers and must be studied carefully. See Figure 16-118 for an example.
Page 861 Freescale Semiconductor, Inc. Communication Processor Module SMSYNx SMCLK SMC1 TRANSMIT DATA SMTXD 1s ARE SENT FIVE 1s ARE SENT TX FIFO FIVE 1s FIRST BIT OF TRANSMISSION SMSYNx LOADED ASSUME FIRST 5-BIT COULD BEGIN DETECTED APPX. CHARACTER TRANSMIT HERE IF TX FIFO...
Page 862 Freescale Semiconductor, Inc. Communication Processor Module 16.11.7.5 USING THE TIME-SLOT ASSIGNER FOR SYNCHRONIZATION. The time-slot assigner offers a method to internally synchronize a SMCx Transparent channel without using the SMSYNx pin. This method is similar to that of the SMSYNx pin, except that the synchronization event is not the falling edge of the SMSYNx signal, but the first time-slot for this SMCx receiver/transmitter after the frame sync indication.
Page 863 Freescale Semiconductor, Inc. Communication Processor Module Once the REN bit is set in the SMCMR, the first time-slot after frame sync causes the SMCx receiver to achieve synchronization. Data is received immediately, but only during the defined receive time-slots. The receiver continues receiving data during its defined time-slots until you clear the REN bit.
Page 864 Freescale Semiconductor, Inc. Communication Processor Module 16.11.7.6 SMCx TRANSPARENT CONTROLLER PARAMETER RAM MEMORY MAP. There is no protocol-specific parameter RAM for the SMCx Transparent controller. Only the general SMCx parameter RAM is used. See Section 16.11.4 SMC General Parameter RAM Memory Map for more information.
Page 865 Freescale Semiconductor, Inc. Communication Processor Module 16.11.7.8 SMCx TRANSPARENT CONTROLLER ERRORS. The serial management controllers report message reception and transmission error conditions using the channel buffer descriptors and the SMCE–Transparent register. The following transmission errors can be detected by the SMCx Transparent controller.
Page 866 Freescale Semiconductor, Inc. Communication Processor Module CLEN—Character Length This field is programmed with a value between 3 and 15 to obtain 4 to 16 bits per character. If the character length is less than 8 bits, the MSBs of the byte in buffer memory are not used on transmit and are written with zeros on receive.
Page 867 Freescale Semiconductor, Inc. Communication Processor Module REN—SMCx Receive Enable 0 = SMCx receiver disabled. 1 = SMCx receiver enabled. 16.11.7.10 SMCx TRANSPARENT RECEIVE BUFFER DESCRIPTOR. Using receive (RX) buffer descriptors, the communication processor module reports information about the received data for each buffer and closes the current buffer, generates a maskable interrupt, and starts to receive data into the next buffer after one of the following events occurs: •...
Page 868 Freescale Semiconductor, Inc. Communication Processor Module W—Wrap (Final Buffer Descriptor in Table) 0 = This is not the last buffer descriptor in the RX buffer descriptor table. 1 = This is the last buffer descriptor in the RX buffer descriptor table. After this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that RBASE points to in the table.
Page 869 Freescale Semiconductor, Inc. Communication Processor Module 16.11.7.11 SMCx TRANSPARENT TRANSMIT BUFFER DESCRIPTOR. Data is sent to the communication processor module for transmission on an SMCx channel by arranging it in buffers referenced by the channel’s transmit (TX) buffer descriptor table. Using the buffer descriptors, the communication processor module confirms transmission or indicates error conditions so that the processor knows the buffers have been serviced.
Page 870 Freescale Semiconductor, Inc. Communication Processor Module L— Last in Message 0 = The last byte in the buffer is not the last byte in the transmitted transparent frame. Data from the next transmit buffer (if ready) is transmitted immediately following the last byte of this buffer.
Page 871 Freescale Semiconductor, Inc. Communication Processor Module 16.11.7.12 SMCx TRANSPARENT EVENT REGISTER. When a serial management controller is in transparent mode, the 8-bit memory-mapped SMCx event register is referred to as the SMCx transparent event (SMCE–Transparent) register. It is used to generate interrupts and report events recognized by the SMCx channel.
Page 872 Freescale Semiconductor, Inc. Communication Processor Module 16.11.7.13 SMCx TRANSPARENT MASK REGISTER. When a serial management controller is in transparent mode, the 8-bit read/write SMCx mask register is referred to as the SMCx transparent mask (SMCM–Transparent) register. It has the same bit format as the SMCE–Transparent register.
Page 873 Freescale Semiconductor, Inc. Communication Processor Module 10. Initialize the TX buffer descriptor and assume the TX data buffer is at 0x00002000 in main memory and contains five 8-bit characters. Write 0xB000 to TX_BD_Status, 0x0005 to TX_BD_Length, and 0x00002000 to TX_BD_Pointer.
Page 874 Freescale Semiconductor, Inc. Communication Processor Module 7. Initialize the TX buffer descriptor and assume the TX data buffer is at 0x00002000 in main memory and contains five 8-bit characters. Write 0xB000 to TX_BD_Status, 0x0005 to TX_BD_Length, and 0x00002000 to TX_BD_Pointer.
Page 875 Freescale Semiconductor, Inc. Communication Processor Module To use the SMCx GCI channels properly, the time-slot assigner in the serial interface must be configured to route the monitor and circuit interface channels to the serial management controller you prefer. Refer to Section 16.7 The Serial Interface with Time-Slot Assigner for more details on how to program this configuration.
Page 876 Freescale Semiconductor, Inc. Communication Processor Module 16.11.8.2 SMCx GCI PARAMETER RAM MEMORY MAP. The SMCx GCI parameter RAM area begins at the same offset from each SMCx base area. The SMCx in GCI mode has a very different parameter RAM memory map than the SMCx in UART or transparent mode.
Page 877 Freescale Semiconductor, Inc. Communication Processor Module L—Last (EOM) This bit is only valid when a serial management controller implements the monitor channel protocol and is set when the EOM indication is received on the E bit. When this bit is set, the data byte is invalid.
Page 878 Freescale Semiconductor, Inc. Communication Processor Module AR—Abort Request This bit is only valid when a serial management controller uses the monitor channel protocol and it is set by a serial management controller when an abort request is received on the A bit. The SMCx transmitter transmits the EOM on the E bit after an abort request is received.
Page 879 Freescale Semiconductor, Inc. Communication Processor Module • C/I_TXBD—The SMCx circuit interface channel transmit (TX) buffer descriptor is used by the communication processor module to report information about the circuit interface channel transmit byte. OFFSET + 0 RESERVED C/I DATA RESERVED R—Ready...
Page 880 Freescale Semiconductor, Inc. Communication Processor Module 16.11.8.4 SMCx GCI MODE REGISTER. When a serial management controller is in GCI mode, the 16-bit, memory-mapped, read/write SMCx mode register is referred to as the SMCx GCI mode (SMCM–GCI) register. The functions of bits 8–15 are common to each SMCx protocol, but bits 0–7 vary according to the protocol selected by the SM bits.
Page 881 Freescale Semiconductor, Inc. Communication Processor Module TEN—SMCx Transmit Enable 0 = SMCx transmitter disabled. 1 = SMCx transmitter enabled. REN—SMCx Receive Enable 0 = SMCx receiver disabled. 1 = SMCx receiver enabled. 16.11.8.5 SMCx GCI EVENT REGISTER. When a serial management controller is in GCI mode, the 8-bit memory-mapped SMCx event register is referred to as the SMCx GCI event (SMCE–GCI) register.
Page 882 Freescale Semiconductor, Inc. Communication Processor Module 16.11.8.6 SMCx GCI MASK REGISTER. When a serial management controller is in GCI mode, the 8-bit, memory-mapped, read/write SMCx mask register is referred to as the SMCx GCI mask (SMCM–GCI) register. It has the same bit format as the SMCE–GCI register. If a bit in this register is a 1, the corresponding interrupt in the SMCE–GCI is enabled.
Page 883 Freescale Semiconductor, Inc. Communication Processor Module PERIPHERAL BUS RECEIVE_REG SPI MODE REG TRANSMIT_REG COUNTER SHIFT_REGISTER IN_CLK PINS INTERFACE SPI BRG BRGCLK SPISEL SPIMOSI SPICLK SPIMISO Figure 16-120. SPI Block Diagram 16.12.1 Features The following is a list of the serial peripheral interface’s main features: •...
Page 884 Freescale Semiconductor, Inc. Communication Processor Module 16.12.2 SPI Clocking and Pin Functions You can configure the serial peripheral interface as a master for the serial channel or as a slave. You can also use it in a multimaster environment. When the serial peripheral interface is a master, use the SPI baud rate generator to generate the SPI transmit and receive clocks.
Page 885 Freescale Semiconductor, Inc. Communication Processor Module 16.12.3 The SPI Transmission and Reception Process When the serial peripheral interface is in master mode, it transmits a message to the peripheral or slave, which sends back an immediate reply. When the MPC823 has more than one slave, it can use the general-purpose parallel I/O pins to selectively enable different slaves.
Page 886 Freescale Semiconductor, Inc. Communication Processor Module Transmission continues until no more data is available or the SPISEL pin is negated. If the pin is negated before all the data is transmitted, it stops, but the TX buffer descriptor stays open. Further transmission continues once the SPISEL pin is reasserted and SPICLK begins toggling.
Page 887 Freescale Semiconductor, Inc. Communication Processor Module 16.12.3.2 SPI PARAMETER RAM MEMORY MAP. The SPI parameter RAM area begins at the SPI base address and is used for the general SPI parameters. Notice that it is similar to the SCCx general-purpose parameter RAM. You must initialize certain parameter RAM values before the serial peripheral interface is enabled.
Page 888 Freescale Semiconductor, Inc. Communication Processor Module • RFCR and TFCR—The receive and transmit function code register entries contain the value that you want to appear on the AT pins when the associated SDMA channel accesses memory. This register controls the byte-ordering convention used in the transfers.
Page 889 Freescale Semiconductor, Inc. Communication Processor Module Bits 0–2—Reserved These bits are reserved and must be set to 0. BO—Byte Ordering You must set these bits to select the required byte ordering of the data buffer. If this bit field is modified on-the-fly, it takes effect at the beginning of the next frame or at the beginning of the next buffer descriptor.
Page 890 Freescale Semiconductor, Inc. Communication Processor Module • RRBPTR—The RX buffer descriptor pointer entry for each SPI channel points to the next buffer descriptor that the receiver transfers data to when it is idle or to the current buffer descriptor during frame processing. After a reset or when the end of the buffer descriptor table is reached, the communication processor module initializes this pointer to the value programmed in the RBASE entry.
Page 891 Freescale Semiconductor, Inc. Communication Processor Module 16.12.3.4 SPI BUFFER DESCRIPTOR RING. The data associated with the serial peripheral interface is stored in buffers, which are referenced by buffer descriptors organized in a buffer descriptor ring located in the dual-port RAM. This ring has the same basic configuration as the SCCx, SMCx, USB, and I C controllers.
Page 892 Freescale Semiconductor, Inc. Communication Processor Module 16.12.4 Programming the Serial Peripheral Interface 16.12.4.1 SPI MODE REGISTER. The read/write SPI mode (SPMODE) register controls both the serial peripheral interface operation mode and clock source. Table 16-2 contains more information on commands that can be used with this register.
Page 893 Freescale Semiconductor, Inc. Communication Processor Module REV—Reverse Data This bit determines the receive and transmit character bit order. 0 = Reverse data. Least-significant bit of the character transmitted and received first. 1 = Normal operation. Most-significant bit of the character transmitted and received first.
Page 894 Freescale Semiconductor, Inc. Communication Processor Module PM—Prescale Modulus Select This field specifies the divide ratio of the prescale divider in the SPI clock generator. The BRGCLK is divided by 4 * ([PM0–PM3] + 1), thus giving a clock divide ratio of 4 to 64. The clock has a 50% duty cycle.
Page 895 Freescale Semiconductor, Inc. Communication Processor Module SPICLK (CI = 0) SPICLK (CI = 1) SPIMOSI (FROM MASTER) SPIMISO (FROM SLAVE) SPISEL NOTE: Q = Undefined Signal Figure 16-122. SPI Transfer Format If CP is Set to 0 SPICLK (CI = 0)
Page 896 Freescale Semiconductor, Inc. Communication Processor Module 16.12.4.1.2 SPI Receive Buffer Descriptor. Using receive (RX) buffer descriptors, the communication processor module reports information about each buffer of received data, closes the current buffer, generates a maskable interrupt, and starts receiving data in the next buffer once the current buffer is full.
Page 897 Freescale Semiconductor, Inc. Communication Processor Module W—Wrap (Final Buffer Descriptor in Table) 0 = This is not the last buffer descriptor in the RX buffer descriptor table. 1 = This is the last buffer descriptor in the RX buffer descriptor table. After this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that RBASE points to in the table.
Page 898 Freescale Semiconductor, Inc. Communication Processor Module DATA LENGTH This field represents the number of octets that the communication processor module writes into this buffer descriptor data buffer. The communication processor module writes it once as the buffer descriptor is closed. The serial peripheral interface writes these bits after the received data is placed into the associated data buffer.
Page 899 Freescale Semiconductor, Inc. Communication Processor Module W—Wrap (Final Buffer Descriptor in Table) 0 = This is not the last buffer descriptor in the TX buffer descriptor table. 1 = This is the last buffer descriptor in the TX buffer descriptor table. After this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that TBASE points to in the table.
Page 900 Freescale Semiconductor, Inc. Communication Processor Module DATA LENGTH This field indicates the number of octets that the communication processor module must transmit from this buffer descriptor data buffer. However, it is never modified by the communication processor module. Normally, this value is greater than zero, but if the number of data bits in the character is greater than 8, then DATA LENGTH must be even.
Page 901 Freescale Semiconductor, Inc. Communication Processor Module 16.12.4.3 SPI EVENT REGISTER. The 8-bit memory-mapped SPI event (SPIE) register is used to generate interrupts and report events recognized by the serial peripheral interface. When an event is recognized, the serial peripheral interface sets the corresponding bit in this register.
Page 902 Freescale Semiconductor, Inc. Communication Processor Module 16.12.4.4 SPI MASK REGISTER. The 8-bit read/write SPI mask (SPIM) register has the same bit formats as the SPIE register. If a bit in the SPIM is 1, the corresponding interrupt in the SPIE register is enabled. If the bit is zero, the corresponding interrupt in the SPIE register is masked.
Page 903 Freescale Semiconductor, Inc. Communication Processor Module 9. Initialize the TX buffer descriptor and assume the TX data buffer is at 0x00002000 in main memory and contains five 8-bit characters. Write 0xB800 to TX_BD_Status, 0x0005 to TX_BD_Length, and 0x00002000 to TX_BD_Pointer.
Page 904 Freescale Semiconductor, Inc. Communication Processor Module 9. Write 0xFF to the SPIE register to clear any previous events. 10. Write 0x37 to the SPIM register to enable all possible serial peripheral interface interrupts. 11. Write 0x00000020 to the CIMR to allow the serial peripheral interface to generate a system interrupt.
Page 905 Freescale Semiconductor, Inc. Communication Processor Module 16.13 THE I C CONTROLLER ® The inter-integrated circuits (I ) controller enables the MPC823 to exchange data with a number of other I C devices, such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCD displays. The I C controller is a synchronous, multimaster bus that is used to connect several integrated circuits on a board.
Page 906 Freescale Semiconductor, Inc. Communication Processor Module 16.13.1 Features The following is a list of the I C controller’s main features: • Two-Pin Interface • Full-Duplex Operation • Master or Slave I C Mode Support • MultiMaster Environment Support • Continuous Transfer Mode for Autoscanning Peripherals •...
Page 907 Freescale Semiconductor, Inc. Communication Processor Module STOP CONDITION START CONDITION DATA BYTE Figure 16-125. I C Timing 16.13.3 I C Controller Transmission and Reception Process 16.13.3.1 I C MASTER MODE. When the I C controller is in master mode, it initiates a transaction by transmitting a message specifying a read or write operation to the I C slave.
Page 908 Freescale Semiconductor, Inc. Communication Processor Module 16.13.3.1.1 Master Write. To begin a write operation to a slave device that contains internal addresses, you must prepare a TX data buffer that is N+2 bytes in length. The first byte contains the 7-bit device address followed by the write bit asserted (R/W = 0). The second byte contains the internal base address of the write.
Page 909 Freescale Semiconductor, Inc. Communication Processor Module 16.13.3.1.2 Master Read. To begin a read operation to a slave device that contains internal addresses, you must prepare two TX buffers. TX buffer 0 must be 2 bytes long and TX buffer 1 must be N+1 bytes long, where N is the number of bytes to be read sequentially from the slave device.
Page 910 Freescale Semiconductor, Inc. Communication Processor Module When communicating to either slave device, set the R bit in the TX buffer descriptor to prepare it for transmission. Set the I bit in the TX and RX buffer descriptors to enable the transmission and reception status to be updated in the I2CE register and to enable I interrupts to the core.
Page 911 Freescale Semiconductor, Inc. Communication Processor Module 16.13.3.2.1 Write to Master. If an external master requests a write operation, the I controller acknowledges the received data and writes it into a receive buffer using the next available RX buffer descriptor until the next start or stop condition is detected.
Page 912 Freescale Semiconductor, Inc. Communication Processor Module 16.13.4 I C Parameter RAM Memory Map The I C controller parameter RAM area begins at the I C base address, which is used for the general I C parameters. It is similar to the SCCx general-purpose parameter RAM. You must initialize certain parameter RAM values before the serial peripheral interface is enabled.
Page 913 Freescale Semiconductor, Inc. Communication Processor Module • RFCR and TFCR—The RX and TX function code entries contain the value that you want to appear on the AT pins when the associated SDMA channel accesses memory. This register controls the byte-ordering convention used in the transfers.
Page 914 Freescale Semiconductor, Inc. Communication Processor Module Bits 0–2—Reserved These bits are reserved and must be set to 0. BO—Byte Ordering You must set this bit to select the required byte ordering of the data buffer. 00 = The DEC/Intel convention is used for byte ordering (swapped operation) and is also called little-endian byte ordering.
Page 915 Freescale Semiconductor, Inc. Communication Processor Module • RBPTR—The receive buffer pointer entry for each I C channel points to the next buffer descriptor that the receiver transfers data to when it is idle or to the current buffer descriptor during frame processing. After a reset or when the end of the buffer descriptor table is reached, the communication processor module initializes this pointer to the value programmed in the RBASE entry.
Page 916 Freescale Semiconductor, Inc. Communication Processor Module 16.13.6 The I C Buffer Descriptor Ring The data associated with the I C controller is stored in buffers, which are referenced by buffer descriptors organized in a buffer descriptor ring located in the dual-port RAM. This ring has the same basic configuration as the serial communication and serial management controllers.
Page 917 Freescale Semiconductor, Inc. Communication Processor Module 16.13.7 Programming the I C Controller 16.13.7.1 I C MODE REGISTER. The read/write I C mode (I2MOD) register controls both the I C operation mode and clock source. I2MOD FIELD RESERVED REVD PDIV RESET ADDR (IMMR &...
Page 918 Freescale Semiconductor, Inc. Communication Processor Module EN—Enable I This bit enables I C operation. When EN is cleared, the I C controller is in a reset state and consumes minimal power. 0 = I C controller is disabled. 1 = I C controller is enabled.
Page 919 Freescale Semiconductor, Inc. Communication Processor Module E—Empty 0 = The data buffer associated with this RX buffer descriptor is filled with received data or data reception is aborted due to an error condition. The core is free to examine or write to any fields of this RX buffer descriptor. The communication processor module does not use this buffer descriptor as long as the E bit is zero.
Page 920 Freescale Semiconductor, Inc. Communication Processor Module DATA LENGTH This field represents the number of octets that the communication processor module writes into this buffer descriptor data buffer. The communication processor module writes it once the buffer descriptor closes. The I C controller writes these bits after the received data is placed into the associated data buffer.
Page 921 Freescale Semiconductor, Inc. Communication Processor Module W—Wrap (Final Buffer Descriptor in Table) 0 = This is not the last buffer descriptor in the TX buffer descriptor table. 1 = This is the last buffer descriptor in the TX buffer descriptor table. After this buffer is used, the communication processor module receives incoming data into the first buffer descriptor that TBASE points to in the table.
Page 922 Freescale Semiconductor, Inc. Communication Processor Module DATA LENGTH This field represents the number of octets the communication processor module must transmit from this buffer descriptor data buffer. However, it is never modified by the communication processor module. Normally, this value must be greater than zero. The I controller writes these bits after it finishes transmitting the associated data buffer.
Page 923 Freescale Semiconductor, Inc. Communication Processor Module 16.13.7.5 I C BAUD RATE GENERATOR REGISTER. The 8-bit, memory mapped, read/write I C baud rate generator (I2BRG) register sets the divide ratio of the baud rate generator. This register is set to all ones at hard reset.
Page 924 Freescale Semiconductor, Inc. Communication Processor Module Bits 1–6—Reserved. These bits are reserved and must be set to 0. M/S—Master/Slave This bit configures the I C controller to operate as a master or a slave. 0 = I C controller is a slave.
Page 925 Freescale Semiconductor, Inc. Communication Processor Module 16.13.7.8 I C MASK REGISTER. The 8-bit read/write I C mask register (I2CMR) has the same bit formats as the I2CER. If a bit in the I2CMR is 1, the corresponding interrupt in the I2CER is enabled.
Page 926 Freescale Semiconductor, Inc. Communication Processor Module 11. Initialize the RX buffer descriptor. Assume the RX data buffer is at 0x00001000 in main memory. Write 0xB000 to RX_BD_Status, 0x0 to RX_BD_Length (optional), and 0x00001000 to RX_BD_Pointer. 12. Initialize the TX buffer descriptors. Assume the TX data buffer 0 is at 0x00004000 in main memory.
Page 927 Freescale Semiconductor, Inc. Communication Processor Module 16.14.1 Features The following is a list of the parallel I/O port’s main features: • Port A is 12 Bits • Port B is 16 Bits • Port C is 12 Bits • Port D is 13 Bits •...
Page 928 Freescale Semiconductor, Inc. Communication Processor Module Table 16-41 contains the default description of all port A pin options. Table 16-41. Port A Pin Assignment PIN FUNCTION SIGNAL PAPAR = 0 PAPAR = 1 PERIPHERALS PADIR = 0 PADIR = 1...
Page 929 Freescale Semiconductor, Inc. Communication Processor Module 16.14.3 The Port A Registers Port A has four 16-bit, memory-mapped, read/write control registers. 16.14.3.1 PORT A OPEN-DRAIN REGISTER. The port A open-drain register (PAODR) indicates when the port pins are configured in a normal or wired-OR configuration. Three of the PAODR bits can be open-drain to correspond to those pins that have serial channel output capability.
Page 930 Freescale Semiconductor, Inc. Communication Processor Module 16.14.3.3 PORT A DATA DIRECTION REGISTER. The port A data direction (PADIR) register is cleared by system reset. PADIR FIELD RESERVED DR9 DR10 DR11 DR12 DR13 DR14 DR15 RESET ADDR (IMMR & 0xFFFF0000) + 0x950 Bits 0–3—Reserved...
Page 931 Freescale Semiconductor, Inc. Communication Processor Module 16.14.4 Port A Example Configurations The port A pins can be configured in many ways. PA15 can be configured as a general-purpose I/O pin, but not an open-drain pin. It can also be the USBRXD pin for the USB.
Page 932 Freescale Semiconductor, Inc. Communication Processor Module OPEN DRAIN CNTL PADAT BIT 14 USBTXD/PA14 OUTPUT LATCH 16 BITS PADIR USBOE 16 BITS PAODR 16 BITS PAPAR Figure 16-132. Parallel Block Diagram For PA14 PA7 can be configured as a general-purpose I/O pin, but not an open-drain pin. If the corresponding PADIR bit is a zero, it can also be the CLK1 pin, the TIN1 pin, the L1RCLKA pin, or all three at once.
Page 933 Freescale Semiconductor, Inc. Communication Processor Module 16.14.5 Port B Pin Functionality All port B pins can be open-drain and are independently configured as general-purpose I/O pins if the corresponding bit in the PBPAR is cleared. They are configured as dedicated on-chip peripheral pins if the corresponding PBPAR bit is set.
Page 934 Freescale Semiconductor, Inc. Communication Processor Module 16.14.6 The Port B Registers Port B has four memory-mapped, read-write control registers. 16.14.6.1 PORT B OPEN-DRAIN REGISTER. The 16-bit port B open drain register (PBODR) indicates when the port pins are configured in a a normal or wired-OR configuration.
Page 935 Freescale Semiconductor, Inc. Communication Processor Module 16.14.6.2 PORT B DATA REGISTER. A read of the port B data register (PBDAT) returns the data to the pin, regardless of whether the pin is defined as an input or output. This allows output conflicts to be found on the pin by comparing the written data with the data on the pin.
Page 936 Freescale Semiconductor, Inc. Communication Processor Module 16.14.6.3 PORT B DATA DIRECTION REGISTER. The port B data direction register (PBDIR) is cleared at system reset. PBDIR FIELD RESERVED RESET ADDR (IMMR & 0xFFFF0000) + 0x FIELD DR16 DR17 DR18 DR19 DR20 DR21 DR22 DR23 DR24 DR25 DR26 DR27 DR28 DR29 DR30 DR31...
Page 937 Freescale Semiconductor, Inc. Communication Processor Module 16.14.6.4 PORT B PIN ASSIGNMENT REGISTER. The port B pin assignment register (PBPAR) is cleared by system reset. PBPAR FIELD RESERVED RESET (IMMR & 0xFFFF0000) + 0x ADDR FIELD DD16 DD17 DD18 DD19 DD20 DD21 DD22 DD23 DD24 DD25 DD26 DD27 DD28 DD29 DD30 DD31...
Page 938 Freescale Semiconductor, Inc. Communication Processor Module 16.14.7 Port B Configuration Example You can configure the PB31 pin as a general-purpose I/O or open-drain pin. It can also be the LCD_A pin for the LCD controller or the SPI select input SPISEL pin. If PB31 is not...
Page 939 Freescale Semiconductor, Inc. Communication Processor Module When the pin is configured as an output, port C interrupts cannot be generated. To configure a port C pin as a general-purpose output pin, follow these steps: 1. Write the corresponding PCPAR bit with a zero.
Page 940 Freescale Semiconductor, Inc. Communication Processor Module The port C lines associated with the CDx and CTSx pins have a mode of operation in which the pin can be internally connected to the corresponding serial communication controller, but can also generate interrupts. Port C still detects changes on the CTSx and CDx pins and asserts the corresponding interrupt request, but the serial communication controller simultaneously uses the CTSx and/or CDx pin to automatically control operation.
Page 941 Freescale Semiconductor, Inc. Communication Processor Module 16.14.9.1 PORT C DATA REGISTER. A read of the port C data register (PCDAT) returns the data to the pin, regardless of whether the pin is defined as an input or output. This allows output conflicts to be found on the pin by comparing the written data with the data on the pin.
Page 942 Freescale Semiconductor, Inc. Communication Processor Module 16.14.9.3 PORT C PIN ASSIGNMENT REGISTER. The port C pin assignment register (PCPAR) is a 16-bit register that is cleared by system reset. PCPAR FIELD RESERVED DD9 DD10 DD11 DD12 DD13 DD14 DD15 RESET ADDR (IMMR &...
Page 943 Freescale Semiconductor, Inc. Communication Processor Module CTSx—Clear To Send 2 and 3 0 = PCx is a general-purpose interrupt I/O pin. The SCCx internal CTSx signal is always asserted. If PCDIR configures this pin as an input, the pin can generate an interrupt to the core, as controlled by the PCINT bits.
Page 944 Freescale Semiconductor, Inc. Communication Processor Module 16.14.9.5 PORT C INTERRUPT CONTROL REGISTER. The 16-bit read/write port C interrupt control (PCINT) register indicates how changes on the pin cause interrupts when they are generated with that pin. The PCINT is cleared by reset.
Page 945 Freescale Semiconductor, Inc. Communication Processor Module 16.14.10 Port D Pin Functionality The 13 port D pins are independently configured as general-purpose I/O pins if the corresponding port D pin assignment register (PDPAR) is cleared. They are configured as dedicated on-chip peripheral pins if the corresponding PDPAR bit is set.
Page 946 Freescale Semiconductor, Inc. Communication Processor Module 16.14.11 Port D Registers Port D has three 16-bit, memory-mapped, read/write control registers. 16.14.11.1 PORT D DATA REGISTER. A read of the port D data (PDDAT) register returns the data on the pins, regardless of whether the pins are an input or an output. This allows output conflicts to be found on the pins by comparing the written data with the data on the pins.
Page 947 Freescale Semiconductor, Inc. Communication Processor Module 16.14.11.3 PORT D PIN ASSIGNMENT REGISTER. The port D pin assignment register (PDPAR) is cleared at system reset. PDPAR FIELD RESERVED DD9 DD10 DD11 DD12 DD13 DD14 DD15 RESET ADDR (IMMR & 0xFFFF0000) + 0x972 Bits 0–2—Reserved...
Page 948 Freescale Semiconductor, Inc. Communication Processor Module IREQ[0:7] IRQ0 EDGE/ LEVEL LEVEL 7 LEVEL 6 POWERPC LEVEL5 CORE LEVEL 4 IREQ LEVEL 3 PCMCIA LEVEL 2 LEVEL 1 LEVEL 0 DEBUG DEBUG SYSTEM INTERFACE UNIT PORT C[4:15] TIMER1 TIMER2 TIMER3 TIMER4...
Page 949 Freescale Semiconductor, Inc. Communication Processor Module Within the CPM interrupt level, the sources are assigned a priority structure. On the MPC823, you have some flexibility with the relative priority of the interrupt sources. Once an unmasked interrupt source is pending in the CIPR, the CPM interrupt controller sends an interrupt request to the U-Bus at level 0, 1, 2, 3, 4, 5, 6, or 7.
Page 950 Freescale Semiconductor, Inc. Communication Processor Module 16.15.2.1 USB AND SCCx RELATIVE PRIORITY. The relative priority between the USB and SCCs is programmable and can be dynamically changed. In Table 16-45 there is no entry for the USB and SCCs, but rather there are entries for SCCa, SCCb, SCCc, and SCCd because each one of them can be mapped to any of these locations.
Page 951 Freescale Semiconductor, Inc. Communication Processor Module Table 16-45. Prioritization of CPM Interrupt Sources NUMBER PRIORITY LEVEL INTERRUPT SOURCE MULTIPLE EVENTS DESCRIPTION Highest Parallel I/O–PC15 SCCa (Grouped and Spread) SCCb (Grouped) SCCc (Grouped) SCCd (Grouped) Parallel I/O–PC14 Timer 1 Parallel I/O–PC13 Parallel I/O–PC12...
Page 952 Freescale Semiconductor, Inc. Communication Processor Module 16.15.2.3 NESTED INTERRUPTS. The CPM interrupt controller supports a fully nested interrupt environment that allows a high priority interrupt from another CPM source to suspend a lower priority interrupt service routine. This nesting is achieved by the CPM interrupt in-service register (CISR).
Page 953 Freescale Semiconductor, Inc. Communication Processor Module SCCE CIPR EVENT REQUEST TO THE IMB 13 INPUT AT THE LEVEL (13 EVENT BITS) SPECIFIED 28 INPUT IN IRL2–IRL0 IN THE CICR. (28 CIPR BITS) SCCM CIMR MASK MASK Figure 16-134. Interrupt Request Masking 16.15.4 Generating and Calculating an Interrupt Vector...
Page 954 Freescale Semiconductor, Inc. Communication Processor Module Table 16-46. Encoding the Interrupt Vector INTERRUPT INTERRUPT SOURCE INTERRUPT VECTOR NUMBER DESCRIPTION Parallel I/O—PC15 11111 11110 SCC2 11101 SCC3 11100 Reserved 11011 Parallel I/O—PC14 11010 Timer 1 11001 Parallel I/O—PC13 11000 Parallel I/O—PC12...
Page 955 Freescale Semiconductor, Inc. Communication Processor Module The interrupt vector table is the same as the CPM interrupt priority table, except for two differences. First, the USB and SCCx vectors are fixed. They are not affected by the USB and SCCx group mode, spread mode, or the relative priority order of the USB and SCCs.
Page 956 Freescale Semiconductor, Inc. Communication Processor Module SCCP—SCCc Priority Order This field defines whether the USB or SCCs will assert a request in the SCCc priority position. 00 = USB will assert its request in the SCCc position. 01 = SCC2 will assert its request in the SCCc position.
Page 957 Freescale Semiconductor, Inc. Communication Processor Module IEN—Interrupt Enable This bit is a master enable for the CPM interrupts. 0 = CPM interrupts are disabled. 1 = CPM interrupts are enabled. SPS—Spread Priority Scheme This bit selects the relative USB and SCCx priority scheme and cannot be changed dynamically.
Page 958 Freescale Semiconductor, Inc. Communication Processor Module In a polled interrupt scheme, you must periodically read the CIPR. When a pending interrupt is handled, clear the corresponding bit in the CIPR. However, if an event register exists, clear the unmasked event register bits instead, thus causing the CIPR bit to be cleared. To clear a bit in the CIPR, write a 1 to that bit.
Page 959 Freescale Semiconductor, Inc. Communication Processor Module Note: The USB or SCCx CIMR bit positions are unaffected by the relative priority between the USB or SCCs. To clear bits that were set by multiple interrupt events, you must clear all the unmasked events in the corresponding event register. If a...
Page 960 Freescale Semiconductor, Inc. Communication Processor Module Note: The USB or SCCx CISR bit positions are not affected by the relative priority between the USB or SCCs. If the error vector is taken, no bit in the CISR is set. All undefined bits in the CISR return zeros when read. You can control the extent to which CPM interrupts can interrupt other CPM interrupts by selectively clearing the CISR.
Page 961 Freescale Semiconductor, Inc. Communication Processor Module 16.15.6.2 USB INTERRUPT HANDLER EXAMPLE. In this example, the USB bit in the CIPR remains set as long as one or more unmasked event bits remain in the USBE register. This is an example of a handler for an interrupt source with multiple events. Notice that the USB bit in the CIPR does not need to be cleared by the handler, but the USB bit in the CISR does.
Page 962 Freescale Semiconductor, Inc. SECTION 17 PCMCIA INTERFACE The PCMCIA host adapter module provides all control logic for a PCMCIA interface. Only the analog power switching logic and buffering needs to be provided externally. The PCMCIA host supports one PCMCIA socket.
Page 963 Freescale Semiconductor, Inc. PCMCIA Interface SOCKET POWER ON INDICATION VCC_B MAX 780A VPP1_B OR EQUIV. VPP2_B D[8:15] DATA_B[15:8] D[0:7] DATA_B[7:0] TRANSCEIVER BUFFER WITH OE CE1_B CE1_B PCMCIA CE2_B CE2_B HOST ADAPTER MODULE WE/PGM WE/PGM_B OE_B (IORD),(IOWR) (IORD_B),(IOWR_B) RESET_B BUFFER WITH OE...
Page 964 Freescale Semiconductor, Inc. PCMCIA Interface 17.3 PCMCIA SIGNALS The PCMCIA module consists of the cycle control, input port, output port, and various other signals. 17.3.1 The PCMCIA Cycle Control Signals The following signals are used for I/O accesses to the PCMCIA card: •...
Page 965 Freescale Semiconductor, Inc. PCMCIA Interface • Data Bus (D[0:15])—Bidirectional. Signals D0 through D15 constitute the bidirectional data bus. The most-significant bit is D0. Significance decreases downward to D15. • Extend Bus Cycle (WAIT_B)—Input. This signal is asserted by the PC card to delay completion of the pending memory or I/O cycle.
Page 966 Freescale Semiconductor, Inc. PCMCIA Interface 17.3.2 The PCMCIA Input Port Signals The MPC823 provides synchronization, transition detection, optional interrupt generation and a means for the software to read the signal state. This function is not necessarily specific to PCMCIA and the signals can be used as a general-purpose input port with edge detection and interrupt capability.
Page 967 Freescale Semiconductor, Inc. PCMCIA Interface • Speaker (SPKR)—Input. When the card and its socket are programmed for I/O interface operation, the BVD2_B signal is used as SPKR and it is generated by the I/O PC cards. The SPKR signal must be used to provide the socket’s single amplitude (digital) audio waveform to the system.
Page 968 Freescale Semiconductor, Inc. PCMCIA Interface 17.4 PCMCIA OPERATION 17.4.1 Memory-Only Cards Table 17-2 shows a worst case example of host programming. Table 17-2. Host Programming for Memory Cards MEMORY 600NS 200NS 150NS 100NS ACCESS TIME CYCLE 20ns 30ns 40ns 62ns...
Page 969 Freescale Semiconductor, Inc. PCMCIA Interface 17.4.3 Interrupts Each input from the PCMCIA card to the host (BVD, CD, RDY and VS) is sampled in the PCMCIA interface input pins register (PIPR) and any change to these bits is reported in the PCMCIA interface status change register (PSCR).
Page 970 Freescale Semiconductor, Inc. PCMCIA Interface IOIS16_B SPKR CBDREQ1 DREQ2 CBDREQ2 PORT C MULTIPLEXER LOGIC PORT C DREQ2 INTERNAL DMA REQUEST Figure 17-2. Internal DMA Request Logic 17.5 PROGRAMMING THE PCMCIA INTERFACE The following section describes the PCMCIA interface programming model. All registers are memory-mapped within the internal control register area.
Page 971 Freescale Semiconductor, Inc. PCMCIA Interface CBVS1—Card B Voltage Sense 1 0 = Card B cannot operate at 3.3V. 1 = Card B can operate at 3.3V. CBVS2—Card B Voltage Sense 2 This bit is reserved by the PCMCIA controller for a secondary operating voltage. It must normally be set to 1 by Card B.
Page 972 Freescale Semiconductor, Inc. PCMCIA Interface If Card B and its socket are configured for I/O interface operation or if the card’s power supply circuitry is using the IRQ signal, CBRDY is: 0 = Card B is requesting an interrupt. 1 = Card B is not requesting an interrupt.
Page 973 Freescale Semiconductor, Inc. PCMCIA Interface CBWP_C—Card B Write-Protect Change 0 = Signal is changed. 1 = Signal is unchanged. CBCD2_C—Card B Card Detect 2 Change 0 = Signal is changed. 1 = Signal is unchanged. CBCD1_C—Card B Card Detect 1 Change 0 = Signal is changed.
Page 974 Freescale Semiconductor, Inc. PCMCIA Interface 17.5.3 PCMCIA Interface Enable Register The PCMCIA interface enable register (PER) acts as a mask for the various sources of a PCMCIA interrupt. Interrupts caused by bits 16-22 are reported as CBSCHLVL interrupts, while interrupts caused by bits 24-27 are reported as CBIRQLVL interrupts.
Page 975 Freescale Semiconductor, Inc. PCMCIA Interface CB_EBVD2—Card B Enable for Battery Voltage/SPKR 0 = Disable interrupt on any change in the relevant pin. 1 = Enable interrupt on changes in the relevant pin. CB_EBVD1—Card B Enable for Battery Voltage/STSCHG 0 = Disable interrupt on any change in the relevant pin.
Page 976 Freescale Semiconductor, Inc. PCMCIA Interface 17.5.4 PCMCIA Interface General Control Register B The PCMCIA interface general control register B (PGCRB) provides control for the IREQ and STSCHG interrupt levels, This register also controls the PCMCIA output port signals. When the PCMCIA controller is not operating, the CBOE and CBRESET bits can be used to access the OP[2:3] pins as general-purpose output pins without configuring any other PCMCIA register.
Page 977 Freescale Semiconductor, Inc. PCMCIA Interface CBOE—Card B Output Enable The value of this bit is always reflected on the OP2 pin. When the PCMCIA controller is in active mode, POE_B is connected to the OP2 pin. POE_B is used to three-state the address and strobe pins addressing the PCMCIA card slot.
Page 978 Freescale Semiconductor, Inc. PCMCIA Interface This field is compared to the address on the address bus to determine if a PCMCIA window is being accessed by an internal bus master. These bits are used in conjunction with the BSIZE field in the POR.
Page 979 Freescale Semiconductor, Inc. PCMCIA Interface 00101 = 64 bytes. 00100 = 128 bytes. 01100 = 256 bytes. 01101 = 512 bytes. 01111 = 1K. 01110 = 2K. 01010 = 4K. 01011 = 8K. 01001 = 16K. 01000 = 32K. 11000 = 64K.
Page 980 Freescale Semiconductor, Inc. PCMCIA Interface PSHT—PCMCIA Strobe Hold Time This attribute is used to determine when IOWR_B or WE_B are negated during a PCMCIA write access or when IORD_B or OE_B are negated during a PCMCIA read access handled by the PCMCIA interface. This helps meet address/data hold time requirements for slow memories and peripherals.
Page 981 Freescale Semiconductor, Inc. PCMCIA Interface PSL—PCMCIA Strobe Length This attribute determines the number of cycles the strobe will be asserted during a PCMCIA access for this window. It is the main parameter for determining the length of the cycle. The cycle may be lengthened by asserting the WAIT signal.
Page 982 Freescale Semiconductor, Inc. PCMCIA Interface PRS—PCMCIA Region Select 000 = Common memory space. 001 = Reserved. 010 = Attribute memory space. 011 = I/O space. 100 = DMA (normal DMA transfer. 101 = DMA last transaction. 110 = Drive the value of the A22 and A23 signals on CE2 and CE1.
Page 983 Freescale Semiconductor, Inc. PCMCIA Interface 17.6 PCMCIA CONTROLLER TIMING EXAMPLES CLKOUT A[0:31] RD/WR BURST CE[1:2] ALE_B PCOE WAIT_B DATA PSST PSHT Figure 17-3. PCMCIA Single Beat Read Cycle (PRS = 0, PSST = 1, PSL = 3, PSHT = 1)
Page 984 Freescale Semiconductor, Inc. PCMCIA Interface CLKOUT A[0:31] RD/WR BURST CE[1:2] ALE_B PCOE WAIT_B DATA PSST PSHT Figure 17-4. PCMCIA Single Beat Read Cycle (PRS = 0, PSST = 2, PSL = 4, PSHT = 1) MPC823 REFERENCE MANUAL 17-23 For More Information On This Product,...
Page 985 Freescale Semiconductor, Inc. PCMCIA Interface CLKOUT A[0:31] RD/WR BURST CE[1:2] ALE_B PCOE WAIT_B DATA PSST PSHT Figure 17-5. PCMCIA Single Beat Read Cycle (PRS = 0, PSST = 1, PSL = 3, PSHT = 0) MPC823 REFERENCE MANUAL MOTOROLA For More Information On This Product,...
Page 986 Freescale Semiconductor, Inc. PCMCIA Interface CLKOUT A[0:31] RD/WR BURST CE[1:2] ALE_B PCWE WAIT_B DATA PSST PSHT Figure 17-6. PCMCIA Single Beat Write Cycle (PRS = 2, PSST = 1, PSL = 3, PSHT = 1) MPC823 REFERENCE MANUAL 17-25 For More Information On This Product,...
Page 987 Freescale Semiconductor, Inc. PCMCIA Interface CLKOUT A[0:31] RD/WR BURST CE[1:2] ALE_B IOWR_B WAIT_B DATA IOIS16_B PSST PSHT Figure 17-7. PCMCIA Single Beat Write Cycle (PRS = 3, PSST = 1, PSL = 4, PSHT = 3) MPC823 REFERENCE MANUAL MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 988 Freescale Semiconductor, Inc. PCMCIA Interface CLKOUT A[0:31] RD/WR BURST CE[1:2] ALE_B IOWR_B WAIT_B DATA PSST WAIT DELAY PSHT Figure 17-8. PCMCIA Single Beat Write with Wait (PRS = 3, PSST = 1, PSL = 3, PSHT = 0) MPC823 REFERENCE MANUAL...
Page 989 Freescale Semiconductor, Inc. PCMCIA Interface CLKOUT A[0:31] RD/WR BURST CE[1:2] ALE_B IORD_B WAIT_B DATA PSST WAIT DELAY PSHT Figure 17-9. PCMCIA Single Beat Read with Wait (PRS = 3, PSST = 1, PSL = 3, PSHT = 1) MPC823 REFERENCE MANUAL...
Page 990 Freescale Semiconductor, Inc. PCMCIA Interface CLKOUT A[0:31] RD/WR BURST ALE_B IOWR DATA IOIS16_B PSHT PSST Figure 17-10. PCMCIA I/O Read of a 16-Bit Slave Port (PPS = 1, PRS = 3, PSST = 1, PSL = 2, PSHT = 0)
Page 991 Freescale Semiconductor, Inc. PCMCIA Interface CLKOUT A[0:31] RD/WR BURST ALE_B IOWR DATA IOSI16_B PSST PSHT PSST PSHT Figure 17-11. PCMCIA I/O Read of an 8-Bit Slave Port (PPS = 1, PRS = 3, PSST = 1, PSL = 2, PSHT = 0...
Page 992 Freescale Semiconductor, Inc. PCMCIA Interface CLKOUT A[0:31] AT=0XF AT=0XF RD/WR BURST CE[1:2] ALE_B IORD PCOE SIZE SIZE=WORD SIZE=HALF DATA PSST PSHT PSST PSHT Figure 17-12. PCMCIA DMA Read Cycle (PRS = 4, PSST = 1, PSL = 3, PSHT = 0)
Page 993 Freescale Semiconductor, Inc. SECTION 18 LCD CONTROLLER The MPC823 contains an on-chip LCD controller that can be used to drive an LCD panel display. The integrated LCD controller shortens access time, reduces power consumption, and saves system board space by not using external glue logic. The LCD controller can interface with a variety of passive, active, dual-scan, single-scan, and smart LCD panels.
Page 994 Freescale Semiconductor, Inc. LCD Controller 18.1.1 LCD Technology A liquid crystal display (LCD) implements a low-power display technology that uses ambient light to display images. LCDs consist of two pieces of glass with electrodes printed on the inside and polarizers are used on the external front and rear surfaces. When the LCD is off, no voltage is applied to the electrodes and light passes through the LCD.
Page 995 Freescale Semiconductor, Inc. LCD Controller The time it takes to refresh a row is called the duty cycle. In a simple refresh policy, one row is refreshed at a time. However, this creates large voltage spikes on the LCD electrodes.
Page 996 Freescale Semiconductor, Inc. LCD Controller 18.1.2.1 PASSIVE LCD INTERFACE. A passive LCD panel interface uses X and Y shift registers to operate. The X shift register is used to display a column and the Y shift register is used to display a row. The LCD controller fills the shift register, provides framing, and reverses the display polarity from frame-to-frame or line-to-line.
Page 997 Freescale Semiconductor, Inc. LCD Controller 18.1.2.3 SMART PANEL LCD INTERFACE. In a smart panel interface, the whole memory display buffer resides on the panel, which is directly connected to the system bus. Also, the CPU accesses the display memory directly, so you do not need a controller.
Page 998 Freescale Semiconductor, Inc. LCD Controller generation and a data path to the panel. The LCD controller block diagram is illustrated in Figure 18-6. TIMING GENERATION REGISTERS DMA ADDRESS MODES CONTROL FRAME SHIFT LOAD LCD_AC INTERFACE COLOR FIFOS LCD DATA Figure 18-6. LCD Controller Block Diagram...
Page 999 Freescale Semiconductor, Inc. LCD Controller 18.3 LCD CONTROLLER OPERATION The LCD controller uses the system interface unit to communicate with the core and external system. It has its own DMA functionality to fetch display memory into the FIFOs for pixel generation.
Page 1000 Freescale Semiconductor, Inc. LCD Controller After reset, the LCD controller is disabled (PON=0) in the LCD configuration and control register (LCCR). To operate the LCD controller, you must program the LCD registers and set the PON bit. When enabled, the FIFOs ask the DMA controller to fill them using burst read memory cycles.

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