Usb Interrupt Mask Register; Table 28-12 Usb Interrupt Mask Register Description - Motorola DragonBall MC9328MX1 Reference Manual

28.3.8 USB Interrupt Mask Register

The USB Interrupt Mask Register is used to mask the corresponding interrupt in the USB_INTR register.
USB_MASK
BIT 31 30 29
WAKEUP
TYPE rw r
1 0
RESET
BIT 15 14 13
TYPE r r
0 0
RESET
Table 28-12. USB Interrupt Mask Register Description
Name
WAKEUP Wake-Up Mask—Enables/Disables the WAKEUP
Bit 31 interrupt.
Reserved Reserved—These bits are reserved and should read 0.
Bits 30–8
MSOF Missed Start-of-Frame Mask—Enables/Disables the
Bit 7 MSOF interrupt.
SOF Start-of-Frame Mask—Enables/Disables the SOF
Bit 6 interrupt.
RESET_STOP Reset Signaling Stop Mask—Enables/Disables the
Bit 5 RESET_STOP interrupt.
RESET_START Reset Signaling Start Mask—Enables/Disables the
Bit 4 RESET_START interrupt.
RES Suspend to Resume Mask—Enables/Disables the RES
Bit 3 interrupt.
SUSP Suspend Mask—Enables/Disables the SUSP interrupt.
Bit 2
FRAME_MATCH Frame Match Mask—Enables/Disables the
Bit 1 FRAME_MATCH interrupt.
CFG_CHG Configuration Change Mask—Enables/Disables the
Bit 0 CFG_CHG interrupt.
MOTOROLA
USB Interrupt Mask Register
28 27 26 25 24
r r r r r r
0 0 0 0 0 0
12 11 10 9 8
r r r r r r
0 0 0 0 0 0
Description
USB Device Port
23 22 21 20
r r r
0 0 0
0x8000
7 6 5
RESET_ RESET_
MSOF SOF
STOP START
rw rw rw rw
1 1 1
0x00FF
Programming Model
0x0021201C
19 18 17
r r r r
0 0 0 0
4 3 2 1
FRAME_
RES SUSP
MATCH
rw rw rw
1 1 1 1
Settings
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
Addr
16
r
0
0
CFG_
CHG
rw
1
28-17