Table of Contents
Advertisement
Chapter 24
SDRAM Memory Controller
This chapter describes the SDRAM controller (SDRAMC) on the MC9328MX1.
24.1 Features
The SDRAM Controller includes these distinctive features:
•
Supports 4 banks of 64-, 128-, or 256-Mbit synchronous DRAMs
•
Includes 2 independent chip-selects
— Up to 64 Mbyte per chip-select
— Up to four banks simultaneously active per chip-select
— JEDEC standard pinout and operation
•
Supports Micron SyncFlash® SDRAM-interface burst flash memory
— Boot capability from CSD1
•
Supports burst reads of word (32-bit) data types
•
PC100 compliant interface
— 100 MHz system clock achievable with "-8" option PC100 compliant memories
— single and fixed-length (8-word) word access
— Typical access time of 8-1-1-1 at 100 MHz
•
Software configurable bus width, row and column sizes, and delays for differing system
requirements
•
Built in auto-refresh timer and state machine
•
Hardware supported self-refresh entry and exit which keeps data valid during system reset and
low-power modes
•
Auto-powerdown (clock suspend) timer
MOTOROLA
SDRAM Memory Controller
24-1
Advertisement
Chapters
Table of Contents
