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Phase-Locked Loop and Clock Controller
12.5.4.1 System PLL Control Register 0
The System PLL Control Register 0 (SPCTL0) is a 32-bit register that controls the operation of the System
PLL. The SPCTL0 control bits are described in the following sections. A delay of 30 System PLLCLK
cycles is required between two write accesses to SPCTL0 register. The following is a procedure for
changing the System PLL settings:
1. Program the desired values of PD, MFD, MFI, and MFN into the SPCTL0.
2. Set the SPLL_RESTART bit in the CSCR (it will self-clear).
3. New PLL settings will take place.
SPCTL0
BIT
31
30
29
TYPE
r
r
rw
0
0
0
RESET
BIT
15
14
13
TYPE
r
r
rw
0
0
0
RESET
Table 12-12. System PLL Control Register 0 Description
Name
Reserved
Reserved—These bits are reserved and should read 0.
Bits 31–30
PD
Predivider Factor—Defines the predivider factor (PD) that is applied to the
Bits 29–26
PLL input frequency. PD is an integer between 0 and 15 (inclusive). The
System PLL oscillates at a frequency determined by Equation 12-1. The PD is
chosen to ensure that the resulting VCO output frequency remains within the
specified range. When a new value is written into the PD bits, the PLL loses its
lock: after a time delay, the PLL re-locks.
MFD
Multiplication Factor (Denominator Part)—Defines the denominator part of
Bits 25–16
the BRM value for the MF. When a new value is written into the MFD9–MFD0
bits, the PLL loses its lock: after a time delay, the PLL re-locks.
Reserved
Reserved—These bits are reserved and should read 0.
Bits 15–14
12-12
System PLL Control Register 0
28
27
26
25
PD
rw
rw
rw
rw
0
0
1
0
12
11
10
9
MFI
rw
rw
rw
rw
1
0
1
0
Description
MC9328MX1 Reference Manual
24
23
22
21
20
MFD
rw
rw
rw
rw
rw
0
0
0
1
1
0x043F
8
7
6
5
4
MFN
rw
rw
rw
rw
rw
0
0
0
1
1
0x1437
Addr
0x0021B00C
19
18
17
16
rw
rw
rw
rw
1
1
1
1
3
2
1
0
rw
rw
rw
rw
0
1
1
1
Settings
0000 = 0
0001 = 1
...
1111 = 15
0x000 = Reserved
0x001 = 1
...
0x3FF = 1023
MOTOROLA
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