Receiver - Motorola DragonBall MC9328MX1 Reference Manual

Reset = Peripheral Reset OR Software Reset
Deassert
Transmitter
FIFO Empty
Flag
Transmitter
N
Shift Register
Empty
Y
Figure 27-3. Transmitter

27.5.3 Receiver

The receiver accepts a serial data stream and converts it into parallel characters. When enabled, it searches
for a start bit, qualifies it, and samples the following data bits at the bit-center. Jitter tolerance and noise
immunity are provided by sampling at a 16x rate and using voting techniques to clean up the samples.
Once the start bit is found, the data bits, parity bit (if enabled), and stop bits (either 1 or 2 depending on
user selection) are shifted in. Parity is checked and its status reported in the URXDn_1/URXDn_2 register
when parity is enabled. Frame errors and BREAKs are also checked and reported. When a new character is
ready to be received by the RxFIFO, the receive data ready (RDR) bit in the UART Status Register 2
(USR2_1/USR2_2) is asserted and an interrupt is posted (if DREN = 1). If the receiver trigger level is set
to 0, the receiver ready interrupt flag (RRDY) is asserted and an interrupt is posted if the receiver ready
MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules
Assert
Transmitter
FIFO Empty
Flag
Y Transmitter
FIFO
Empty
N
Deassert
Transmitter
FIFO Empty
Flag
Y
Transmitter
FIFO
Empty
Reset
Deassert
Transmitter
FIFO Empty
Flag
Reset
Transmitter
N
FIFO
Empty
Y
FIFO
Empty Interrupt Suppression Flow Chart
Sub-Block Description
Reset
Deassert
N
Transmitter
FIFO Empty
Flag
Transmitter
Y
FIFO Contains > 2
Characters
Reset
Reset
N
27-11