High Frequency Clock Source; Figure 12-1 Clock Controller Module; Table 12-1 Clock Controller Module Signal Descriptions - Motorola DragonBall MC9328MX1 Reference Manual

Phase-Locked Loop and Clock Controller

12.2.2 High Frequency Clock Source

The System PLL produces the USBPLLCLK signal that is the source for the following clock signals:
• CLK48M—for the USB
• HCLK and BCLK—HCLK is the MC9328MX1 system clock and BCLK goes to the ARMTDMI
core.
• Peripheral Clocks 1, 2, and 3—The peripheral clocks (PERCLK) provide clock signals to both
integrated and external peripherals.
There are two possible external high frequency clock sources for the System PLL—an external 16 MHz
oscillator or the Bluetooth reference clock signal. The source is selected by the CLK16_SEL bit in the
Clock Source Control Register.
OSC_EN
OSC16
0
RFBTCLK16 1
CLK16_SEL
PRE-
MULT
OSC32 CLK32
XTALOSC
Wake-Up Logic
S
Table 12-1. Clock Controller Module Signal Descriptions
Signal Names I/O
RFBTCLK16 I
CLK48M O
FCLK O
12-2
CLK16M
1
System
PLL
0
System_SEL
MCU PLL
SPLLEN
PLL Stop &
MPLLEN
Figure 12-1. Clock Controller Module
16 MHz clock input from an external Bluetooth RF module through the
internal BTA module.
Continuous 48 MHz clock output when System PLL is enabled or when
external 48 MHz clock is selected.
Fast clock (FCLK) output to the CPU.
MC9328MX1 Reference Manual
OSC32
SYNC Logic
HCLK
System PLLCLK
USBDIV
PRESC
BCLKDIV
PCLKDIV1
PCLKDIV2
PCLKDIV3
HCLK
CLK48M
CLK16M
PREMCLK
FCLK
CLK0SEL [2:0]
Description
CLK32
RTC
CLK48M
USB
FCLK
CPU
BCLK
HCLK
System
PERCLK1
Internal
PERCLK2
Peripherals
PERCLK3
000
CLKO
CLKO
Default
MOTOROLA
Stop
Run
Run