Function Multiplexing Control Register; Table 8-3 Function Multiplexing Control Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Integrated portable system processor
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8.1.2 Function Multiplexing Control Register

The Function Multiplexing Control Register (FMCR) controls the multiplexing of the signal lines shared
by the SSI and SIM modules. It also controls the SDRAM/SyncFlash chip select lines and masking of the
external bus request. See Table 8-3 on page 8-3 for detailed description of bit settings.
FMCR
BIT
31
30
TYPE
r
r
0
0
RESET
BIT
15
14
TYPE
r
r
0
0
RESET
Table 8-3. Function Multiplexing Control Register Description
Name
Reserved
Reserved—These bits are reserved and should read 0.
Bits 31–9
SPI2_RXD_SEL
SPI2 Receive Data Input Select - Selects the
Bit 8
SPI2 Receive data INput source
SSI_RXFS_SEL
SSI Receive Frame Sync Input
Bit 7
Select—Selects the Receive Frame Sync input
source.
SSI_RXCLK_SEL
SSI Receive Clock Select—Selects the
Bit 6
Receive Clock input source.
SSI_RXDAT_SEL
SSI Receive Data Select—Selects the Receive
Bit 5
Data input source.
SSI_TXFS_SEL
SSI Transmit Frame Sync Select—Selects the
Bit 4
Transmit Frame Sync input source.
SSI_TXCLK_SEL
SSI Transmit Clock Select—Selects the
Bit 3
Transmit Clock input source.
MOTOROLA
Function Multiplexing Control Register
29
28
27
26
25
r
r
r
r
r
0
0
0
0
0
13
12
11
10
9
r
r
r
r
r
0
0
0
0
0
Description
System Control
24
23
22
21
r
r
r
r
0
0
0
0
0x0000
8
7
6
5
rw
rw
rw
rw
0
0
0
0
0x0003
0 = Input from SPI2_RXD-0 pin (AOUT of
GPIO port A[1])
1 = Input from SPI2_RXD_1 pin (AOUT of
Port D[9])
0 = Input from Port C[3] SSI_RXFS pin
1 = Input from Port B[14] SIM_SVEN pin
0 = Input from Port C[4] SSI_RXCLK pin
1 = Input from Port B[15] SIM_PD pin
0 = Input from Port C[5] SSI_RXDAT pin
1 = Input from Port B[16] SIM_TX pin
0 = Input from Port C[7] SSI_TXFS pin
1 = Input from Port B[18] SIM_RST pin
0 = Input from Port C[8] SSI_TXCLK pin
1 = Input from Port B[19] SIM_CLK pin
Programming Model
Addr
0x0021B808
20
19
18
17
16
r
r
r
r
r
0
0
0
0
0
4
3
2
1
0
rw
rw
rw
rw
rw
0
0
0
1
1
Settings
8-3

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