Ssi Data And Control Pins; Ssi_Txdat, Serial Transmit Data; Ssi_Rxdat, Serial Receive Data; Ssi_Txclk, Serial Transmit Clock - Motorola DragonBall MC9328MX1 Reference Manual

30.4 SSI Data and Control Pins

The SSI has six I/O pins. These pins are shared with either Port B or Port C pins, depending on the
configuration of the ports. See Section 30.2.3, "Pin Configuration for SSI," for more information. Each pin
is described in detail in the sections following Table 30-22.
Pin Description
Serial Transmit Data
Serial Receive Data
Serial Transmit Clock
Serial Receive Clock
Serial Transmit Frame Sync
Serial Receive Frame Sync

30.4.1 SSI_TXDAT, Serial Transmit Data

The SSI_TXDAT pin transmits data from the TXSR. While data is being transmitted, the SSI_TXDAT pin
is an output pin. This pin is disabled between data word transmissions and on the trailing edge of the bit
clock after the last bit of a word is transmitted. This pin has an internal pull-up controlled by the GPIO's
PUEN bit. For more information, refer to the Chapter 32, "GPIO Module and I/O Multiplexer (IOMUX)."

30.4.2 SSI_RXDAT, Serial Receive Data

The SSI_RXDAT pin brings serial data into the SSI Receive Shift Register (RXSR).

30.4.3 SSI_TXCLK, Serial Transmit Clock

The SSI_TXCLK pin can be used as either an input or an output. This clock signal is used by the
transmitter and can be either continuous or gated. During gated clock mode, data on the SSI_TXCLK pin is
valid only during the transmission of data. If the pull-up is disabled for this pin in the GPIO Module's
Pull-Up Enable Register, then the clock pin is tri-stated when data is not transmitting. In synchronous
mode, this pin is used by both the transmit and receive sections. When using gated clock mode, an external
resistor is connected to this pin to prevent the signal from floating when not being driven.

30.4.4 SSI_RXCLK, Serial Receive Clock

The SSI_RXCLK pin can be used as either an input or an output. This clock signal is used by the receiver
and is always continuous. During gated clock mode, the SSI_TXCLK pin is used instead for clocking in
2
data. In I S master mode, this pin is used as an output pin for the oversampling clock, SYS_CLK
(PerCLK3).
MOTOROLA
Table 30-22. SSI Pin Description
Pin Name
SSI_TXDAT
SSI_RXDAT
SSI_TXCLK
SSI_RXCLK
SSI_TXFS
SSI_RXFS
Synchronous Serial Interface (SSI)
SSI Data and Control Pins
Port C
Multiplexed Pin Multiplexed Pin
PTC [6]
PTC [5]
PTC [8]
PTC [4]
PTC [7]
PTC [3]
Port B
PTB [17]
PTB [16]
PTB [19]
PTB [15]
PTB [18]
PTB [14]
30-35