Fast Interrupt Pending Register Low; Table 10-29 Fast Interrupt Pending Register Low Description - Motorola DragonBall MC9328MX1 Reference Manual

10.4.13.2 Fast Interrupt Pending Register Low

FIPNDL
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Table 10-29. Fast Interrupt Pending Register Low Description
Name
FIPEND Fast Interrupt Pending Bit—Indicates if a fast interrupt
Bits 31–0 request is pending. When a fast interrupt enable bit is set and
the corresponding interrupt source is asserted, the interrupt
controller asserts a fast interrupt request. The fast interrupt
pending bits reflect the interrupt input lines that are asserted
and are currently enabled to generate a fast interrupt.
MOTOROLA
Fast Interrupt Pending Register Low
28 27 26 25
FIPEND [31:16]
r r r r
0 0 0 0
12 11 10 9
FIPEND [15:0]
r r r r
0 0 0 0
Description
Interrupt Controller (AITC)
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
r r r r r
0 0 0 0 0
0x0000
0 = No fast interrupt request
pending
1 = Fast interrupt request pending
Programming Model
Addr
0x00223064
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
r r r r
0 0 0 0
Settings
10-33