Motorola DragonBall MC9328MX1 Reference Manual page 907

Table 31-5. CSI Control Register 1 Description (Continued)
Name
GCLK_MODE Gated Clock Mode—Controls how data is
Bit 4 latched. When set, it latches data on selected
pixel clock edge and when CSI_HSYNC is logic
high. When reset, it latches data on selected pixel
clock edge regardless of CSI_HSYNC.
INV_DATA Invert Data Input—Inverts the CSI_D [7:0] data
Bit 3 lines before they are applied to the interface
circuitry.
INV_PCLK Invert PIXCLK Input—Inverts the CSI_PIXCLK
Bit 2 signal before they are applied to the interface
circuitry.
REDGE Rising Edge—Controls the edge of CSI_PIXCLK
Bit 1 that latches data.
EN Enable—Enables/Disables the CMOS Sensor
Bit 0 Interface module.
MOTOROLA
Description
CMOS Sensor Interface Module
Programming Model
Settings
0 = Latches data on the selected pixel
clock edge
1 = Latches data on selected pixel clock
edge and when CSI_HSYNC is logic
high.)
0 = No effect
1 = Inverts CSI_D [7:0] data lines
0 = No effect
1 = Inverts CSI_PIXCLK signal
0 = Latches data at the falling edge of
CSI_PIXCLK
1 = Latches data at the rising edge of
CSI_PIXCLK
0 = Disable CSI module
1 = Enable CSI module
31-7