Motorola DragonBall MC9328MX1 Reference Manual page 956

L_CH field, 16-30
LENGTH field, 16-30
PAYLOAD_HEADER register, 16-30
PCDR register
PCLK_DIV1 field, 12-9
PCLK_DIV2 field, 12-8
PCLK_DIV3 field, 12-8
PCDR register, 12-8
PCR register
ACD field, 19-23
ACDSEL bit, 19-23
BPIX field, 19-22
CLKPOL bit, 19-23
COLOR bit, 19-22
END_SEL bit, 19-23
FLMPOL bit, 19-23
LPPOL bit, 19-23
OEPOL bit, 19-23
PBSIZ field, 19-22
PCD field, 19-23
PIXPOL bit, 19-22
REV_VS bit, 19-23
SCLKIDLE bit, 19-23
SCLKSEL bit, 19-23
SHARP bit, 19-23
TFT bit, 19-22
PCR register, 19-22
PCR_n register
ACCESS_MODE field, 7-16
PCR_n register, 7-15
PE bit, 25-33
Pen A/D sample rate control register,
see ASP_PSMPLRG register
Pen ADC operation, 15-3
PERIODREG1 register, 18-13
PERIODREG2 register, 18-13
PERIODREGx register
CSRC bit, 18-13
WAIT field, 18-13
peripheral access registers, see PAR_n,
Peripheral clock divider register, see PCDR register
peripheral control registers, see PCR_n,
peripheral size registers, see PSRn_n registers
Phase-locked loop and clock control, see PLL and clock
control
PLL and clock control
ARM920T processor low power modes, 12-4
clock sources, 12-1
DPLL output frequency calculation, 12-3
DPLL phase and frequency jitter, 12-3
generation of 48 MHz clocks, 12-11
high frequency clock source, 12-2
introduction, 12-1
low frequency clock source, 12-1
Index-xiv
PLL operation at power-up, 12-4
PLL operation at wake-up, 12-4
power management in clock controller, 12-4
programming digital phase locked loops, 12-9
programming model, 12-5
SDRAM power modes, 12-4
POR signal, 6-3
Port A data direction register, see DDIR_A register
Port A data register, see DR_A register
Port A general purpose register, see GPR_A register
Port A GPIO in use register, see GIUS_A register
Port A input configuration register A1,
see ICONFA1_A register
Port A input configuration register A2,
see ICONFA2_A register
Port A input configuration register B1,
see ICONFB1_A register
Port A input configuration register B2,
see ICONFB2_A register
Port A interrupt configuration register 1,
see ICR1_A register
Port A interrupt configuration register 2,
see ICR2_A register
Port A interrupt mask register, see IMR_A register
Port A interrupt status register, see ISR_A register
Port A output configuration register 1,
see OCR1_A register,
Port A output configuration register 2,
see OCR1_A register
Port A pull_up enable register, see PUEN_A register
Port A sample status register, see SSR_A register
Port A software reset register, see SWR_A register
Port B data direction register, see DDIR_B register
Port B data register, see DR_B register
Port B general purpose register, see GPR_B register
Port B GPIO in use register, see GIUS_B register
Port B input configuration register A1,
see ICONFA1_B register
Port B input configuration register A2,
see ICONFA2_B register
Port B input configuration register B1,
see ICONFB1_B register
Port B input configuration register B2,
see ICONFB2_B register
Port B interrupt configuration register 1,
see ICR1_B register
Port B interrupt configuration register 2,
see ICR2_B register
Port B interrupt mask register, see IMR_B register
Port B interrupt status register, see ISR_B register
Port B output configuration register 1,
see OCR1_B register
Port B output configuration register 2,
see OCR1_B register
MC9328MX1 Reference Manual MOTOROLA