Calculating The Ssi Bit Clock From The Input Clock Value - Motorola DragonBall MC9328MX1 Reference Manual

Synchronous Serial Interface (SSI)
Table 30-15. SSI Transmit Clock Control Register and SSI Receive Clock Control Register
Name
WL Word Length—Selects the length (8, 10, 12, or 16 bits) of the data
Bits 14–13 words being transferred by the SSI. WL also controls the frame sync
pulse length when the length of the frame sync (SRCR:RFSL or
STCR:TFSL) is set to 1 word. The value of this field is used as a
divider value to convert serial bit clock to word clock as shown in
Figure 30-4.
DC Frame Rate Divider Control—Specifies the divide ratio for the
Bits 12–8 programmable frame rate divider shown in Figure 30-5. The divider
converts the word clock to the frame clock. In normal mode, this ratio
determines the word transfer rate. In network mode, this ratio sets the
number of words per frame.
In network mode, a divide ratio of one (DC = 00000) is a special case
(on-demand mode).
In normal mode, a divide ratio of one (DC = 00000) provides
continuous periodic data word transfer (a bit-length sync must be
used).
PM Prescale Modulus Select—Specifies the divide ratio for the modulus
Bits 7–0 divider shown in Figure 30-4. This divider is one of three dividers that
convert the PerCLK3 signal to the serial bit clock.

30.3.10.1 Calculating the SSI Bit Clock from the Input Clock Value

The serial bit clock is the result of the Clock Controller input PerCLK3 being divided by one fixed, one
selectable, and one programmable divider. Serial bit clock may range from the value (PerCLK3 / 4
× ×
to (PerCLK3 / (4 8 256)). See Figure 30-4 on page 30-5. Note that WL has a value of 8, 10, 12, or 16.
f
INT_BIT_CLK
f
FRAME_SYN_CLK
Example 1: When the 7-bit clock controller divider, PCLKDIV3 in the PLL and Clock Control module, is
set to 5, then PerCLK3 is 96 MHz ÷ 5 = 19.2 MHz.
The SSI is set up in normal mode with a word length of 8 (WL = 00), a frame rate divider control of 1
(DC = 0001), a prescale modulus of 74 (decimal) (PM = 01001010), and the PSR bit cleared (PSR = 0).
In this case, the bit clock rate is 19.2 MHz ÷ (4 × 1 × 75) = 64 kHz.
That means that the frame sync clock (SSI_TXFS) is 64 kHz ÷ (2 × 8) = 4 kHz.
Example 2: When the 7-bit clock controller divider, PCLKDIV3, is set to 8, then PerCLK3 is
96 MHz ÷ 8 = 12 MHz.
The SSI is set up in network mode, with a word length of 16 (WL = 11), a frame rate divider control of 1
(DC = 0001), a prescale modulus of 1 (decimal) (PM = 00000001), and the PSR bit cleared (PSR = 0).
In this case, the bit clock rate is 12 MHz ÷ (4 × 1 × 2) = 1.5 MHz.
That means that the frame sync clock (SSI_TXFS) is 1.5 MHz ÷ (2 × 16) = 46.875 kHz.
30-28
Description (Continued)
Description
= f ÷ [4 x (7 x PSR + 1) x (PM + 1)]
PerCLK3
= (f ) ÷ [(DC + 1) x WL]
INT_BIT_CLK
MC9328MX1 Reference Manual
Settings
00 = 8 Bits per word
01 = 10 Bits per word
10 = 12 Bits per word
11 = 16 Bits per word
00000 = Divide Ratio is 1
00001 = Divide Ratio is 2
...
11111 = Divide Ratio is 32
In network mode,
DC = 00000 is a special
case.
0x00 = Divide ratio is 1
0x01 = Divide ratio is 2
...
0xFF = Divide ratio is 256
× ×
1 1)
Eqn. 30-4
Eqn. 30-5
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