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Memory Stick Host Controller (MSHC) Module
21.7.1 Memory Stick Control/Status Register
The bit position assignments for the Memory Stick Control/Status Register are shown in the following
register display. The settings for this register are described in Table 21-8.
This register is initialized on power up or when RST bit of Memory Stick Control/Status Register is 1.
MSCS
BIT
15
14
RST
PWS
SIEN
TYPE
rw
rw
0
0
RESET
Table 21-8. Memory Stick Control/Status Register Description
Name
RST
Reset—Resets the MSHC module.
Bit 15
PWS
Power Save—Enables/Disables power save mode.
Bit 14
Data can only be written to MSCS register and the
MSICS register when PWS is 1. It is not possible to
write to PWS while the protocol is executing.
SIEN
Serial Interface Enable—Enables/Disables serial
Bit 13
Interface output enabled. Normally set to 1 during
operation.
DAKEN
XDAK Enable—Configures the internal DMA transfer
Bit 12
protocol by enabling the DMA acknowledge signal
XDAK. This XDAK signal supports 4-half-word burst
DMA transfer. Therefore, when the user needs to
configure the module for 4-half-word DMA burst
transfer mode, DAKEN bit must be set to 1. When the
user needs to configure the module for 1-half-word
burst DMA transfer mode, DAKEN bit can be set to
either value.
See NOTE of the RFF and TFE bits of the MSDRQC
register.
NOCRC
No CRC—Controls whether a CRC will be added to the
Bit 11
end of the data array. Normally, this bit remains at 0
during operation.
21-14
Memory Stick Control/Status Register
13
12
11
10
DAKEN
NOCRC
rw
rw
rw
rw
0
0
0
Description
MC9328MX1 Reference Manual
9
8
7
6
BSYCNT
INT
DRQ
rw
rw
r
r
1
0
1
0
0
0x050A
0 = No Reset
1 = Reset MSHC module
0 = Power save disabled
1 = Power save enabled
0 = Serial interface disabled
1 = Serial interface enabled
0 = XDAK input disabled
1 = XDAK input enabled
0 = CRC on
1 = CRC off
0x0021A002
5
4
3
2
1
RBE
RBF
TBE
r
r
r
r
r
0
0
1
0
1
Setting
MOTOROLA
Addr
0
TBF
r
0
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