Motorola MC68340 Manuals

Manuals and User Guides for Motorola MC68340. We have 2 Motorola MC68340 manuals available for free PDF download: User Manual

Motorola MC68340 User Manual (441 pages)

Integrated Processor with DMA

Brand: Motorola | Category: Computer Hardware | Size: 2.56 MB

4
Table of Contents
25
Block Diagram
25
Device Overview
26
M68300 Family
27
Advantages
27
Central Processor Unit
27
Organization
28
Background Debug Mode
28
Cpu32
29
External Bus Interface
29
On-Chip Peripherals
29
System Integration Module
30
Chip Select and Wait State Generation
30
Clock Synthesizer
30
Discrete I/O Pins
30
Interrupt Handling
30
System Configuration and Protection
31
Direct Memory Access Module
31
IEEE 1149.1 Test Access Port
31
Serial Module
32
Power Consumption Management
32
Timer Modules
33
Compact Disc-Interactive
33
Physical
34
More Information
35
Signal Descriptions
- 35
  Functional Signal Groups
36
Signal Index
38
Address Bus
38
Address Bus (A23-A0)
38
Address Bus (A31-A24)
38
Data Bus (D15-D0)
39
Chip Selects (Cs3-Cs0)
39
Function Codes (FC3-FC0)
40
Address Strobe ( AS )
40
Bus Control Signals
40
Data and Size Acknowledge ( DSACK1, DSACK0 )
40
Interrupt Request Level (Irq7, Irq6, Irq5, Irq3)
41
Bus Arbitration Signals
41
Bus Grant ( BG )
41
Bus Request ( BR )
41
Data Strobe ( DS )
41
Read/Write (R/ W )
41
Transfer Size (SIZ1, SIZ0)
42
Bus Error ( BERR )
42
Clock Signals
42
Exception Control Signals
42
Halt ( HALT )
42
Read-Modify-Write Cycle ( RMC )
42
Reset ( RESET )
43
Clock Mode Select (MODCK)
43
Crystal Oscillator (EXTAL, XTAL)
43
External Filter Capacitor (XFC)
43
Instruction Fetch (IFETCH)
43
Instruction Pipe (IPIPE)
43
Instrumentation and Emulation Signals
44
Breakpoint (BKPT)
44
DMA Acknowledge (DACK2, DACK1)
44
DMA Done ( DONE2, DONE1 )
44
DMA Module Signals
44
DMA Request ( DREQ2, DREQ1 )
44
Freeze (FREEZE)
45
Clear to Send (CTSA, CTSB)
45
Receive Data (Rxda, Rxdb)
45
Serial Crystal Oscillator (X2, X1)
45
Serial External Clock Input (SCLK)
45
Serial Module Signals
45
Transmit Data (Txda, Txdb)
46
Receiver Ready ( R RDYA )
46
Timer Gate ( TGATE2, TGATE1 )
46
Timer Input (TIN2, TIN1)
46
Timer Output (TOUT2, TOUT1)
46
Timer Signals
47
Synthesizer Power (VCCSYN )
47
Test Clock (TCK)
47
Test Data in (TDI)
47
Test Data Out (TDO)
47
Test Mode Select (TMS)
47
Test Signals
50
Bus Operation
50
Bus Transfer Signals
51
Bus Control Signals
- 51
  Input Sample Window
52
Function Code Signals
53
Address Bus (A31-A0)
53
Address Strobe ( AS )
53
Bus Cycle Termination Signals
53
Data Bus (D15-D0)
53
Data Strobe ( DS )
53
Data Transfer and Size Acknowledge Signals ( DSACK1 and DSACK0 )
54
Autovector ( AVEC )
54
Bus Error ( BERR )
54
Data Transfer Mechanism
54
Dynamic Bus Sizing
56
Byte Operand to 8-Bit Port, Odd or Even (A0 = X)
- 56
  MC68340 Interface to Various Port Sizes
56
Misaligned Operands
56
Operand Transfer Cases
57
Byte Operand to 16-Bit Port, Even (A0 = 0)
58
Byte Operand to 16-Bit Port, Odd (A0 = 1)
58
Word Operand to 8-Bit Port, Aligned
59
Long-Word Operand to 8-Bit Port, Aligned
- 60
  Long-Word Operand Read Timing From 8-Bit Port
59
Word Operand to 16-Bit Port, Aligned
61
Long-Word Operand to 16-Bit Port, Aligned
- 61
  Long-Word Operand Write Timing to 8-Bit Port
- 62
  Long-Word and Word Read and Write Timing—16-Bit Port
63
Bus Operation
63
Synchronous Operation with DSACK
64
Fast Termination Cycles
- 64
  Fast Termination Timing
65
Data Transfer Cycles
65
Read Cycle
67
Write Cycle
68
Read-Modify-Write Cycle
70
CPU Space Address Encoding
70
CPU Space Cycles
71
Breakpoint Acknowledge Cycle
72
LPSTOP Broadcast Cycle
73
Breakpoint Operation Flowchart
74
Breakpoint Acknowledge Cycle Timing (Opcode Returned)
75
Breakpoint Acknowledge Cycle Timing (Exception Signaled)
76
Interrupt Acknowledge Bus Cycles
76
Interrupt Acknowledge Cycle-Terminated Normally
76
Module Base Address Register Access
77
Interrupt Acknowledge Cycle Flowchart
78
Autovector Interrupt Acknowledge Cycle
78
Interrupt Acknowledge Cycle Timing
79
Spurious Interrupt Cycle
80
Autovector Operation Timing
81
Bus Exception Control Cycles
83
Bus Errors
- 84
  Bus Error Without DSACK
85
Late Bus Error with DSACK
85
Retry Operation
86
Retry Sequence
87
Halt Operation
87
Late Retry Sequence
88
Double Bus Fault
88
HALT Timing
89
Bus Arbitration
- 90
  Bus Arbitration Flowchart for Single Request
- 91
  Bus Arbitration Timing Diagram—Active Bus Case
- 91
  Bus Arbitration Timing Diagram—Idle Bus Case
92
Bus Grant
92
Bus Grant Acknowledge
92
Bus Request
93
Bus Arbitration Control
93
Show Cycles
94
Bus Arbitration State Diagram
95
Reset Operation
95
Show Cycle Timing Diagram
96
Timing for External Devices Driving RESET
97
Power-Up Reset Timing Diagram
98
Module Overview
98
System Integration Module
99
Module Base Address Register Operation
99
Module Operation
100
System Configuration and Protection Operation
- 100
  SIM40 Module Register Block
101
Double Bus Fault Monitor
101
Internal Bus Monitor
101
Periodic Interrupt Timer
101
Software Watchdog
101
Spurious Interrupt Monitor
- 102
  System Configuration and Protection Function
- 104
  Software Watchdog Block Diagram
105
Periodic Timer Period Calculation
106
Clock Synthesizer Operation
- 107
  Clock Block Diagram for Crystal Operation
- 107
  MC68340 Crystal Oscillator
106
Simultaneous Interrupts By Sources in the SIM40
106
Using the Periodic Timer As a Real-Time Clock
108
Clock Control
- 108
  Clock Block Diagram for External Oscillator Operation
108
Phase Comparator and Filter
110
Chip Select Operation
111
Programmable Features
- 111
  Global Chip Select Operation
112
External Bus Interface Operation
- 112
  Port a
- 113
  Port B
- 113
  Full Interrupt Request Multiplexer
114
Freeze
114
Low-Power Stop
115
Programming Model
- 116
  SIM40 Programming Model
117
Module Base Address Register (MBAR)
- 118
  Module Configuration Register (MCR)
- 120
  Autovector Register (AVR)
- 120
  Reset Status Register (RSR)
- 121
  Software Interrupt Vector Register (SWIV)
  - 124
    Periodic Interrupt Timer Register (PITR)
  - 125
    Clock Synthesizer Control Register (SYNCR)
- 134
  System Protection Control Register (SYPCR) (Note That This Register Can Only Be Written
118
System Configuration and Protection Registers
135
SIM40 Example Configuration Code
138
Overview
139
Features
139
Virtual Memory
140
CPU32 Block Diagram
140
Loop Mode Instruction Execution
140
Loop Mode Instruction Sequence
141
Exception Handling
141
Vector Base Register
142
Addressing Modes
142
Instruction Set
144
Low-Power STOP Instruction
144
Privilege States
144
Processing States
144
Table Lookup and Interpolate Instructions
145
Architecture Summary
145
Programming Model
- 146
  User Programming Model
- 146
  Supervisor Programming Model Supplement
147
Registers
- 147
  Status Register
148
Instruction Set
148
Low-Power Stop (LPSTOP)
- 149
  Table Lookup and Interpolation (TBL)
148
M68000 Family Compatibility
148
New Instructions
149
Instruction Format and Notation
- 149
  Instruction Word General Format
149
Unimplemented Instructions
152
Instruction Summary
157
Condition Code Register
158
Data Movement Instructions
159
Integer Arithmetic Operations
161
Logic Instructions
161
Shift and Rotate Instructions
162
Bit Manipulation Instructions
163
Binary-Coded Decimal (BCD) Instructions
163
Program Control Instructions
164
System Control Instructions
166
Condition Tests
166
Using the TBL Instructions
167
Table Example 1: Standard Usage
168
Table Example 2: Compressed Table
- 169
  Table Example 3: 8-Bit Independent Variable
- 170
  Table Example 3
171
Table Example 4: Maintaining Precision
173
Nested Subroutine Calls
173
Pipeline Synchronization with the NOP Instruction
173
Processing States
173
Table Example 5: Surface Interpolations
174
Privilege Levels
174
State Transitions
175
Supervisor Privilege Level
175
User Privilege Level
- 175
  Changing Privilege Level
- 175
  Exception Stack Frame
176
Exception Vectors
- 177
  Exception Vectors
- 177
  Types of Exceptions
- 178
  Exception Processing Sequence
- 178
  Exception Stack Frame
- 178
  Multiple Exceptions
- 179
  Address Error
- 179
  Bus Error
- 181
  Reset Operation Flowchart
- 183
  Instruction Traps
- 183
  Software Breakpoints
- 184
  Format Error
- 184
  Hardware Breakpoints
- 184
  Illegal or Unimplemented Instructions
- 185
  Privilege Violations
- 186
  Tracing
- 187
  Interrupts
- 188
  Return From Exception
189
Fault Recovery
- 191
  Types of Faults
- 194
  Correcting a Fault
197
CPU32 Stack Frames
- 197
  Four-Word Stack Frame
- 197
  Six-Word Stack Frame
- 197
  Bus Error Stack Frame
198
Internal Transfer Count Register
- 199
  Format $C—BERR Stack for Prefetches and Operands
- 199
  Format $C—BERR Stack On MOVEM Operand
200
CPU32 Integrated Development Support
200
Development Support
- 200
  Format $C—Four- and Six-Word BERR Stack
- 201
  Background Debug Mode (BDM) Overview
- 201
  Deterministic Opcode Tracking Overview
- 201
  On-Chip Hardware Breakpoint Overview
201
Bus State Analyzer Configuration
201
In-Circuit Emulator Configuration
202
Background Debug Mode
- 202
  Enabling BDM
202
BDM Block Diagram
- 203
  BDM Sources
  - 203
    External BKPT Signal
  - 204
    BGND Instruction
  - 204
    Double Bus Fault
- 204
  Command Execution
- 204
  BDM Registers
  - 204
    Fault Address Register (FAR)
  - 204
    Return Program Counter (RPC)
- 205
  Returning From BDM
- 205
  Serial Interface
205
BDM Command Execution Flowchart
- 206
  CPU Serial Logic
207
Debug Serial I/O Block Diagram
- 208
  Development System Serial Logic
208
Serial Interface Timing Diagram
- 209
  BKPT Timing for Single Bus Cycle
209
BKPT Timing for Forcing BDM
- 209
  BKPT /DSCLK Logic Diagram
- 210
  Command Set
  - 210
    Command Format
  - 211
    Command Sequence Diagram
  - 212
    Command Set Summary
212
Command-Sequence Diagram
- 213
  Read A/D Register RAREG/RDREG
- 213
  Write A/D Register (WAREG/WDREG)
- 213
  Read System Register RSREG
- 213
  Write System Register WSREG
- 213
  Read Memory Location READ
- 213
  Write Memory Location WRITE
- 224
  Future Commands
224
Deterministic Opcode Tracking
- 224
  Instruction Fetch ( IFETCH )
- 224
  Instruction Pipe ( IPIPE )
224
Functional Model of Instruction Pipeline
- 225
  Opcode Tracking During Loop Mode
225
Instruction Pipeline Timing Diagram
226
Instruction Execution Timing
226
Resource Scheduling
- 226
  Microsequencer
- 226
  Bus Controller Resources
- 227
  Instruction Pipeline
  - 227
    Prefetch Controller
227
Block Diagram of Independent Resources
- 228
  Write Pending Buffer
- 228
  Microbus Controller
- 228
  Instruction Execution Overlap
228
Simultaneous Instruction Execution
- 229
  Effects of Wait States
- 229
  Instruction Execution Time Calculation
229
Attributed Instruction Times
- 230
  Effects of Negative Tails
231
Instruction Stream Timing Examples
- 231
  Timing Example 1—Execution Overlap
- 232
  Example 1—Instruction Stream
- 232
  Example 2—Branch Taken
- 232
  Timing Example 2-Branch Instructions
  - 233
    Example 2—Branch Not Taken
  - 233
    Example 3—Branch Negative Tail
- 233
  Timing Example 3-Negative Tails
234
Instruction Timing Tables
- 236
  Fetch Effective Address
- 237
  Calculate Effective Address
- 238
  MOVE Instruction
- 238
  Special-Purpose MOVE Instruction
- 239
  Arithmetic/Logic Instructions
- 242
  Immediate Arithmetic/Logic Instructions
- 243
  Binary-Coded Decimal and Extended Instructions
- 244
  Single Operand Instructions
- 245
  Shift/Rotate Instructions
- 246
  Bit Manipulation Instructions
- 247
  Conditional Branch Instructions
- 248
  Control Instructions
- 249
  Exception-Related Instructions and Operations
- 250
  Save and Restore Operations
  - 251
    DMA Controller Module
- 251
  DMA Block Diagram
252
DMA Module Overview
- 253
  Single-Address Transfers
- 253
  Dual-Address Transfer
254
DMA Acknowledge ( DACK )
254
DMA Done ( DONE )
254
DMA Module Signal Definitions
254
DMA Request ( DREQ )
254
Internal Request Generation
- 255
  Internal Request, Maximum Rate
- 255
  Internal Request, Limited Rate
254
Transfer Request Generation
255
External Request Generation
- 255
  External Burst Mode
- 255
  External Cycle Steal Mode
256
Data Transfer Modes
- 256
  Single-Address Mode
- 256
  DMA External Connections to Serial Module
- 257
  Single-Address Read
- 258
  Single-Address Read Timing (External Burst)
- 260
  Single-Address Write
- 260
  Single-Address Write Timing (External Burst)
- 262
  Dual-Address Mode
- 262
  Dual-Address Read
264
Dual-Address Write
268
Bus Arbitration
- 268
  Channel Initialization and Startup
- 269
  Data Transfers
  - 269
    Internal Request Transfers
  - 269
    External Request Transfers
- 270
  Channel Termination
  - 270
    Interrupt Operation
268
DMA Channel Operation
270
Fast Termination Option
271
Fast Termination Option (Cycle Steal)
- 272
  Fast Termination Option (External Burst—Source Requesting)
- 273
  Module Configuration Register (MCR)
272
Register Description
273
DMA Module Programming Model
- 276
  Interrupt Register (INTR)
- 276
  Channel Control Register (CCR)
- 280
  Channel Status Register (CSR)
- 282
  Function Code Register (FCR)
- 283
  Source Address Register (SAR)
- 283
  Destination Address Register (DAR)
- 284
  Byte Transfer Counter Register (BTC)
285
Data Packing
285
Packing and Unpacking of Operands
286
DMA Channel Initialization Sequence
- 286
  DMA Channel Configuration
  - 287
    DMA Channel Operation in Single-Address Mode
  - 287
    DMA Channel Operation in Dual-Address Mode
- 288
  DMA Channel Example Configuration Code
- 296
  Simplified Block Diagram
- 297
  Module Overview
- 298
  Serial Communication Channels a and B
- 298
  Baud Rate Generator Logic
- 298
  Internal Channel Control Logic
- 298
  Interrupt Control Logic
- 299
  Comparison of Serial Module to MC68681
299
Serial Module Signal Definitions
- 300
  Crystal Input or External Clock (X1)
- 300
  Crystal Output (X2)
- 300
  External and Internal Interface Signals
- 301
  External Input (SCLK)
- 301
  Channel a Transmitter Serial Data Output (Txda)
- 301
  Channel a Receiver Serial Data Input (Rxda)
- 301
  Channel B Transmitter Serial Data Output (Txdb)
- 301
  Channel B Receiver Serial Data Input (Rxdb)
- 301
  Channel a Request-To-Send ( RTSA )
  - 302
    Rtsb
- 302
  Channel a Clear-To-Send ( CTSA )
- 302
  Channel B Clear-To-Send ( CTSB )
- 302
  Channel a Transmitter Ready ( T RDYA )
  - 302
    T Rdya
- 302
  Channel a Receiver Ready ( R RDYA )
303
Operation
- 303
  Baud Rate Generator
- 303
  Transmitter and Receiver Operating Modes
- 303
  Baud Rate Generator Block Diagram
- 304
  Transmitter and Receiver Functional Diagram
- 305
  Transmitter
  - 305
    Transmitter Timing Diagram
  - 306
    Receiver
  - 307
    FIFO Stack
- 307
  Receiver Timing Diagram
- 309
  Looping Modes
  - 309
    Automatic Echo Mode
  - 309
    Local Loopback Mode
  - 309
    Remote Loopback Mode
- 310
  Multidrop Mode
  - 310
    Looping Modes Functional Diagram
  - 311
    Multidrop Mode Timing Diagram
  - 312
    Bus Operation
  - 312
    Interrupt Acknowledge Cycles
  - 312
    Read Cycles
  - 312
    Register Description and Programming
  - 312
    Write Cycles
- 314
  Serial Module Programming Model
  - 314
    Module Configuration Register (MCR)
  - 316
    Interrupt Level Register (ILR)
  - 316
    Interrupt Vector Register (IVR)
  - 317
    Mode Register 1 (MR1)
  - 319
    Status Register (SR)
  - 321
    Clock-Select Register (CSR)
  - 322
    Command Register (CR)
  - 325
    Receiver Buffer (RB)
  - 325
    Transmitter Buffer (TB)
  - 326
    Input Port Change Register (IPCR)
  - 327
    Auxiliary Control Register (ACR)
  - 327
    Interrupt Status Register (ISR)
  - 329
    Interrupt Enable Register (IER)
  - 330
    Input Port (IP)
  - 331
    Output Port Control Register (OPCR)
  - 332
    Output Port Data Register (OP)
  - 333
    Mode Register 2 (MR2)
  - 335
    I/O Driver Example
    - 335
      Interrupt Handling
    - 335
      Programming
  - 335
    Serial Module Initialization
336
Serial Module Programming Flowchart
341
Serial Module Initialization Sequence
- 341
  Serial Module Configuration
- 342
  Serial Module Example Configuration Code
- 345
  Module Overview
- 345
  Simplified Block Diagram
- 346
  Timer and Counter Functions
  - 346
    Prescaler and Counter
  - 346
    Timeout Detection
  - 346
    Comparator
  - 347
    Clock Selection Logic
- 347
  Internal Control Logic
- 347
  Timer Functional Diagram
- 348
  Interrupt Control Logic
348
Timer Modules Signal Definitions
- 349
  Timer Input (TIN1, TIN2)
- 349
  External and Internal Interface Signals
- 350
  Timer Gate ( TGATE1 , TGATE2 )
- 350
  Timer Output (TOUT1, TOUT2)
350
Operating Modes
- 350
  Input Capture/Output Compare
- 351
  Input Capture/Output Compare Mode
- 352
  Square-Wave Generator
- 352
  Square-Wave Generator Mode
- 353
  Variable Duty-Cycle Square-Wave Generator
- 354
  Variable-Width Single-Shot Pulse Generator
- 354
  Variable Duty-Cycle Square-Wave Generator Mode
- 355
  Variable-Width Single-Shot Pulse Generator Mode
- 356
  Pulse-Width Measurement
- 356
  Pulse-Width Measurement Mode
- 357
  Period Measurement
358
Event Count
- 358
  Period Measurement Mode
- 359
  Event Count Mode
- 360
  Timer Bypass
  - 361
    Bus Operation
  - 361
    Interrupt Acknowledge Cycles
  - 361
    Read Cycles
  - 361
    Register Description
  - 361
    Write Cycles
  - 362
    Module Configuration Register (MCR)
- 364
  Control Register (CR)
- 364
  Interrupt Register (IR)
- 367
  Status Register (SR)
- 369
  Counter Register (CNTR)
- 369
  Preload 1 Register (PREL1)
- 370
  Compare Register (COM)
- 370
  Preload 2 Register (PREL2)
362
Timer Module Programming Model
371
Timer Module Initialization Sequence
- 371
  Timer Module Configuration
- 372
  Timer Module Example Configuration Code
376
Overview
- 377
  TAP Controller
- 377
  Test Access Port Block Diagram
378
Boundary Scan Register
- 378
  TAP Controller State Machine
- 382
  Input Pin Cell (I.pin)
- 382
  Output Latch Cell (O.latch)
- 383
  Active-High Output Control Cell (Io.ctl1)
- 383
  Active-Low Output Control Cell (Io.ctl0)
384
Instruction Register
- 384
  Bidirectional Data Cell (Io.cell)
- 384
  General Arrangement for Bidirectional Pins
- 385
  Extest (000)
- 385
  Sample/Preload (001)
- 386
  Bypass (X1X, 101)
- 386
  Hi-Z (100)
386
MC68340 Restrictions
- 386
  Bypass Register
387
Non-Ieee 1149.1 Operation
388
Minimum System Configuration
- 388
  Processor Clock Circuitry
388
Minimum System Configuration Block Diagram
389
Sample Crystal Circuit
389
Statek Corporation Crystal Circuit
- 390
  Reset Circuitry
390
SRAM Interface
391
ROM Interface
391
Serial Interface
392
External Circuitry for 8-Bit Boot ROM
- 393
  Access Time Calculations
392
Memory Interface Information
- 392
  Using an 8-Bit Boot ROM
- 392
  Serial Interface
393
Access Time Computation Diagram
- 394
  Calculating Frequency-Adjusted Output
393
Bit Boot ROM Timing
394
Signal Relationships to CLKOUT
395
Signal Width Specifications
396
Skew Between Two Outputs
397
Interfacing an 8-Bit Device to 16-Bit Memory Using Single-Address DMA Mode
397
Power Consumption Considerations
- 398
  MC68340 Power Reduction at 5V
398
MC68340 Current Vs. Activity at 5 V
399
MC68340 Current Vs. Clock Frequency at 5 V
- 400
  Mc68340V (3.3 V)
399
MC68340 Current Vs. Voltage/Temperature
401
Thermal Characteristics
402
AC Electrical Specification Definitions
402
Power Considerations
404
Drive Levels and Test Points for AC Specifications
405
DC Electrical Specifications
406
AC Electrical Specifications Control Timing
408
AC Timing Specifications
411
Read Cycle Timing Diagram
412
Write Cycle Timing Diagram
413
Fast Termination Read Cycle Timing Diagram
414
Fast Termination Write Cycle Timing Diagram
- 415
  Bus Arbitation Timing—Active Bus Case
- 416
  Bus Arbitration Timing—Idle Bus Case
416
Show Cycle Timing Diagram
417
IACK Cycle Timing Diagram
418
Background Debug Mode FREEZE Timing
418
Background Debug Mode Serial Port Timing
419
DMA Module AC Electrical Specifications
419
DMA Signal Timing Diagram
420
Timer Module Clock Signal Timing Diagram
420
Timer Module Electrical Specifications
421
Timer Module Signal Timing Diagram
422
Serial Module Electrical Specifications
422
Serial Module General Timing Diagram
424
IEEE 1149.1 Electrical Specifications
426
Pin Assignment
- 427
  Lead Ceramic Quad Flat Pack (FE Suffix)
- 429
  Lead Plastic Pin Grid Array (RP Suffix)
426
Standard MC68340 Ordering Information
431
Package Dimensions
- 431
  FE Suffix
- 432
  RP Suffix

Motorola MC68340 User Manual (472 pages)

Integrated, with DMA

Brand: Motorola | Category: Processor | Size: 29.62 MB

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Manuals and User Guides for Motorola MC68340. We have 2 Motorola MC68340 manuals available for free PDF download: User Manual

Motorola MC68340 User Manual (441 pages)

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Motorola MC68340 User Manual (472 pages)

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