Figure 24-29 Self-Refresh Entry Due To Low-Power Mode Timing Diagram; Figure 24-30 Low-Power Mode Self-Refresh Exit Timing Diagram - Motorola DragonBall MC9328MX1 Reference Manual

SDRAM Memory Controller
Low-Power Mode
Signal from CPU
SDRAM Low-Power
Mode Acknowledge
Signal
SDCLK
SDCKEx
ADDR
RAS,
CAS,
SDW
CSDx
DATA
DATA
Figure 24-29. Self-Refresh Entry Due to Low-Power Mode Timing Diagram
Low-Power Mode
Signal from CPU
SDRAM Low-Power
Mode Acknowledge
Signal
SDCLK
SDCKEx
ADDR
RAS,
CAS,
SDWE
CSDx
DATA
Figure 24-30. Low-Power Mode Self-Refresh Exit Timing Diagram
24-34
A10 = 1
PRE-ALL
A
NOP NOP
MC9328MX1 Reference Manual
>= t
RP
SLFRRSH
>= t + 1 Clock
RC
NOP REF A
MOTOROLA