Dma Interrupt Mask Register; Table 13-5 Dma Interrupt Mask Register Description - Motorola DragonBall MC9328MX1 Reference Manual

DMA Controller

13.4.1.3 DMA Interrupt Mask Register

The DMA Interrupt Mask Register (DIMR) masks both normal interrupts and error interrupts generated by
the corresponding channel. There is one control bit for each channel. When an interrupt is masked, the
interrupt controller does not generate an interrupt request to the AITC, however the status of the interrupt
can be observed from the interrupt status register, burst time-out status register, request time-out status
register, or the transfer error status register. At reset, all the interrupts are masked and all the bits in this
register are set to 1.
DIMR
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–11
CH10–CH0 Channel 10 to 0—Controls the interrupts for each DMA channel.
Bits 10–0
13-10
DMA Interrupt Mask Register
28 27 26 25
r r r
0 0 0
12 11 10
CH10 CH9
r r rw rw
0 0 1
Table 13-5. DMA Interrupt Mask Register Description
Description
MC9328MX1 Reference Manual
24 23 22 21
r r r r r
0 0 0 0 0
0x0000
9 8 7 6 5
CH8 CH7 CH6 CH5
rw rw rw rw
1 1 1 1 1
0x07FF
Addr
0x00209008
20 19 18 17
r r r r
0 0 0 0
4 3 2 1
CH4 CH3 CH2 CH1
rw rw rw rw
1 1 1 1
Settings
0 = Enables interrupts
1 = Disables interrupts
MOTOROLA
16
r
0
0
CH0
rw
1