Motorola DragonBall MC9328MX1 Reference Manual page 35

List of Tables List of Tables
MC9328MX1 Reference Manual Revision History Rev. 1 . . . . . . . . . . . . . . . . . liv
Table 1-1 Endpoint Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Table 2-1 MC9328MX1 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Table 2-2 MC9328MX1 Signal Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Table 3-1 MCU Memory Space (Physical Addresses) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Table 3-2 MC9328MX1 Internal Registers Sorted by Address . . . . . . . . . . . . . . . . . . . . . 3-6
Table 4-1 ARM920T Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Table 4-2 ARM Thumb Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Table 4-3 Register Availability by Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Table 5-1 ETM Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Table 6-1 Reset Module Pin and Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Table 6-2 RSR Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Table 6-3 Hardware Reset Source Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Table 7-1 R-AHB to IP Bus Interface Operation (Big Endian-Read Operation) . . . . . . . 7-4
Table 7-2 R-AHB to IP Bus Interface Operation (Big Endian-Write Operation) . . . . . . 7-5
Table 7-3 R-AHB to IP Bus Interface Operation (Little Endian-Read Operation) . . . . . 7-7
Table 7-4 R-AHB to IP Bus Interface Operation (Little Endian-Write Operation) . . . . . 7-8
Table 7-5 AIPI Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Table 7-6 Peripheral Address MODULE_EN Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Table 7-7 AIPI1 Peripheral Size Register 0
and AIPI2 Peripheral Size Register 0 Description . . . . . . . . . . . . . . . . . . . 7-12
Table 7-8 AIPI1 Peripheral Size Register 1
and AIPI2 Peripheral Size Register 1 Description . . . . . . . . . . . . . . . . . . . 7-13
Table 7-9 PSR Data Bus Size Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
Table 7-10 Peripheral Access Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
Table 7-11 Peripheral Control Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
Table 7-12 Time-Out Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
Table 7-13 Core and 8-Bit Peripheral Register Content After Code Execution . . . . . . . . . 7-18
Table 7-14 Core and 16-Bit Peripheral Register Content (Little Endian). . . . . . . . . . . . . . 7-18
Table 7-15 Core and 16-Bit Peripheral Register Content (Big Endian) . . . . . . . . . . . . . . . 7-19
Table 7-16 Core and 32-bit Peripheral Register Content (Little Endian) . . . . . . . . . . . . . . 7-20
Table 7-17 Core and 32-bit Peripheral Register Content (Big Endian) . . . . . . . . . . . . . . . 7-20
Table 8-1 System Control Module Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Table 8-2 Silicon ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
MOTOROLA List of Tables xxxv