Spi Block Diagram; Table 18-1 Spi 1 And Spi 2 Signal Multiplexing - Motorola DragonBall MC9328MX1 Reference Manual

Chapter 18
Serial Peripheral Interface Modules
(SPI 1 and SPI 2)
The MC9328MX1 contains two identical serial peripheral interface modules (SPI 1 and SPI 2). Due to pin
availability, the SPI 2 module operates in master mode only and does not support the SPI Ready
(SPI_RDY) control signal function.
SPI 1 signals are multiplexed with GPIO ports as primary functions. See Chapter 2, "Signal Descriptions
and Pin Assignments," for detailed pin assignments. SPI 2 signals are connected to the "IN" and "OUT"
ports of the GPIO modules. The user must configure the corresponding GPIO registers to make SPI 1 and
SPI 2 signals available at the pins. See Section 18.2.3, "Pin Configuration for SPI 1 and SPI 2," for more
information about selecting SPI 1 and SPI 2 signals.
SPI Signal Names
SPI1_SPI_RDY
SPI1_SCLK
SPI1_SS
SPI1_MISO
SPI1_MOSI
SPI2_SCLK
SPI2_SS
SPI2_RXD
SPI2_TXD

18.1 SPI Block Diagram

This section describes how the SPI modules communicate with external devices.
Each SPI module has one 8
(TXFIFO). The SPI ready (SPI_RDY) and slave select (SS) control signals enable fast data
communication with fewer software interrupts. The block diagram shown in Figure 18-1 on page 18-2 is
the same for each SPI module, except that the SPI 2 module does not support the SPI_RDY control signal
function.
MOTOROLA
Table 18-1. SPI 1 and SPI 2 Signal Multiplexing
Primary function of GPIO port C [13]
Primary function of GPIO port C [14]
Primary function of GPIO port C [15]
Primary function of GPIO port C [16]
Primary function of GPIO port C [17]
AIN of GPIO port A [0] or AIN of port D [7]
AIN of GPIO port A [17] or AIN of port D [8]
AOUT of GPIO port A [1] or AOUT of port D [9]
BIN of GPIO port D [31] or AIN of port D [10]
×
16-bit receive buffer (RXFIFO) and one 8
Serial Peripheral Interface Modules (SPI 1 and SPI 2)
Connect to GPIO Signal
×
16-bit transmit buffer
18-1