Table 28-15 Endpoint N Interrupt Status Registers Description - Motorola DragonBall MC9328MX1 Reference Manual

USB_EP0_INTR
USB_EP1_INTR
USB_EP2_INTR
USB_EP3_INTR
USB_EP4_INTR
USB_EP5_INTR
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Table 28-15. Endpoint n Interrupt Status Registers Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–9
FIFO_FULL FIFO Full—Indicates whether the FIFO is full or not.
Bit 8
FIFO_EMPTY FIFO Empty—Indicates whether the FIFO is empty or
Bit 7 not.
FIFO_ERROR FIFO Error—Indicates an error condition in the FIFO
Bit 6 controller. The specific error condition can be checked
by reading the Endpoint n FIFO Status Register
(USB_EPn_FSTAT).
FIFO_HIGH FIFO High—Asserts when the FIFO has hit a high
Bit 5 level alarm. FIFO_HIGH applies only when the FIFO
is in receive mode (USB OUT).
FIFO_LOW FIFO Low—Asserts when the FIFO has hit a low level
Bit 4 alarm. FIFO_LOW applies only when the FIFO is in
transmit mode (USB IN).
MOTOROLA
Endpoint 0 Interrupt Status Register
Endpoint 1 Interrupt Status Register
Endpoint 2 Interrupt Status Register
Endpoint 3 Interrupt Status Register
Endpoint 4 Interrupt Status Register
Endpoint 5 Interrupt Status Register
28 27 26 25 24
r r r r r
0 0 0 0 0
12 11 10 9 8
FIFO_
FULL
r r r r rw
0 0 0 0 0
Description
USB Device Port
23 22 21
r r r
0 0 0
0x0000
7 6 5
FIFO_ FIFO_ FIFO_ FIFO_
EMPTY ERROR HIGH LOW
rw rw rw
1 0 0
0x0080
0 = The FIFO is not full
1 = The FIFO is full
0 = The FIFO is not empty
1 = The FIFO is empty
0 = No error condition pending
1 = Error condition pending
0 = The number of data bytes in the FIFO
is less than GR value from the
Endpoint n FIFO Control Register
1 = The number of free bytes in the FIFO
is less than ALRM value from the
Endpoint n FIFO Alarm Register
0 = The number of free bytes in the FIFO
is less than 4xGR value from the
Endpoint n FIFO Control Register
1 = The number of data bytes in the FIFO
is less than ALRM value from the
Endpoint n FIFO Alarm Register
Programming Model
Addr
0x00212034
0x00212064
0x00212094
0x002120C4
0x002120F4
0x00212124
20 19 18 17
r r r r
0 0 0 0
4 3 2 1
MDEV DEV
EOT EOF
REQ REQ
rw rw rw rw
0 0 0 0
Settings
28-21
16
r
0
0
rw
0