Motorola DragonBall MC9328MX1 Reference Manual page 847

Table 29-6. I
Name
MSTA Master/Slave Mode Select—Selects master or
Bit 5 slave mode operation. When the device loses
arbitration while running in master mode, MSTA is
cleared without generating a STOP signal.
MTX Transmit/Receive Mode Select—Selects the
Bit 4 direction of master and slave transfers.
Note: When a slave is addressed during transmit
mode, software sets MTX according to the Slave
Read/Write (SRW) bit in the I2SR Register. In
master mode, MTX is set according to the type of
transfer required. Therefore, for address cycles,
MTX is always set for master mode and cleared for
slave mode.
TXAK Transmit Acknowledge Enable—Specifies the
Bit 3 value driven onto SDA during data acknowledge
cycles for both master mode and slave mode
receivers.
Note: TXAK applies only when the I
receiver.
RSTA Repeated START—Generates a repeated START
Bit 2 condition. This bit always reads 0. Attempting a
repeated START without bus mastership causes
loss of arbitration.
Reserved Reserved—These bits are reserved and should read 0.
Bits 1–0
MOTOROLA
2
C Control Register Description (Continued)
Description
2
C bus is a
2
I C Module
Programming Model
Settings
0 = Slave mode (changing MSTA from 1 to 0
generates a STOP and selects slave
mode)
1 = Master mode (changing MSTA from 0 to 1
signals a START on the bus and selects
master mode)
0 = Receive
1 = Transmit
0 = Sends an acknowledge signal to the bus at
the ninth clock bit after receiving one byte
of data
1 = No acknowledge signal response is sent
(the data acknowledge bit in the
protocol = 1)
0 = No repeated START
1 = Generates a repeated START
29-11