Ssi Control/Status Register; Figure 30-13 Receive Data Path (Rxbit0 = 1, Rshfd = 1); Table 30-7 Ssi Control/Status Register Description - Motorola DragonBall MC9328MX1 Reference Manual

15 14 13 12 11 10 9
SRX
15 14 13 12 11 10 9
RXSR
The first bit shifted in depends on word length.
Arrowheads indicate the bit shifted in first in each case; all lower bits are then shifted in.
Bit 0 is always shifted in last.
Figure 30-13. Receive Data Path (RXBIT0 = 1, RSHFD = 1)

30.3.7 SSI Control/Status Register

The SSI Control/Status Register sets up and monitors the SSI. The SSI status bits are updated when the SSI
is enabled, and then after the transmission or reception of the first bit of the next SSI word is complete. The
Receive Overrun Error (ROE) and Transmitter Underrun Error (TUE) bits are cleared by reading this
register, followed by a read of the SRX register (to clear ROE), or a write to the STX register (to clear
TUE).
SCSR
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
SYS
_CLK I2S_MODE
_EN
TYPE rw rw rw
0 0 0
RESET
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
MOTOROLA
16-Bit Word
8
8
SSI Control/Status Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
SYN NET RE TE
rw rw rw rw
0 0 0 0
Table 30-7. SSI Control/Status Register Description
Description
Synchronous Serial Interface (SSI)
8-Bit Word
10-Bit Word
12-Bit Word
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
24 23 22 21
r r r r
0 0 0 0
0x0000
8 7 6 5
SSI_
RDR TDE ROE
EN
rw r r r
0 0 1 0
0x0041
Programming Model
SSI_RXDAT
Addr
0x00218008
20 19 18 17
r r r r
0 0 0 0
4 3 2 1
TUE TFS RFS RFF
r r r r
0 0 0 0
Settings
30-15
16
r
0
0
TFE
r
1