Channel Control Registers - Motorola DragonBall MC9328MX1 Reference Manual

DMA Controller
Table 13-16. Channel Count Registers Description (Continued)
Name
CNT Count—Contains the number of bytes of data to be transferred during a DMA cycle.
Bits 23–0

13.4.3.4 Channel Control Registers

Each of the channel control registers (CCRx) controls and displays the status of a DMA channel operation.
While any one of the eleven channels may be configured for 2D memory,
only one enabled channel may be configured for 2D memory at any time,
This constraint does not apply to configuring the DMA channels for linear
memory, FIFO, and end-of-burst enable FIFO.
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
CCR7
CCR8
CCR9
CCR10
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
DMOD
TYPE r r rw
0 0 0
RESET
13-22
NOTE:
Channel 0 Control Register
Channel 1 Control Register
Channel 2 Control Register
Channel 3 Control Register
Channel 4 Control Register
Channel 5 Control Register
Channel 6 Control Register
Channel 7 Control Register
Channel 8 Control Register
Channel 9 Control Register
Channel 10 Control Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
SMOD MDIR MSEL
rw rw rw rw
0 0 0 0
MC9328MX1 Reference Manual
Description
24 23 22 21
r r r r
0 0 0 0
0x0000
8 7 6 5
DSIZ SSIZ
rw rw rw rw
0 0 0 0
0x0000
Addr
0x0020908C
0x002090CC
0x0020910C
0x0020914C
0x0020918C
0x002091CC
0x0020920C
0x0020924C
0x0020928C
0x002092CC
0x0020930C
20 19 18 17 16
r r r r r
0 0 0 0 0
4 3 2 1 0
REN RPT FRC CEN
rw rw rw w rw
0 0 0 0 0
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