Peripheral Clock Divider Register; Table 12-6 Clock Sources For Peripherals; Table 12-7 Peripheral Clock Divider Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Phase-Locked Loop and Clock Controller

12.5.2 Peripheral Clock Divider Register

Each peripheral module in the MC9328MX1 uses clock signals from one of the three clock sources shown
in Table 12-6. The three peripheral clock dividers (PCLKDIV1, PCLKDIV2, PCLKDIV3) provide
flexible clock configuration capability so that a minimum set of clock frequencies can satisfy a large group
of modules to achieve better power efficiency.
PCDR
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Table 12-7. Peripheral Clock Divider Register Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–23
PCLK_DIV3 Peripheral Clock Divider 3—Contains the 7-bit integer divider that
Bits 22–16 produces the PERCLK3 clock signal for the peripherals. The input to
the PCLK_DIV3 divider circuit is System PLLCLK.
Reserved Reserved—These bits are reserved and should read 0.
Bits 15–8
PCLK_DIV2 Peripheral Clock Divider 2—Contains the 4-bit integer divider that
Bits 7–4 produces the PERCLK2 clock signal for the peripherals. The input to
the PCLK_DIV2 divider circuit is System PLLCLK.
12-8
Table 12-6. Clock Sources for Peripherals
Clock Source
PERCLK1 UART1, UART2, Timer1, Timer2, PWM
PERCLK2 ASP, LCD, SD, SIM, SPI 1, SPI 2
PERCLK3 SSI
HCLK SDRAM, CSI, Memory Stick, I
Peripheral Clock Divider Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
r r r r
0 0 0 0
Description
MC9328MX1 Reference Manual
Peripheral
2
C, DMA
24 23 22 21 20
r r rw rw rw
0 0 0 0 0
0x000B
8 7 6 5 4
PCLK_DIV2
r rw rw rw rw
0 1 0 1 1
0x00BB
Addr
0x0021B020
19 18 17 16
PCLK_DIV3
rw rw rw rw
1 0 1 1
3 2 1 0
PCLK_DIV1
rw rw rw rw
1 0 1 1
Settings
0000000 = Divide by 1
0000001 = Divide by 2
...
1111111 = Divide by 128
0000 = Divide by 1
0001 = Divide by 2
...
1111 = Divide by 16
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