Csi Interrupt Operation; Register Access When Csi Module Is Disabled; Programming Model; Table 31-4 Csi Module Register Memory Map - Motorola DragonBall MC9328MX1 Reference Manual

CMOS Sensor Interface Module
The RxFIFO full level is programmed by the RxFF_LEVEL bits in CSI Control Register 1. When the
32-word RxFIFO is full, any further data writes to the RxFIFO by the external CMOS sensors are ignored
and the RxFIFO overrun interrupt (when enabled) is generated. The RxFIFO and STATFIFO operate
identically.

31.4.2 CSI Interrupt Operation

The CSI provides a single interrupt to the interrupt controller. For interrupt pin assignments, see
Chapter 10, "Interrupt Controller (AITC)."

31.4.3 Register Access When CSI Module is Disabled

The EN and MCLKDIV [3:0] bits of CSI Control Register 1 should be written during CSI module disable
mode (EN bit = 0) only.
Setting the EN bit to causes all of the CSI module registers to initialize except for the EN and MCLKDIV
0
bits of CSI Control Register 1.
To initialize the CSI module registers for operation, perform the following steps:
• Set the EN bit of CSI Control Register 1 to
• Write values to other registers or other bits of CSI Control Register 1.
• Complete remaining user-specified procedures.

31.5 Programming Model

The CSI module includes five user-accessible 32-bit registers. Table 31-4 summarizes these registers and
their addresses.
31-4
Table 31-4. CSI Module Register Memory Map
Description
CSI Control Register 1
CSI Control Register 2
CSI Status Register 1
CSI Statistic FIFO Register 1
CSI RxFIFO Register 1
MC9328MX1 Reference Manual
.
1
Name Address
CSICR1 0x00224000
CSICR2 0x00224004
CSISR 0x00224008
CSISTATR 0x0022400C
CSIRXR 0x00224010
MOTOROLA