Active Matrix Panel Interface Signals; Figure 19-12 Horizontal Sync Pulse Timing In Passive Mode; Figure 19-13 Vertical Sync Pulse Timing Passive, Color, (Non-Tft) Mode - Motorola DragonBall MC9328MX1 Reference Manual

LCD Controller
19.3.9 8 bpp Mode Color STN Panel
VSYN
(last line)
Hwidth
HSYN
LSCLK
LD[15:0]
Figure 19-12. Horizontal Sync Pulse Timing in Passive Mode
FLM
LP
LSCLK
Figure 19-13. Vertical Sync Pulse Timing Passive, Color, (Non-TFT) Mode

19.3.9.1 Active Matrix Panel Interface Signals

Figure 19-14 shows the LCD interface timing for an active matrix color TFT panel. In this figure signals
are shown with negative polarity (FLMPOL=1, LPPOL=1, CLKPOL=0, OEPOL=1). In TFT mode, the
LSCLK is automatically inverted. The panel interface timing for active matrix panels is sometimes
referred to as a "digital CRT" and is controlled by the shift clock (LSCLK), horizontal sync pulse
(HSYNC, the LP pin in passive mode), vertical sync pulse (VSYNC, the FLM pin in passive mode), output
enable (OE, the ACD pin in passive mode), and line data (LD) signals. The sequence of events for active
matrix interface timing is:
1. LSCLK latches data into the panel on its negative edge (when positive polarity is selected).
In active mode, LSCLK runs continuously.
2. HSYNC causes the panel to start a new line.
3. VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC
pulse.
19-14
Hwait2+2
4
PASS_FRAME_WAIT
End of last line
MC9328MX1 Reference Manual
Hwait1
XMAX
Ts
YMAX
(lines)
Start of frame
Hwait2+2
)
(first line
Hwidth
MOTOROLA