Powerdown Timer; Dma Operation With The Sdram Controller; External Interface; Table 24-1 Ahb Bus And Internal Interface Signals - Motorola DragonBall MC9328MX1 Reference Manual

SDRAM Memory Controller

24.3.7 Powerdown Timer

The powerdown timer detects periods of inactivity to the SDRAM and disables the clock when the inactive
period surpasses the selected time-out. Data is retained during the powerdown state. Subsequent requests
to the SDRAM incur only a minimal added start-up delay (beyond the normal access time). The
powerdown timer may be programmed to expire anytime the controller is not actively reading or writing
the memory, after 64 or 128 clocks of inactivity, or may be disabled entirely.

24.3.8 DMA Operation with the SDRAM Controller

The DMA controller has the capability to perform burst reads of byte and half word data types and the
SDRAM controller support is restricted to burst reads of word (32-bit) data types. Therefore, when using
the DMA in conjunction with the SDRAM controller, ensure that all burst reads from the SDRAM
controller are of word data types. This is configured in the DMA Channel Control Register. When
choosing SDRAM memory as the source address, set the Source Size Bits as a 32-bit port. Refer to the
Chapter 13, "DMA Controller," for more details.

24.4 External Interface

This section discusses input and output signals between the SDRAM Controller and the external memory
devices. Other than the chip-select outputs (CSD0 / CSD1) and clock enables (SDCKE0 / SDCKE1), all
signals are shared between the two chip-select regions. The interface signals are summarized in Table 24-2
and detailed in Section 24.4.1 through Section 24.4.11. Interconnect and timing diagrams are included as
part of the detailed discussion on controller operation in Section 24.6, "Operating Modes."
All external interface signals are referenced to the SDRAM clock, SDCLK.
Name
clk32 32.0 kHz Clock Reference
sf_wack WMIMI bus time-out suppression for SyncFlash low-power mode
wake-up
DQ [31:0] Internal data I/O bus
SDRAMC
MC9328MX1
Signal
Pin Name
Name
SDCLK
SDCKE0 SDCLKE0
SDCKE1 SDCLKE1
CSD0
CSD1
MA [11:10] MA [11:10]
24-4
Table 24-1. AHB Bus and Internal Interface Signals
Function
Table 24-2. SDRAM Interface Pin Characteristics
SDCLK Clock to SDRAM
Clock enable to SDRAM 0
Clock enable to SDRAM 1
CS2 Chip-select to SDRAM array 0
CS3 Chip-select to SDRAM array 1
Multiplexed Address
MC9328MX1 Reference Manual
Function
Direction
Input
Output
I/O
Direction Reset State
Output Enabled
Output High
Output High
Output High
Output High
Output Low
MOTOROLA