Motorola DragonBall MC9328MX1 Reference Manual

Integrated portable system processor

page of 968

/ 968
Contents
Table of Contents
Bookmarks

Table of Contents

Quick Links

Download this manual

DragonBall MC9328MX1 Integrated

Portable System Processor

Reference Manual

MC9328MX1RM/D

Rev. 2, 02/2003

Table of Contents

Chapters

Table of Contents

Summary of Contents for Motorola DragonBall MC9328MX1

Page 1 DragonBall MC9328MX1 Integrated Portable System Processor Reference Manual MC9328MX1RM/D Rev. 2, 02/2003...
Page 2 Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. All other The Bluetooth product or service names are the property of their respective owners.
Page 3: Table Of Contents
Power Management Features ..........1-10 MOTOROLA...
Page 4 The ARM Thumb Instruction Set ......... . 4-8 MC9328MX1 Reference Manual MOTOROLA...
Page 5 System Boot Mode Selection ..........8-7 MOTOROLA...
Page 6 Interrupt Force Register High ........10-28 MC9328MX1 Reference Manual MOTOROLA...
Page 7 11.6.1.1 Chip Select 0 Upper Control Register ......11-11 MOTOROLA Contents...
Page 8 DMA Burst Time-Out Control Register ......13-15 viii MC9328MX1 Reference Manual MOTOROLA...
Page 9 Current-Mode Operation..........15-4 MOTOROLA...
Page 10 Payload Header Register......... 16-30 MC9328MX1 Reference Manual MOTOROLA...
Page 11 Clock Control Register ......... . 16-72 MOTOROLA...
Page 12 MMA MAC Bit Select Register ........17-14 MC9328MX1 Reference Manual MOTOROLA...
Page 13 Soft Reset Registers ..........18-15 MOTOROLA...
Page 14 Eight Bits/Pixel Active Matrix Color Mode ......19-39 19.4.17.7 Twelve Bits/Pixel and Sixteen Bits/Pixel Active Matrix Color Mode ..19-39 MC9328MX1 Reference Manual MOTOROLA...
Page 15 Card Access ........... . . 20-37 20.7.3.1 Block Access—Block Write and Block Read ......20-37 MOTOROLA Contents...
Page 16 Data FIFO Operation ..........21-4 MC9328MX1 Reference Manual MOTOROLA...
Page 17 22.3.3 Digital-to-Analog Converter (D/A) Mode ....... 22-3 MOTOROLA Contents xvii...
Page 18 MA [11:0]—Multiplexed Address Bus ....... . . 24-6 24.4.6 SDBA [4:0], SDIBA [3:0]—Non-Multiplexed Address Bus ....24-6 xviii MC9328MX1 Reference Manual MOTOROLA...
Page 19 SDRAM Memory Refresh ......... . 24-65 MOTOROLA...
Page 20 SmartCard Presence Detect ......... 25-15 MC9328MX1 Reference Manual MOTOROLA...
Page 21 Programming Considerations ........25-52 MOTOROLA...
Page 22 Baud Rate Automatic Detection Logic ....... . . 27-16 xxii MC9328MX1 Reference Manual MOTOROLA...
Page 23 USB Enable Register ..........28-18 MOTOROLA...
Page 24 RESET_START—Start of USB Reset Signaling..... . 28-44 28.8.1.5 WAKEUP—Resume (Wake-Up) Signaling Detected ....28-45 xxiv MC9328MX1 Reference Manual MOTOROLA...
Page 25 Generation of Repeated START........29-16 MOTOROLA...
Page 26 SSI Reset and Initialization Procedure ........30-44 xxvi MC9328MX1 Reference Manual MOTOROLA...
Page 27 Input Configuration Register A1 ........32-12 MOTOROLA...
Page 28 Pull_Up Enable Registers ......... . . 32-25 xxviii MC9328MX1 Reference Manual MOTOROLA...
Page 29 MMA Data Access ..........17-2 MOTOROLA...
Page 30 MSHC Module Serial Clock Divider ....... 21-11 MC9328MX1 Reference Manual MOTOROLA...
Page 31 Figure 24-27 Hardware Refresh Timing Diagram ....... . 24-32 MOTOROLA...
Page 32 Receive State Machine Diagram........25-11 xxxii MC9328MX1 Reference Manual MOTOROLA...
Page 33 Figure 30-16 Serial Clock and Frame Sync Timing....... 30-37 MOTOROLA...
Page 34 Top Level of Circuitry for Port X, Pin [i]......32-2 Figure 32-2 GPIO Module Block Diagram for Port X, Pin [i]..... . . 32-4 xxxiv MC9328MX1 Reference Manual MOTOROLA...
Page 35 Silicon ID Register Description ........8-2 MOTOROLA...
Page 36 Fast Interrupt Pending Register Low Description ..... 10-33 Table 10-30 Typical Hardware Accelerated Normal Interrupt Entry Sequence ..10-35 xxxvi MC9328MX1 Reference Manual MOTOROLA...
Page 37 Channel Control Registers Description ......13-23 Table 13-18 DMA_EOBO_CNT and DMA_EOBI_CNT Settings ....13-24 MOTOROLA List of Tables xxxvii...
Page 38 Native Count Register Description ....... . . 16-31 xxxviii MC9328MX1 Reference Manual MOTOROLA...
Page 39 Table 16-55 Wake-Up Status Register Description ......16-70 MOTOROLA List of Tables...
Page 40 MMA MAC Bit Select Register Description ......17-15 Table 17-12 MMA MAC X Base Address Register Description ....17-16 MC9328MX1 Reference Manual MOTOROLA...
Page 41 Display Mapping in 12 bpp, CSTN Panel, Little Endian ....19-6 Table 19-4 Display Mapping in 12 bpp, CSTN Panel, Big Endian ....19-7 MOTOROLA List of Tables...
Page 42 MMC/SD Revision Number Register Description ..... 20-25 Table 20-14 MMC/SD Interrupt Mask Register Description ..... . . 20-26 xlii MC9328MX1 Reference Manual MOTOROLA...
Page 43 Read Packet........... 21-27 MOTOROLA...
Page 44 Single 8M x 16 Control Register Values ......24-41 xliv MC9328MX1 Reference Manual MOTOROLA...
Page 45 SIM Interrupts..........25-18 MOTOROLA...
Page 46 Table 27-5 DTR Edge Triggered Interrupt Truth Table ......27-7 xlvi MC9328MX1 Reference Manual MOTOROLA...
Page 47 Device Request Status ......... . 28-12 MOTOROLA...
Page 48 Clock Pin Configuration ......... 30-26 xlviii MC9328MX1 Reference Manual MOTOROLA...
Page 49 Interrupt Mask Register Description....... . 32-21 MOTOROLA List of Tables...
Page 50 Pull_Up Enable Register Description ....... 32-25 MC9328MX1 Reference Manual MOTOROLA...
Page 51: About This Book
ID register, and I/O drive control registers. Bootstrap Mode Operation: The operation of bootstrap models is described in Chapter 9 detail in this chapter. This chapter describes programming information necessary MOTOROLA About This Book...
Page 52 MMC, its operation and programming information. Memory Stick Host Controller (MSHC): This chapter describes how data is Chapter 21 transferred to a Memory Stick device. It also discusses how to configure and program the Memory Stick Host Controller. MC9328MX1 Reference Manual MOTOROLA...
Page 53 GPIO and I/O Multiplexer (IOMUX): This chapter covers all GPIO lines Chapter 32 found in the MC9328MX1. Because each pin is individually configurable, a detailed description of the operation is provided. MOTOROLA About This Book liii...
Page 54: Document Revision History
MC68SZ328 Product Brief (order number MC68SZ328P/D) MC68SZ328 User’s Manual (order number MC68SZ328UM/D) The manuals may be found at the Motorola Semiconductors World Wide Web site at http://www.motorola.com/semiconductors. These documents may be downloaded directly from the World Wide Web site, or printed versions may be ordered. The World Wide Web site also may have useful application notes.
Page 55 DRAM dynamic random access memory digital signal processor EDO RAM extended data out DRAM forward error correction FIFO first in first out GPIO general purpose input/output inquiry access code: A predefined Bluetooth ID input/output in-circuit emulation MOTOROLA About This Book...
Page 56 SDRAM synchronous dynamic random access memory serial peripheral interface SRAM static random access memory TQFP thin quad flat pack UART universal asynchronous receiver/transmitter universal serial bus XTAL crystal MC9328MX1 Reference Manual MOTOROLA...
Page 57: Block Diagram
Chapter 1 Introduction Motorola’s DragonBall family of microprocessors has demonstrated leadership in the portable handheld market. Continuing this legacy, the DragonBall MX (Media Extensions) series provides a leap in performance with an ARM9™ microprocessor core and highly integrated system functions. DragonBall MX products specifically address the requirements of the personal, portable product market by providing intelligent integrated peripherals, an advanced processor core, and power management capabilities.
Page 58: Features
Two General-Purpose 32-bit Counters/Timers • Watchdog Timer • Real-Time Clock/Sampling Timer (RTC) • LCD Controller (LCDC) • Pulse-Width Modulation (PWM) Module • Universal Serial Bus (USB) Device • Multimedia Card and Secure Digital (MMC/SD) Host Controller MC9328MX1 Reference Manual MOTOROLA...
Page 59: Arm920T Microprocessor Core
Cache locking to support mixed loads of real-time and user applications • Virtual Memory Management Unit (VMMU) 1.4 AHB to IP Bus Interfaces (AIPIs) The MC9328MX1 AIPIs provide a communication interface between the high-speed AHB bus and a lower-speed IP bus for slow slave peripherals. MOTOROLA Introduction...
Page 60: External Interface Module (Eim)
• Auto-powerdown (clock suspend) timer 1.7 Clock Generation Module (CGM) and Power Control Module The MC9328MX1 CGM and Power Control Module features: • Digital phase-locked loops (PLLs) and clock controller for all internal clocks generation MC9328MX1 Reference Manual MOTOROLA...
Page 61: Two Serial Peripheral Interfaces (Spi)
Programmable timer input/output pins • Input capture capability with programmable trigger edge • Output compare with programmable mode 1.11 Watchdog Timer The MC9328MX1 Watchdog Timer features: • Programmable time out of 0.5 s to 64 s • Resolution of 0.5 s MOTOROLA Introduction...
Page 62: Real-Time Clock/Sampling Timer (Rtc)
In BW mode, the maximum bit depth is 4 bpp • Up to 16 grey levels out of 16 palettes • Capable of directly driving popular LCD drivers from manufacturers including Motorola, Sharp, Hitachi, and Toshiba • Support for data bus width for 12- or 16-bit TFT panels •...
Page 63: Universal Serial Bus (Usb) Device
Up to ten MMC cards and one SD are supported by standard (maximum data rate with a maximum of ten cards) • Support for hot swappable operation • Support for data rates from 20 Mbps to 80 Mbps MOTOROLA Introduction...
Page 64: Memory Stick® Host Controller (Mshc)
Bulk data transfer complete or transfer error interrupts provided to interrupt handler (and then to the core) • DMA burst time-out error terminates the DMA cycle when the burst cannot be completed within a programmed timing period • Acknowledge signal provided to peripheral after DMA burst is complete MC9328MX1 Reference Manual MOTOROLA...
Page 65: Synchronous Serial Interface And Inter-Ic Sound (Ssi/I 2 S) Module
Allows user to initialize system and download program or data to system memory through UART • Accepts execution command to run program stored in system memory • Supports memory/register read/write operation of selectable data size of byte, half-word, or word MOTOROLA Introduction...
Page 66: Analog Signal Processing (Asp) Module
• 32-word (16-bit) Rx and Tx buffer Programmable RF controller supports three front ends (including SPI / µWire controller) • • Support for external transceiver ICs from manufacturers such as Motorola (MC13180) and Silicon Wave™ • Bluetooth application timer •...
Page 67: Operating Voltage Range
1.30 Packaging The MC9328MX1 features two packages: • 256-pin MAPBGA package with 14 mm × 14 mm × 1.3 mm, 0.8 mm ball pitch • 225-pin PBGA package with 13 mm × 13 mm, 0.8 mm ball pitch MOTOROLA Introduction 1-11...
Page 68 Introduction 1-12 MC9328MX1 Reference Manual MOTOROLA...
Page 69: Table 2-1 Mc9328Mx1 Signal Descriptions
Clock signal sent to external synchronous memories (such as burst flash) during burst mode. RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input signal by external DRAM. MOTOROLA Signal Descriptions and Pin Assignments...
Page 70 Clocks and Resets EXTAL16M Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when internal oscillator circuit is shut down. XTAL16M Crystal output EXTAL32K 32 kHz crystal input XTAL32K 32 kHz crystal output MC9328MX1 Reference Manual MOTOROLA...
Page 71 ETM packet signals which are multiplex with ECB, LBA, BCLK, PA17, A [19:16]. ETMTRACEPKT [7:0] are selected in ETM mode. CMOS Sensor Interface CSI_D [7:0] Sensor port data CSI_MCLK Sensor port master clock CSI_VSYNC Sensor port vertical sync MOTOROLA Signal Descriptions and Pin Assignments...
Page 72 SIM_RX Receive Data SIM_TX Transmit Data SIM_PD Presence Detect Schmitt trigger input SIM_SVEN SIM Vdd Enable SPI1_MOSI Master Out/Slave In SPI1_MISO Slave In/Master Out SPI1_SS Slave Select (Selectable polarity) SPI1_SCLK Serial Clock SPI1_SPI_RDY Serial Data Ready MC9328MX1 Reference Manual MOTOROLA...
Page 73 SD_CMD SD Command—If the system designer does not want to make use of the internal pull-up, via the Pull-up enable register, a 4.7K–69K external pull up resistor must be added. SD_CLK MMC Output Clock MOTOROLA Signal Descriptions and Pin Assignments...
Page 74 Ring Indicator UART2_DCD Data Carrier Detect UART2_DTR Data Terminal Ready Serial Audio Port – SSI (configurable to I2S protocol) SSI_TXDAT SSI_RXDAT SSI_TXCLK Transmit Serial Clock SSI_RXCLK Receive Serial Clock SSI_TXFS Transmit Frame Sync SSI_RXFS Receive Frame Sync MC9328MX1 Reference Manual MOTOROLA...
Page 75 Negative resistance input (a) Negative resistance input (b) Positive reference for pen ADC Negative reference for pen ADC AVDD Analog power supply AGND Analog ground BlueTooth I/O clock signal Output Input Input Output Output Output MOTOROLA Signal Descriptions and Pin Assignments...
Page 76: I/O Pads Power Supply And Signal Multiplexing Scheme
(memory and external peripherals). The function multiplexing information also shown in Table 2-2 allows the user to select the function of each pin by configuring the appropriate GPIO registers when those pins are multiplexed to provide different functions. MC9328MX1 Reference Manual MOTOROLA...
Page 77: Table 2-2 Mc9328Mx1 Signal Multiplexing Scheme
ETMPIPESTAT0 PA28 NVDD1 NVDD1 ETMTRACEPKT3 PA27 NVDD1 Static NVDD1 NVDD1 Static NVDD1 ETMTRACEPKT2 PA26 NVDD1 NVDD1 ETMTRACEPKT1 PA25 NVDD1 NVDD1 ETMTRACEPKT0 PA24 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 Static QVDD1 QVDD1 Static Static MOTOROLA Signal Descriptions and Pin Assignments...
Page 78 NVDD1 Static NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 Static NVDD1 NVDD1 Static NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 Static NVDD1 NVDD1 Static NVDD1 2-10 MC9328MX1 Reference Manual MOTOROLA...
Page 79 SDCLK NVDD1 NVDD1 NVDD1 NVDD1 ETMTRACEPKT7 PA20 NVDD1 NVDD1 ETMTRACEPKT6 PA19 NVDD1 NVDD1 BCLK ETMTRACEPKT5 PA18 BCLK NVDD1 Static NVDD1 NVDD1 Static NVDD1 PA17 ETMTRACEPKT4 PA17 PA17 NVDD1 NVDD1 NVDD1 MA11 NVDD1 MA10 MOTOROLA Signal Descriptions and Pin Assignments 2-11...
Page 80 NVDD1 RESET_SF NVDD1 CLKO Static AVDD1 AVDD1 Static AVDD1 RESET_IN AVDD1 RESET_OUT AVDD1 AVDD1 BIG_ENDIAN AVDD1 BOOT3 AVDD1 BOOT2 AVDD1 BOOT1 AVDD1 BOOT0 AVDD1 TRISTATE AVDD1 TRST QVDD2 QVDD2 Static Static AVDD1 EXTAL16M AVDD1 XTAL16M 2-12 MC9328MX1 Reference Manual MOTOROLA...
Page 81 CSI_D2 NVDD2 CSI_D1 NVDD2 CSI_D0 NVDD2 CSI_MCLK NVDD2 PWMO NVDD2 NVDD2 TMR2OUT PD31 PD31 NVDD2 LD15 PD30 PD30 NVDD2 LD14 PD29 PD29 NVDD2 LD13 PD28 PD28 NVDD2 LD12 PD27 PD27 QVDD3 QVDD3 Static MOTOROLA Signal Descriptions and Pin Assignments 2-13...
Page 82 FLM/VSYNC PD14 PD14 NVDD2 LP/HSYNC PD13 PD13 NVDD2 ACD/OE PD12 PD12 NVDD2 CONTRAST PD11 PD11 NVDD2 SPL_SPR UART2_DSR PD10 PD10 NVDD2 UART2_RI NVDD2 UART2_DCD NVDD2 UART2_DTR NVDD2 LSCLK Static AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 2-14 MC9328MX1 Reference Manual MOTOROLA...
Page 83 PC31 BTRFVDD PC30 PC30 BTRFVDD PC29 PC29 BTRFVDD PC28 PC28 BTRFVDD PC27 PC27 BTRFVDD PC26 PC26 BTRFVDD PC25 PC25 BTRFVDD PC24 PC24 BTRFVDD PC23 PC23 BTRFVDD BT10 PC22 PC22 BTRFVDD BT11 PC21 PC21 MOTOROLA Signal Descriptions and Pin Assignments 2-15...
Page 84 UART2_TXD PB30 PB30 NVDD4 UART2_RTS PB29 PB29 NVDD4 UART2_CTS PB28 PB28 NVDD4 USBD_VMO PB27 PB27 NVDD4 USBD_VPO PB26 PB26 NVDD4 USBD_VM PB25 PB25 NVDD4 USBD_VP PB24 PB24 NVDD4 USBD_SUSPND PB23 PB23 NVDD4 USBD_RCV PB22 PB22 2-16 MC9328MX1 Reference Manual MOTOROLA...
Page 85 NVDD4 SIM_SVEN SSI_RXFS PB14 PB14 NVDD4 SD_CMD MS_BS PB13 PB13 NVDD4 SD_SCLK MS_SCLKO PB12 PB12 NVDD4 SD_DAT3 MS_SDIO PB11 PB11 (pull down) NVDD4 SD_DAT2 MS_SCLKI PB10 PB10 NVDD4 SD_DAT1 MS_PI1 NVDD4 SD_DAT0 MP_PI0 MOTOROLA Signal Descriptions and Pin Assignments 2-17...
Page 86 Signal Descriptions and Pin Assignments 2-18 MC9328MX1 Reference Manual MOTOROLA...
Page 87: Memory Space
Figure 3-1 on page 3-2. 3.1.1 Memory Map The base address referred to in each peripheral register address is the address from this table. The exact address description of each of the peripherals is described in each peripheral section. MOTOROLA Memory Map...
Page 88: Figure 3-1 Mc9328Mx1 Mcu Physical Memory Map (4 Gbyte)
16 MB $0021 E000 $5000 1000 $1600 0000 1020 KB 4 KB Reserved $0021 EFFF Reserved (Spare) $0021 F000 Reserved active low $0021 FFFF $FFFF FFFF $16FF FFFF Figure 3-1. MC9328MX1 MCU Physical Memory Map (4 Gbyte) MC9328MX1 Reference Manual MOTOROLA...
Page 89: Table 3-1 Mcu Memory Space (Physical Addresses)
$0021 6000 - $0021 6FFF 4 kbyte $0021 7000 - $0021 7FFF 4 kbyte $0021 8000 - $0021 8FFF 4 kbyte $0021 9000 - $0021 9FFF SPI 2 4 kbyte $0021 A000 - $0021 AFFF MSHC 4 kbyte MOTOROLA Memory Map...
Page 90 $1600 0000 - $16FF FFFF External Memory (CS5) 16 Mbyte $1700 0000 - $4FFF FFFF Reserved 912 Mbyte $5000 0000 - $5000 0FFF ARM920T Test Registers 4 kbyte $5000 1000 - $FFFF FFFF Reserved 2815 Mbyte + 1020 kbyte MC9328MX1 Reference Manual MOTOROLA...
Page 91: On-Chip Mcu Memory
SyncFlash, CS0, or Bootstrap ROM. After system power up, reading or writing to the double map space ($0000,0000 to $000F,FFFF) is the same as reading or writing to the first 1 Mbyte of the selected boot ROM which is controlled by the configuration of BOOT [3:0] input pins. MOTOROLA Memory Map...
Page 92: Internal Registers
SECONDS RTC Seconds Counter Register 0x00204008 ALRM_HM RTC Hours and Minutes Alarm Register 0x0020400C ALRM_SEC RTC Seconds Alarm Register 0x00204010 RCCTL RTC Control Register 0x00204014 RTCISR RTC Interrupt Status Register 0x00204018 RTCIENR RTC Interrupt Enable Register MC9328MX1 Reference Manual MOTOROLA...
Page 93 URX5D_1 UART1 Receiver Register 5 UART 1 0x00206018 URX6D_1 UART1 Receiver Register 6 UART 1 0x0020601C URX7D_1 UART1 Receiver Register 7 UART 1 0x00206020 URX8D_1 UART1 Receiver Register 8 UART 1 0x00206024 URX9D_1 UART1 Receiver Register 9 MOTOROLA Memory Map...
Page 94 UART1 Control Register 3 UART 1 0x0020608C UCR4_1 UART1 Control Register 4 UART 1 0x00206090 UFCR_1 UART1 FIFO Control Register UART 1 0x00206094 USR1_1 UART1 Status Register 1 UART 1 0x00206098 USR2_1 UART1 Status Register 2 MC9328MX1 Reference Manual MOTOROLA...
Page 95 URX10D_2 UART2 Receiver Register 10 UART 2 0x0020702C URX11D_2 UART2 Receiver Register 11 UART 2 0x00207030 URX12D_2 UART2 Receiver Register 12 UART 2 0x00207034 URX13D_2 UART2 Receiver Register 13 UART 2 0x00207038 URX14D_2 UART2 Receiver Register 14 MOTOROLA Memory Map...
Page 96 UART2 Escape Character Register UART 2 0x002070A0 UTIM_2 UART2 Escape Timer Register UART 2 0x002070A4 UBIR_2 UART2 BRM Incremental Register UART 2 0x002070A8 UBMR_2 UART2 BRM Modulator Register UART 2 0x002070AC UBRC_2 UART2 Baud Rate Count Register 3-10 MC9328MX1 Reference Manual MOTOROLA...
Page 97 Y-Size Register A DMAC 0x0020904C WSRB W-Size Register B DMAC 0x00209050 XSRB X-Size Register B DMAC 0x00209054 YSRB Y-Size Register B DMAC 0x00209080 SAR0 Channel 0 Source Address Register DMAC 0x00209084 DAR0 Channel 0 Destination Address Register MOTOROLA Memory Map 3-11...
Page 98 Channel 3 Request Source Select Register DMAC 0x00209154 BLR3 Channel 3 Burst Length Register DMAC 0x00209158 RTOR3 Channel 3 Request Time-Out Register BUCR3 Channel 3 Bus Utilization Control Register DMAC 0x00209180 SAR4 Channel 4 Source Address Register 3-12 MC9328MX1 Reference Manual MOTOROLA...
Page 99 Channel 7 Control Register DMAC 0x00209250 RSSR7 Channel 7 Request Source Select Register DMAC 0x00209254 BLR7 Channel 7 Burst Length Register DMAC 0x00209258 RTOR7 Channel 7 Request Time-Out Register BUCR7 Channel 7 Bus Utilization Control Register MOTOROLA Memory Map 3-13...
Page 100 PSR1_2 AIPI2 Peripheral Size Register 1 AIPI2 0x00210008 PAR_2 AIPI2 Peripheral Access Register AIPI2 0x0021000C PCR_2 AIPI2 Peripheral Control Register AIPI2 0x00210010 TSR_2 AIPI2Time-Out Status Register 0x00211000 PORT_CNTL Port Control Register 0x00211004 CNTL Control Register 3-14 MC9328MX1 Reference Manual MOTOROLA...
Page 101 0x00212024 USB_ENAB USB Enable Register USBD 0x00212030 USB_EP0_STAT Endpoint 0 Status/Control Register USBD 0x00212034 USB_EP0_INTR Endpoint 0 Interrupt Status Register USBD 0x00212038 USB_EP0_MASK Endpoint 0 Interrupt Mask Register USBD 0x0021203C USB_EP0_FDAT Endpoint 0 FIFO Data Register MOTOROLA Memory Map 3-15...
Page 102 0x002120AC USB_EP2_LWFP Endpoint 2 Last Write Frame Pointer Register USBD 0x002120B0 USB_EP2_FALRM Endpoint 2 FIFO Alarm Register USBD 0x002120B4 USB_EP2_FRDP Endpoint 2 FIFO Read Pointer Register USBD 0x002120B8 USB_EP2_FWRP Endpoint 2 FIFO Write Pointer Register 3-16 MC9328MX1 Reference Manual MOTOROLA...
Page 103 Endpoint 5 Interrupt Mask Register USBD 0x0021212C USB_EP5_FDAT Endpoint 5 FIFO Data Register USBD 0x00212130 USB_EP5_FSTAT Endpoint 5 FIFO Status Register USBD 0x00212134 USB_EP5_FCTRL Endpoint 5 FIFO Control Register USBD 0x00212138 USB_EP5_LRFP Endpoint 5 Last Read Frame Pointer Register MOTOROLA Memory Map 3-17...
Page 104 MMC/SD Higher Argument Register MMC/SDHC 0x00214030 ARGL MMC/SD Lower Argument Register MMC/SDHC 0x00214034 RES_FIFO MMC/SD Response FIFO Register MMC/SDHC 0x00214038 BUFFER_ACCESS MMC/SD Buffer Access Register 0x00215000 ASP_PADFIFO Pen Sample FIFO 0x00215004 ASP_VADFIFO Voice ADC Register 3-18 MC9328MX1 Reference Manual MOTOROLA...
Page 105 Offset Clock High Register 0x00216030 HECCRC_CONTROL HECCRC Control Register 0x00216034 WHITE_CONTROL White Control Register 0x00216038 ENCRYPTION_CONTROL_X13 Encryption Control X13 Register 0x00216040 CORRELATION_TIME_SETUP Correlation Time Setup Register CORRELATION_TIME_STAMP Correlation Time Stamp Register 0x00216048 RF_GPO RF GPO Register MOTOROLA Memory Map 3-19...
Page 106 Buf Word 10 (LW0) Register 0x002160AC BUF_WORD_11 (LW0) Buf Word 11 (LW0) Register 0x002160B0 BUF_WORD_12 (LW0) Buf Word 12 (LW0) Register 0x002160B4 BUF_WORD_13 (LW0) Buf Word 13 (LW0) Register 0x002160B8 BUF_WORD_14 (LW0) Buf Word 14 (LW0) Register 3-20 MC9328MX1 Reference Manual MOTOROLA...
Page 107 0x00216114 WU_COUNT WakeUp Count Register 0x00216118 CLK_CONTROL Clock Control Register 0x00216120 SPI_WORD0 SPI Word0 Register 0x00216124 SPI_WORD1 SPI Word1 Register 0x00216128 SPI_WORD2 SPI Word2 Register 0x0021612C SPI_WORD3 SPI Word3 Register 0x00216130 SPI_WRITE_ADDR SPI Write Address Register MOTOROLA Memory Map 3-21...
Page 108 SSI Transmit Clock Control Register 0x00218018 SRCCR SSI Receive Clock Control Register 0x0021801C STSR SSI Time Slot Register 0x00218020 SFCSR SSI FIFO Control/Status Register 0x00218028 SSI Option Register SPI 2 0x00219000 RXDATAREG2 SPI 2 Rx Data Register 3-22 MC9328MX1 Reference Manual MOTOROLA...
Page 109 System PLL Control Register 1 PLLCLK 0x0021B020 PCDR Peripheral Clock Divider Register RESET 0x0021B800 Reset Source Register SYS CTRL 0x0021B804 SIDR Silicon ID Register SYS CTRL 0x0021B808 FMCR Function Multiplexing Control Register SYS CTRL 0x0021B80C GPCR Global Peripheral Control Register MOTOROLA Memory Map 3-23...
Page 110 Port B GPIO In Use Register GPIO B 0x0021C124 SSR_B Port B Sample Status Register GPIO B 0x0021C128 ICR1_B Port B Interrupt Configuration Register 1 GPIO B 0x0021C12C ICR2_B Port B Interrupt Configuration Register 2 3-24 MC9328MX1 Reference Manual MOTOROLA...
Page 111 Port D Input Configuration Register A1 GPIO D 0x0021C310 ICONFA2_D Port D Input Configuration Register A2 GPIO D 0x0021C314 ICONFB1_D Port D Input Configuration Register B1 GPIO D 0x0021C318 ICONFB2_D Port D Input Configuration Register B2 MOTOROLA Memory Map 3-25...
Page 112 SDCTL0 SDRAM 0 Control Register SDRAMC 0x00221004 SDCTL1 SDRAM 1 Control Register SDRAMC 0x00221014 MISCELLANEOUS Miscellaneous Register SDRAMC 0x00221018 SDRST SDRAM Reset Register 0x00222000 MMA_MAC_MOD MMA MAC Module Register 0x00222004 MMA_MAC_CTRL MMA MAC Control Register 3-26 MC9328MX1 Reference Manual MOTOROLA...
Page 113 DCT/iDCT IRQ Enable Register 0x0022240C MMA_DCTIRQSTAT DCT/iDCT IRQ Status Register 0x00222410 DSA_DCTSRCDATA DCT/iDCT Source Data Address 0x00222414 MMA_DCTDESDATA DCT/iDCT Destination Data Address 0x00222418 MMA_DCTXOFF DCT/iDCT X-Offset Address 0x0022241C MMA_DCTYOFF DCT/iDCT Y-Offset Address 0x00222420 MMA_DCTXYCNT DCT/iDCT XY Count MOTOROLA Memory Map 3-27...
Page 114 Interrupt Force Register Low AITC 0x00223058 NIPNDH Normal Interrupt Pending Register High AITC 0x0022305C NIPNDL Normal Interrupt Pending Register Low AITC 0x00223060 FIPNDH Fast Interrupt Pending Register High AITC 0x00223064 FIPNDL Fast Interrupt Pending Register Low 3-28 MC9328MX1 Reference Manual MOTOROLA...
Page 115 Module Name Address Name Description 0x00224000 CSICR1 CSI Control Register 1 0x00224004 CSICR2 CSI Control Register 2 0x00224008 CSISR CSI Status Register 1 0x0022400C CSISTATR CSI Statistic FIFO Register 1 0x00224010 CSIRXR CSI RxFIFO Register 1 MOTOROLA Memory Map 3-29...
Page 116 Memory Map 3-30 MC9328MX1 Reference Manual MOTOROLA...
Page 117: Introduction
ARM920T processor is 100% user code binary compatible with ARM7TDMI , and backwards ® compatible with the ARM7™ Thumb® Family and the StrongARM processor families, giving designers software-compatible processors with a range of price/performance points from 60 MIPS to 200+ MIPS. MOTOROLA ARM920T Processor...
Page 118: Arm920T Macrocell
A 32-bit data bus connects each cache to the ARM9TDMI core allowing a 32-bit instruction to be fetched and fed into the instruction Decode stage of the pipeline at the same time as a 32-bit data access for the Memory stage of the pipeline. MC9328MX1 Reference Manual MOTOROLA...
Page 119: Cache Lock-Down
The physical address of all the lines held in the data cache is stored by the PATAG memory, removing the need for address translation when evicting a line from the cache. MOTOROLA ARM920T Processor...
Page 120: Control Coprocessor (Cp15)
All other processor states are held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds: • Four ALU flags (Negative, Zero, Carry, and Overflow) • Two interrupt disable bits (one for each type of interrupt) MC9328MX1 Reference Manual MOTOROLA...
Page 121: Exception Types
Four types of shift can be specified. Most data processing instructions can perform a shift followed by a logical or arithmetic operation. Multiply instructions come in two classes: • Normal, 32-bit result • Long, 32-bit result variants. Both types of multiply instruction can optionally perform an accumulate operation. MOTOROLA ARM920T Processor...
Page 122: Load And Store Instructions
There is a Branch with Link (BL) that allows efficient subroutine calls. BL preserves the address of the instruction after the branch in R14 (the Link Register, or LR). This allows a move instruction to put the LR in to the PC and return to the instruction after the branch. MC9328MX1 Reference Manual MOTOROLA...
Page 123: Coprocessor Instructions
Accumulate UMULL Unsigned Long Multiply UMLAL Unsigned Long Multiply Accumulate Count Leading Zeroes BKPT Breakpoint Move From Status Register Move to Status Register Branch Branch and Link Branch and Link and Exchange Branch and Exchange Software Interrupt MOTOROLA ARM920T Processor...
Page 124: The Arm Thumb Instruction Set
Logical Exclusive OR Logical (inclusive) OR Logical Shift Left Logical Shift Right Arithmetic Shift Right Rotate Right Multiply BKPT Breakpoint Unconditional Branch Conditional Branch Branch and Link Branch and Link and Exchange Branch and Exchange Software Interrupt MC9328MX1 Reference Manual MOTOROLA...
Page 125: Arm920T Modes And Registers
Interrupt Mode System Modes Mode Mode Mode R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ CPSR CPSR CPSR CPSR CPSR CPSR SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ = Mode-specific banked registers MOTOROLA ARM920T Processor...
Page 126 ARM920T Processor 4-10 MC9328MX1 Reference Manual MOTOROLA...
Page 127: Introduction To The Etm
ARM7™ processor and ETM7, refer to the ETM7 Technical Reference Manual Rev.1 (ARM Limited: 2001, order number DDI0158D). The block diagram of the ETM is shown in Figure 5-1. Figure 5-1. ETM Block Diagram MOTOROLA Embedded Trace Macrocell (ETM)
Page 128: Programming And Reading Etm Registers
2. Set bits [20:17] of Port A General Purpose Register (GPR_A) ETMTRACEPKT Alternate function of 1. Clear bits [27:24] of Port A GPIO In Use Register (GIUS_A) [3:0] GPIO Port A [27:24] 2. Set bits [27:24] of Port A General Purpose Register (GPR_A) MC9328MX1 Reference Manual MOTOROLA...
Page 129: Functional Description Of The Reset Module
See Table 6-1 for reset module signal and pin definitions. There is one source capable of generating a global reset: A high condition on the POR pin for at least × 32 kHz clocks when the 32 kHz crystal oscillator is running. MOTOROLA Reset Module...
Page 130: Arm920T Processor Reset
ROM, sync flash, or CS0 space. The memory location of the fetch depends on the configuration of the BOOT pins and the value of the TEST pin on the rising edge of HRESET (see Section 8.2, “System Boot Mode Selection,” on page 8-7). MC9328MX1 Reference Manual MOTOROLA...
Page 131: Programming Model
RESET_OUT signal), only the highest-priority event is registered by the RSR using the following priority order: 1. POR signal 2. Qualified external reset signal 3. Watchdog signal Otherwise, the last signal that is released is honored. MOTOROLA Reset Module...
Page 132: Table 6-2 Rsr Register Description
0 = Reset was NOT a RESET_IN pin assertion Bit 0 reset was caused by a RESET_IN pin 1 = Reset WAS a RESET_IN pin assertion assertion. Table 6-3. Hardware Reset Source Matrix Source Qualified external reset Watchdog time-out MC9328MX1 Reference Manual MOTOROLA...
Page 133: Overview
IP bus peripherals. The AIPI captures read data (qualified by IPS_XFR_WAIT) from the IP bus interface and drives it on the R-AHB. The AIPI module terminates the transfer by asserting AIPI_HREADY_OUT. MOTOROLA AHB to IP Bus Interface (AIPI)
Page 134: Figure 7-1 Aipi Interface
AHB for the write operation. haddr[16:0] HWDATA[31:0] IPS_WDATA[31:0] HWDATA[31:0] IPS_RDATA[15:1][31: AIPI_HRDATA[31:0] IPS_MODULE_EN[15: HPROTL IPS_ADDR1[11:1] HTRANSL IPS_BYTE_7_0 HWRITE IPS_BYTE_15_8 HSIZE[1:0] AIPI IPS_BYTE_23_16 HREADY_IN IPS_BYTE_31_24 AIPI_HRESP[1:0] IPS_RWB AIPI_HREADY_OUT IPS_XFR_WAIT[15:1] HCLK IPS_XFR_ERR[15:1] HCLK IPS_SUPERVISOR_A HSEL_AIPI IPS_GATED_CLK_EN[1 HRESET BIGEND_IN Figure 7-1. AIPI Interface MC9328MX1 Reference Manual MOTOROLA...
Page 135: Figure 7-2 Block Diagram Of The Aipi Module
IP bus_peripheral_size aipi_timeout ips_xfr_wait ips_xfr_err ips_rdata[31:0] aipi_start_transfer aipi_watchdog ips_rdata[15:1][31:0] aipi_data_mux aipi_xfr_mux aipi_ip_decode mux_select [3:0] ips_xfr_wait[15:1] ips_xfr_err[15:1] Figure 7-2. Block Diagram of the AIPI Module MOTOROLA AHB to IP Bus Interface (AIPI)
Page 136: Table 7-1 R-Ahb To Ip Bus Interface Operation (Big Endian-Read Operation)
16-bit ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0] 32-bit ips_rdata ips_rdata – – [31:24] [23:16] – – ips_rdata[15:8] ips_rdata[7:0] MC9328MX1 Reference Manual MOTOROLA...
Page 137 – ips_wdata[7:0] – – – – ips_wdata – [15:8] – – – ips_wdata[7:0] 32-bit ips_wdata – – – [31:24] – ips_wdata – – [23:16] – – ips_wdata – [15:8] – – – ips_wdata[7:0] MOTOROLA AHB to IP Bus Interface (AIPI)
Page 138: Table 7-2 R-Ahb To Ip Bus Interface Operation (Big Endian-Write Operation)
8-bit ips_wdata[7:0] – – – – ips_wdata[7:0] – – – – ips_wdata[7:0] – – – – ips_wdata[7:0] 16-bit ips_wdata ips_wdata[7:0] – – [15:8] – – ips_wdata ips_wdata[7:0] [15:8] 32-bit ips_wdata ips_wdata ips_wdata ips_wdata[7:0] [31:24] [23:16] [15:8] MC9328MX1 Reference Manual MOTOROLA...
Page 139: Table 7-3 R-Ahb To Ip Bus Interface Operation (Little Endian-Read Operation)
Word ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] 16-bit ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0] 32-bit – – ips_rdata[15:8] ips_rdata[7:0] ips_rdata ips_rdata – – [31:24] [23:16] MOTOROLA AHB to IP Bus Interface (AIPI)
Page 140 – ips_wdata[7:0] – – ips_wdata – [15:8] – ips_wdata[7:0] – – ips_wdata – – – [15:8] 32-bit – – – ips_wdata[7:0] – – ips_wdata – [15:8] – ips_wdata – – [23:16] ips_wdata – – – [31:24] MC9328MX1 Reference Manual MOTOROLA...
Page 141: Table 7-4 R-Ahb To Ip Bus Interface Operation (Little Endian-Write Operation)
– ips_wdata[7:0] – – ips_wdata[7:0] – – ips_wdata[7:0] – – ips_wdata[7:0] – – – 16-bit – – ips_wdata ips_wdata[7:0] [15:8] ips_wdata ips_wdata[7:0] – – [15:8] 32-bit ips_wdata ips_wdata ips_wdata ips_wdata[7:0] [31:24] [23:16] [15:8] MOTOROLA AHB to IP Bus Interface (AIPI)
Page 142: Table 7-5 Aipi Module Register Memory Map
0x0021 5000 – 0x0021 5FFF 0x0020 6000 – 0x0020 6FFF 0x0021 6000 – 0x0021 6FFF 0x0020 7000 – 0x0020 7FFF 0x0021 7000 – 0x0021 7FFF 0x0020 8000 – 0x0020 8FFF 0x0021 8000 – 0x0021 8FFF 7-10 MC9328MX1 Reference Manual MOTOROLA...
Page 143: Table 7-6 Peripheral Address Module_En Numbers
0x0021 C000 – 0x0021 CFFF 0x0020 D000 – 0x0020 DFFF 0x0021 D000 – 0x0021 DFFF 0x0020 E000 – 0x0020 EFFF 0x0021 E000 – 0x0021 EFFF 0x0020 F000 – 0x0020 FFFF 0x0021 F000 – 0x0021 FFFF MOTOROLA AHB to IP Bus Interface (AIPI) 7-11...
Page 144: Peripheral Size Registers[1:0]
Module_En (Lower)—Each bit represents the lower bit of See Table 7-9 for bit settings Bits 15–1 the 2-bit field (PSR1 + PSR0) that represents the Module_En number. Reserved Reserved—This bit is reserved and should read 0. Bit 0 7-12 MC9328MX1 Reference Manual MOTOROLA...
Page 145: Table 7-8 Aipi1 Peripheral Size Register 1 And Aipi2 Peripheral Size Register 1 Description
AIPI registers, {PSR1[bit0], PSR0[bit0]} returns a value of 10, indicating that the AIPI registers are word width registers. Table 7-9 shows how to program the PSR registers based on the size or availability of an IP bus peripheral. MOTOROLA AHB to IP Bus Interface (AIPI) 7-13...
Page 146: Peripheral Access Registers
Bits 31 through 16 in both registers are preset to 1 and the fields are reserved and can only be read. Addr PAR_1 AIPI1 Peripheral Access Register 0x00200008 PAR_2 AIPI2 Peripheral Access Register 0x00210008 TYPE PAR_1 RESET 0xFFFF PAR_2 RESET 0xFFFF ACCESS TYPE PAR_1 RESET 0xFFFF PAR_2 RESET 0xFFFF 7-14 MC9328MX1 Reference Manual MOTOROLA...
Page 147: Peripheral Control Register
Bits 31 through 16 in both registers are preset to 0 and the fields are reserved and can only be read. Addr PCR_1 AIPI1 Peripheral Control Register 0x0020000C PCR_2 AIPI2 Peripheral Control Register 0x0021000C TYPE PCR_1 RESET 0x0000 PCR_2 RESET 0x0000 ACCESS_MODE TYPE PCR_1 RESET 0x0000 PCR_2 RESET 0x0000 MOTOROLA AHB to IP Bus Interface (AIPI) 7-15...
Page 148: Time-Out Status Register
The register is clear during initial reset. Addr TSR_1 AIPI1 Time-Out Status Register 0x00200010 TSR_2 AIPI2 Time-Out Status Register 0x00210010 ADDR TYPE TSR_1 RESET 0x0000 TSR_2 RESET 0x0000 MODULE_EN TYPE TSR_1 RESET 0x0000 TSR_2 RESET 0x0000 7-16 MC9328MX1 Reference Manual MOTOROLA...
Page 149: Programming Example
[r2, #0x1] STRH [r2, #0x2] [r2, #0x4] LDRB [r2, #0x0] LDRB [r2, #0x1] LDRH [r2, #0x2] [r2, #0x4] The Table 7-13 on page 7-18 illustrates the difference in the 8-bit peripheral register content. MOTOROLA AHB to IP Bus Interface (AIPI) 7-17...
Page 150: Data Access To 16-Bit Peripherals
[r2, #0x2] [r2, #0x4] The Table 7-14 and Table 7-15 illustrate the difference in the 16-bit peripheral register content. Table 7-14. Core and 16-Bit Peripheral Register Content (Little Endian) Address Peripheral Registers – – – – 7-18 MC9328MX1 Reference Manual MOTOROLA...
Page 151: Data Access To 32-Bit Peripherals
[r2, #0x2] [r2, #0x4] LDRB [r2, #0x0] LDRB [r2, #0x1] LDRH [r2, #0x2] [r2, #0x4] The Table 7-16 and Table 7-17 on page 7-20 illustrate the difference in the 32-bit peripheral register content. MOTOROLA AHB to IP Bus Interface (AIPI) 7-19...
Page 152: Special Consideration For Non-Natural Size Access
Therefore, if a programmer is using byte access to set up control information in 32-bit register, extreme care must be taken to ensure the desired byte is written during the desired endian mode. 7-20 MC9328MX1 Reference Manual MOTOROLA...
Page 153: Table 8-1 System Control Module Register Memory Map
Table 8-1. System Control Module Register Memory Map Description Name Address Silicon ID Register SIDR 0x0021B804 Function Multiplexing Control Register FMCR 0x0021B808 Global Peripheral Control Register GPCR 0x0021B80C Global Clock Control Register GCCR 0x0021B810 MOTOROLA System Control...
Page 154: Silicon Id Register
The settings for the bits in the register are listed in Table 8-2. Addr SIDR Silicon ID Register 0x0021B804 TYPE RESET 0x0005 TYPE RESET 0x901D Table 8-2. Silicon ID Register Description Name Description Silicon ID—Contains the chip identification number of the MC9328MX1. Bits 31–0 MC9328MX1 Reference Manual MOTOROLA...
Page 155: Function Multiplexing Control Register
Transmit Frame Sync input source. 1 = Input from Port B[18] SIM_RST pin SSI_TXCLK_SEL SSI Transmit Clock Select—Selects the 0 = Input from Port C[8] SSI_TXCLK pin Bit 3 Transmit Clock input source. 1 = Input from Port B[19] SIM_CLK pin MOTOROLA System Control...
Page 156: Global Peripheral Control Register
The Global Peripheral Control Register (GPCR) controls the driving force parameters of the bus and several other functions in the MC9328MX1. Descriptions of the register settings appear in Table 8-4. Addr GPCR Global Peripheral Control Register 0x0021B80C TYPE RESET 0x0000 TYPE RESET 0x03FB MC9328MX1 Reference Manual MOTOROLA...
Page 157: Table 8-4 Global Peripheral Control Register Description
CMOS Sensor Interface Privileged Mode 0 = All access modes available Bit 0 Access—Selects whether the CSI can only be 1 = Privileged mode access only accessed in privileged mode or if it can be accessed in all modes. MOTOROLA System Control...
Page 158: Global Clock Control Register
1 = CSI clock input is enabled (default). Bit 2 USBD_ USBD Clock Enable—Enables/Disables clock input 0 = USB clock input is disabled. CLK_EN to the USB module. 1 = USB clock input is enabled (default). Bit 2 MC9328MX1 Reference Manual MOTOROLA...
Page 159: Table 8-6 System Boot Mode Selection
Output Signals BOOT[3:0] Active Device 0000 Bootstrap ROM 0001 16-bit SyncFlash D[15:0] 0010 32-bit SyncFlash 0011 8-bit CS0 at D[7:0] 0100 16-bit CS0 at D[31:16] 0101 16-bit CS0 at D[15:0] 0110 32-bit CS0 at D[31:0] 0111 Reserved MOTOROLA System Control...
Page 160 System Control MC9328MX1 Reference Manual MOTOROLA...
Page 161: Operation
The instruction buffer allows the user to download the vector table to the buffer without the use of external ROM or Flash. The feature provides the user a fast and easy environment to use IRQ during program debugging. MOTOROLA Bootstrap Mode Operation...
Page 162: Entering Bootstrap Mode
Comments can be added to files of b-records. As described above, the shortest b-record consists of 10 ASCII characters (when the data count is 0) of 0 to 9 or A to F (hexadecimal digits). Comments included must not contain patterns to prevent the comments from being considered a b-record. MC9328MX1 Reference Manual MOTOROLA...
Page 163: Registers Used In Bootloader Program
The buffer starts at 0x00000004. Up to eight instructions can be loaded to the instruction buffer for execution.Usually, the last instruction is an unconditional jump instruction (jmp) that jumps to the start of the bootloader program (0x00000100). MOTOROLA Bootstrap Mode Operation...
Page 164: Table 9-3 Program Breakdown
Breaking down the register initialization into three parts is not mandatory, however it produces similar b-records and therefore is easier to manage. The resulting b-records appear in Table 9-4. Table 9-4. Resulting B-Records B-Record Number B-Record 00000004 08E3A04F40E1A0F004 0000000400 00000004 08E3A019C4E1A0F004 0000000400 00000004 08E3A02F40E1A0F004 0000000400 00000004 0CE59F3000E1A0F00412345678 0000000400 MC9328MX1 Reference Manual MOTOROLA...
Page 165: Simple Read/Write Examples
0031000003XXYYZZ/ from location (where XX, YY, and ZZ are data in byte) 0x00310000 Read 3 half-words 0031000066 0031000066XXXXYYYYZZZZ/ starting from location (6 bytes = 3 half-words) (where XXXX, YYYY, and ZZZZ are data in 0x00310000 half-word) MOTOROLA Bootstrap Mode Operation...
Page 166 Write 3 bytes starting 0031000003112233 0031000003112233/ from location 0x00310000 Write 3 half-words 0031000046111122223333 0031000046111122223333/ starting from location (6 bytes = 3 half-words) 0x00310000 Write 3 words starting 00310000CC111111112222 00310000CC111111112222222233333333/ from location 222233333333 0x00310000 (12 bytes = 3 words) MC9328MX1 Reference Manual MOTOROLA...
Page 167: Bootloader Flowchart
Comments in a b-record or b-record file must not contain any word or symbol that is longer than nine characters. However, the following characters can be used in a string of any length (all of these have an ASCII code value that is less than 0x30): — space MOTOROLA Bootstrap Mode Operation...
Page 168 (ASCII code value less than 0x30) will force the bootloader to start a new b-record. • General-purpose registers r7–r14 and supervisor scratch registerss3 are used by the bootloader program. Writing to these registers may corrupt the bootloader program. • Please visit the DragonBall Web site for bootstrap utility programs. MC9328MX1 Reference Manual MOTOROLA...
Page 169: Figure 10-1 Aitc Block Diagram
Supports a maximum of 64 interrupt sources • Supports fast and normal interrupts • Selects normal or fast interrupt request for any interrupt source • Indicates pending interrupt sources via a register for normal and fast interrupts MOTOROLA Interrupt Controller (AITC) 10-1...
Page 170: Operation
The interrupt requests are prioritized in the following order: 1. Fast interrupt requests, in order of highest number 2. Normal interrupt requests, in order of highest priority level, then highest source number with the same priority 10-2 MC9328MX1 Reference Manual MOTOROLA...
Page 171: Aitc Interrupt Controller Signals
Unused PWM_INT Unused MMC_IRQ Unused Unused PEN_UP_INT Unused CSI_INT Unused MMA_MAC_INT I2C_INT MMA_INT SPI2_INT COMP_INT SPI1_INT MSIRQ SSI_TX_INT GPIO_INT_PORTA SSI_TX_ERR_INT GPIO_INT_PORTB SSI_RX_INT GPIO_INT_PORTC SSI_RX_ERR_INT LCDC_INT TOUCH_INT SIM_IRQ USBD_INT [0] SIM_DATA USBD_INT [1] RTC_INT USBD_INT [2] MOTOROLA Interrupt Controller (AITC) 10-3...
Page 172: Table 10-2 Aitc Module Register Memory Map
Interrupt Disable Number Register INTDISNUM 0x0022300C Interrupt Enable Register High INTENABLEH 0x00223010 Interrupt Enable Register Low INTENABLEL 0x00223014 Interrupt Type Register High INTTYPEH 0x00223018 Interrupt Type Register Low INTTYPEL 0x0022301C Normal Interrupt Priority Level Register 7 NIPRIORITY7 0x00223020 10-4 MC9328MX1 Reference Manual MOTOROLA...
Page 173 0x00223050 Interrupt Force Register Low INTFRCL 0x00223054 Normal Interrupt Pending Register High NIPNDH 0x00223058 Normal Interrupt Pending Register Low NIPNDL 0x0022305C Fast Interrupt Pending Register High FIPNDH 0x00223060 Fast Interrupt Pending Register Low FIPNDL 0x00223064 MOTOROLA Interrupt Controller (AITC) 10-5...
Page 174: Table 10-3 Register Field Summary
NIPRIORITY2 NIPR23 NIPR22 NIPR21 NIPR20 NIPR19 NIPR18 NIPR17 NIPR16 NIPRIORITY1 NIPR15 NIPR14 NIPR13 NIPR12 NIPR11 NIPR10 NIPR9 NIPR8 NIPRIORITY0 NIPR7 NIPR6 NIPR5 NIPR4 NIPR3 NIPR2 NIPR1 NIPR0 NIVECTOR NIPRILVL NIVECSR FIVECTOR FIVECSR INTIN [63:32] INTSRCH 10-6 MC9328MX1 Reference Manual MOTOROLA...
Page 175: Interrupt Control Register
(32-bit) boundaries. Addr INTCNTL Interrupt Control Register 0x00223000 NIAD FIAD TYPE RESET 0x0000 TYPE RESET 0x0000 Table 10-4. Interrupt Control Register Description Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–21 MOTOROLA Interrupt Controller (AITC) 10-7...
Page 176 Note: To prevent an alternate master from accessing the bus during an interrupt service routine, do not clear the interrupt flag until the end of the service routine. Reserved Reserved—These bits are reserved and should read 0. Bits 18–0 10-8 MC9328MX1 Reference Manual MOTOROLA...
Page 177: Normal Interrupt Mask Register
1 = Disable priority level 1 and lower normal interrupts of priority level less than or equal to the NIMASK are disabled. Settings are shown 16+ = Disable all normal interrupts. in decimal. Setting bit 4 disables all normal interrupts. MOTOROLA Interrupt Controller (AITC) 10-9...
Page 178: Interrupt Enable Number Register
Reserved—These bits are reserved and should read 0. Bits 31–6 ENNUM Interrupt Enable Number—Enables/Disables the 0x00 = Enable interrupt source 0 Bits 5–0 interrupt source associated with this value. 0x01 = Enable interrupt source 1 0x3F = Enable interrupt source 63 10-10 MC9328MX1 Reference Manual MOTOROLA...
Page 179: Interrupt Disable Number Register
Reserved—These bits are reserved and should read 0. Bits 31–6 DISNUM Interrupt Disable Number—Enables/Disables the 0x00 = Disable interrupt source 0 Bits 5–0 interrupt source associated with this value. 0x01 = Disable interrupt source 1 0x3F = Disable interrupt source 63 MOTOROLA Interrupt Controller (AITC) 10-11...
Page 180: Table 10-8 Interrupt Enable Register High Description
INTTYPEH and INTTYPEL setting. interrupt upon assertion 10-12 MC9328MX1 Reference Manual MOTOROLA...
Page 181: Interrupt Enable Register Low
INTTYPEH and INTTYPEL setting. interrupt upon assertion MOTOROLA Interrupt Controller (AITC) 10-13...
Page 182: Interrupt Type Register High And Interrupt Type Register Low
(nIRQ) When a INTTYPE bit is set and the corresponding interrupt 1 = Interrupt source generates a source is asserted, the interrupt controller asserts a fast interrupt fast interrupt (nFIQ) request. 10-14 MC9328MX1 Reference Manual MOTOROLA...
Page 183: Interrupt Type Register Low
NIMASK has not disabled level 1 normal interrupts. These registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be accessed only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries. MOTOROLA Interrupt Controller (AITC) 10-15...
Page 184: Normal Interrupt Priority Level Register 7
1111 = Highest priority normal Bits 27–24 These registers do not affect the prioritization of fast interrupt interrupt priorities. NIPR61 Bits 23–20 NIPR60 Bits 19–16 NIPR59 Bits 15–12 NIPR58 Bits 11–8 NIPR57 Bits 7–4 NIPR56 Bits 3–0 10-16 MC9328MX1 Reference Manual MOTOROLA...
Page 185: Normal Interrupt Priority Level Register 6
1111 = Highest priority normal Bits 27–24 These registers do not affect the prioritization of fast interrupt interrupt priorities. NIPR53 Bits 23–20 NIPR52 Bits 19–16 NIPR51 Bits 15–12 NIPR50 Bits 11–8 NIPR49 Bits 7–4 NIPR48 Bits 3–0 MOTOROLA Interrupt Controller (AITC) 10-17...
Page 186: Normal Interrupt Priority Level Register 5
1111 = Highest priority normal Bits 27–24 These registers do not affect the prioritization of fast interrupt interrupt priorities. NIPR45 Bits 23–20 NIPR44 Bits 19–16 NIPR43 Bits 15–12 NIPR42 Bits 11–8 NIPR41 Bits 7–4 NIPR40 Bits 3–0 10-18 MC9328MX1 Reference Manual MOTOROLA...
Page 187: Normal Interrupt Priority Level Register 4
1111 = Highest priority normal Bits 27–24 These registers do not affect the prioritization of fast interrupt interrupt priorities. NIPR37 Bits 23–20 NIPR36 Bits 19–16 NIPR35 Bits 15–12 NIPR34 Bits 11–8 NIPR33 Bits 7–4 NIPR32 Bits 3–0 MOTOROLA Interrupt Controller (AITC) 10-19...
Page 188: Normal Interrupt Priority Level Register 3
1111 = Highest priority normal Bits 27–24 These registers do not affect the prioritization of fast interrupt interrupt priorities. NIPR29 Bits 23–20 NIPR28 Bits 19–16 NIPR27 Bits 15–12 NIPR26 Bits 11–8 NIPR25 Bits 7–4 NIPR24 Bits 3–0 10-20 MC9328MX1 Reference Manual MOTOROLA...
Page 189: Normal Interrupt Priority Level Register 2
1111 = Highest priority normal Bits 27–24 These registers do not affect the prioritization of fast interrupt interrupt priorities. NIPR21 Bits 23–20 NIPR20 Bits 19–16 NIPR19 Bits 15–12 NIPR18 Bits 11–8 NIPR17 Bits 7–4 NIPR16 Bits 3–0 MOTOROLA Interrupt Controller (AITC) 10-21...
Page 190: Normal Interrupt Priority Level Register 1
1111 = Highest priority normal Bits 27–24 These registers do not affect the prioritization of fast interrupt interrupt priorities. NIPR13 Bits 23–20 NIPR12 Bits 19–16 NIPR11 Bits 15–12 NIPR10 Bits 11–8 NIPR9 Bits 7–4 NIPR8 Bits 3–0 10-22 MC9328MX1 Reference Manual MOTOROLA...
Page 191: Normal Interrupt Priority Level Register 0
1111 = Highest priority normal Bits 27–24 These registers do not affect the prioritization of fast interrupt interrupt priorities. NIPR5 Bits 23–20 NIPR4 Bits 19–16 NIPR3 Bits 15–12 NIPR2 Bits 11–8 NIPR1 Bits 7–4 NIPR0 Bits 3–0 MOTOROLA Interrupt Controller (AITC) 10-23...
Page 192: Normal Interrupt Vector And Status Register
This number can be written to the NIMASK to disable the current priority normal interrupts to build 15 = Highest priority normal interrupt is level a reentrant normal interrupt system. Settings are shown in decimal. 16+ = No normal interrupt request pending 10-24 MC9328MX1 Reference Manual MOTOROLA...
Page 193: Fast Interrupt Vector And Status Register
0 = Interrupt 0 is highest pending fast interrupt 1 = Interrupt 1 is highest pending fast interrupt 63 = Interrupt 63 is highest pending fast interrupt 64+ = not used, does not occur MOTOROLA Interrupt Controller (AITC) 10-25...
Page 194: Table 10-22 Interrupt Source Register High Description
1 = Interrupt source asserted NOTE: The peripheral circuits generating the requests determine the state of this register out of reset; normally, the requests are inactive. This read-only register must be accessed only on word (32-bit) boundaries. 10-26 MC9328MX1 Reference Manual MOTOROLA...
Page 195: Interrupt Source Register Low
1 = Interrupt source asserted NOTE: The state of this register out of reset is determined by the peripheral circuits generating the requests; normally, the requests are inactive. This read-only register must be accessed only on word (32-bit) boundaries. MOTOROLA Interrupt Controller (AITC) 10-27...
Page 196: Interrupt Force Register High And Interrupt Force Register Low
0x0000 Table 10-24. Interrupt Force Register High Description Name Description Settings FORCE Interrupt Source Force Request—Forces a request for the 0 = Standard interrupt operation Bits 31–0 corresponding interrupt source. 1 = Interrupt forced asserted 10-28 MC9328MX1 Reference Manual MOTOROLA...
Page 197: Interrupt Force Register Low
0x0000 Table 10-25. Interrupt Force Register Low Description Name Description Settings FORCE Interrupt Source Force Request—Forces a request for the 0 = Standard interrupt operation Bits 31–0 corresponding interrupt source. 1 = Interrupt forced asserted MOTOROLA Interrupt Controller (AITC) 10-29...
Page 198: And Normal Interrupt Pending Register Low
The normal interrupt pending bits reflect the interrupt input lines that are asserted and are currently enabled to generate a normal interrupt. 10-30 MC9328MX1 Reference Manual MOTOROLA...
Page 199: Normal Interrupt Pending Register Low
The normal interrupt pending bits reflect the interrupt input lines that are asserted and are currently enabled to generate a normal interrupt. MOTOROLA Interrupt Controller (AITC) 10-31...
Page 200: Table 10-28 Fast Interrupt Pending Register High Description
1 = Fast interrupt request pending controller asserts a fast interrupt request. The fast interrupt pending bits reflect the interrupt input lines that are asserted and are currently enabled to generate a fast interrupt. 10-32 MC9328MX1 Reference Manual MOTOROLA...
Page 201: Fast Interrupt Pending Register Low
1 = Fast interrupt request pending controller asserts a fast interrupt request. The fast interrupt pending bits reflect the interrupt input lines that are asserted and are currently enabled to generate a fast interrupt. MOTOROLA Interrupt Controller (AITC) 10-33...
Page 202: Arm920T Processor Interrupt Controller Operation
ORs this mask to the correct INTENABLEH and INTENABLEL register. To disable interrupts, the procedure is exactly the same except the source number is written to the INTDISNUM register. 10-34 MC9328MX1 Reference Manual MOTOROLA...
Page 203: Typical Interrupt Entry Sequences
FIQ service routine begins at 0x0000001C and single cycle memories. Table 10-31. Typical Fast Interrupt Entry Sequence Time Address –2 –1 nFIQ nFIQ Assert Last ADDR before nFIQ Fetch Exec Link Adjust +4 / +2 Fetch +8 / +4 Fetch 0x0000001C Fetch Exec MOTOROLA Interrupt Controller (AITC) 10-35...
Page 204: Writing Reentrant Normal Interrupt Routines
13. Pop the link register from the stack into the PC. 14. Return from nIRQ. NOTE: These steps are still in development and are subject to change. Steps 1, 2, 13, and 14 are automatically done by most C compilers and are included for completeness. 10-36 MC9328MX1 Reference Manual MOTOROLA...
Page 205: Eim I/O Signals
The A [24:0] signals are address bus outputs used to address external devices. 11.2.2 Data Bus The D [31:0] signals are bidirectional data bus pins used to transfer data between the MC9328MX1 and an external device. MOTOROLA External Interface Module (EIM) 11-1...
Page 206: Read/Write
The CS1 through CS5 output signals are active-low and are asserted based on a decode of the internal address bus bits A [31:24] of the accessed address. When disabled, these pins can be used as programmable general-purpose outputs. Table 11-1 specifies the address range for each Chip Select output. 11-2 MC9328MX1 Reference Manual MOTOROLA...
Page 207: Burst Mode Signals
11.3 Pin Configuration for EIM Table 11-2 lists the pins used for the EIM module. Many of these pins are multiplexed with other functions on the device, and must be configured for EIM operation. MOTOROLA External Interface Module (EIM) 11-3...
Page 208: Table 11-2 Eim Pin List
1. Clear bits [23:22] of Port A GPIO In Use Register (GIUS_A) A [23:22] 2. Clear bits [23:22] of Port A General Purpose Register (GPR_A) CS [3] Primary function of pin shared 1. Clear bit 1 (SDCS1_SEL) of Function Muxing Control Register (FMCR) with SDRAM’s CSD1 11-4 MC9328MX1 Reference Manual MOTOROLA...
Page 209 2. Clear bit 19 of Port A General Purpose Register (GPR_A) Not Multiplexed Primary function of GPIO Port 1. Clear bit 20 of Port A GPIO In Use Register (GIUS_A) A [20] 2. Clear bit 20 of Port A General Purpose Register (GPR_A) MOTOROLA External Interface Module (EIM) 11-5...
Page 210: Typical Eim System Connections
Intel EB [2] Flash EB [2] 512Kx16 D [15:0] Data [15:0] ACIA R’W D [7:0] Data [7:0] BCLK Control D [7:0] Data [7:0] EB [3] Figure 11-1. Example of EIM Interface to Memory and Peripherals 11-6 MC9328MX1 Reference Manual MOTOROLA...
Page 211: Figure 11-2 Example Of Eim Interface To Burst Memory
BCLK FLASH WAIT# D [31:16] DQ [15:0] 1Mx16 A [16:1] Address [15:0] EB [2] EB [2] EB [3] EB [3] 64Kx16 D [15:1] Data [15:0] Figure 11-2. Example of EIM Interface to Burst Memory MOTOROLA External Interface Module (EIM) 11-7...
Page 212: Eim Functionality
AHB bus. The internal bus frequency can be divided by 2, 3, or 4 for presentation on the external bus in burst mode operation. 11-8 MC9328MX1 Reference Manual MOTOROLA...
Page 213: Burst Clock Start
• User read or write access to a chip select control register or the EIM configuration register • Byte or halfword access to a chip select control register or the EIM configuration register MOTOROLA External Interface Module (EIM) 11-9...
Page 214: Table 11-4 Eim Module Register Memory Map
Chip Select 4 Upper Control Register CS4U 0x00220020 Chip Select 4 Lower Control Register CS4L 0x00220024 Chip Select 5 Upper Control Register CS5U 0x00220028 Chip Select 5 Lower Control Register CS5L 0x0022002C EIM Configuration Register 0x00220030 11-10 MC9328MX1 Reference Manual MOTOROLA...
Page 215: Chip Select 0 Control Registers
11.6.1.2 Chip Select 0 Lower Control Register Addr CS0L Chip Select 0 Lower Control Register 0x00220004 TYPE RESET 0x0000 CSEN TYPE RESET 0x0801 For bit descriptions, see Table 11-5 on page 11-13. *Configurable on reset. MOTOROLA External Interface Module (EIM) 11-11...
Page 216: Chip Select 1–Chip Select 5 Control Registers
Chip Select 3 Upper Control Register 0x00220018 CS4U Chip Select 4 Upper Control Register 0x00220020 CS5U Chip Select 5 Upper Control Register 0x00220028 62 61 DTACK_SEL SYNC TYPE RESET 0x0000 46 45 TYPE rw rw RESET 0x0000 11-12 MC9328MX1 Reference Manual MOTOROLA...
Page 217: Table 11-5 Chip Select Control Registers Description
When the 11 = Divisor is 4 BCM bit is set (BCM = 1) in the EIM configuration register, BCD is ignored. BCD is cleared by a hardware reset. MOTOROLA External Interface Module (EIM) 11-13...
Page 218 EIM data setup time requirements. DOL has no effect on EIM data latching when SYNC = 0. DOL is cleared by a hardware reset. 11-14 MC9328MX1 Reference Manual MOTOROLA...
Page 219 See Table 11-6, "Chip Select Wait State and Bits 38–36 additional wait-states are required for write Burst Delay Encoding" cycles. This is useful for writing to memories that require additional data setup time. WWS is cleared by a hardware reset. MOTOROLA External Interface Module (EIM) 11-15...
Page 220 0001 = 1 half clock before assertion meet data setup time requirements for slow memories. 1111 = 15 half clocks before assertion WEA does not affect the cycle length. WEA is cleared by a hardware reset. 11-16 MC9328MX1 Reference Manual MOTOROLA...
Page 221 User mode results in a TEA to the ARM9 core and no assertion of the chip select output Reserved Reserved—This bit is reserved and should read 0. Bit 5 MOTOROLA External Interface Module (EIM) 11-17...
Page 222: Table 11-6 Chip Select Wait State And Burst Delay Encoding
Table 11-6. Chip Select Wait State and Burst Delay Encoding Number of Wait-States WWS = 0 WWS = 1 WWS = 7 WSC [5:0] Read Write Read Write Read Write Access Access Access Access Access Access 000000 000001 000010 000011 000100 000101 000110 11-18 MC9328MX1 Reference Manual MOTOROLA...
Page 223 Read Write Access Access Access Access Access Access 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 MOTOROLA External Interface Module (EIM) 11-19...
Page 224 Write Read Write Access Access Access Access Access Access 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 11-20 MC9328MX1 Reference Manual MOTOROLA...
Page 225: Eim Configuration Register
The EIM Configuration Register contains the bit that controls the operation of the burst clock. Addr EIM Configuration Register 0x00220030 TYPE RESET 0x0000 TYPE RESET 0x0000 Table 11-7. EIM Configuration Register Description Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31– 3 MOTOROLA External Interface Module (EIM) 11-21...
Page 226 BCD and BCS bits in the chip select control register. 1 = The burst clock runs all the time (independent of chip select accesses). Reserved Reserved—These bits are reserved and should read 0. Bits 1–0 11-22 MC9328MX1 Reference Manual MOTOROLA...
Page 227: Clock Sources
System_SEL bit in the Clock Source Control Register to produce all of the system clocks from a single 32 kHz crystal oscillator. See Section 12.3.1, “DPLL Phase and Frequency Jitter,” for more detailed information on phase and frequency jitter specifications using this configuration. MOTOROLA Phase-Locked Loop and Clock Controller 12-1...
Page 228: High Frequency Clock Source
16 MHz clock input from an external Bluetooth RF module through the Stop internal BTA module. CLK48M Continuous 48 MHz clock output when System PLL is enabled or when external 48 MHz clock is selected. FCLK Fast clock (FCLK) output to the CPU. 12-2 MC9328MX1 Reference Manual MOTOROLA...
Page 229: Dpll Output Frequency Calculation
Frequency and Phase Lock (FPL) mode. The DPLL mode is user selectable. The DPLL communicates with the clock module. This block contains a control register and provides an interface between the DPLL and the ARMTDMI core. MOTOROLA Phase-Locked Loop and Clock Controller 12-3...
Page 230: Mc9328Mx1 Power Management
Deep power-down mode 12.4.5 Power Management in the Clock Controller Power management in the MC9328MX1 is achieved by controlling the duty cycles of the clock system efficiently. The clocking control scheme is shown in Table 12-3. 12-4 MC9328MX1 Reference Manual MOTOROLA...
Page 231: Clock Source Control Register
32 kHz derived clock source to the System PLL when the design requires clock signals with greater frequency and phase jitter performance than the internal PLL using the 32 kHz clock source provides. MOTOROLA Phase-Locked Loop and Clock Controller 12-5...
Page 232: Table 12-5 Clock Source Control Register Description
11 = System PLL shuts down after forth rising edge of CLK32 is detected and the current bus cycle is completed. Reserved Reserved—This bit is reserved and should read 0. Bit 23 12-6 MC9328MX1 Reference Manual MOTOROLA...
Page 233 PLL. When cleared, the MCU PLL is disabled. 1 = MCU PLL enabled When software writes 0 to MPEN, the PLL shuts down immediately. MPEN sets automatically when MPLLEN asserts, and on system reset. MOTOROLA Phase-Locked Loop and Clock Controller 12-7...
Page 234: Peripheral Clock Divider Register
0000 = Divide by 1 Bits 7–4 produces the PERCLK2 clock signal for the peripherals. The input to 0001 = Divide by 2 the PCLK_DIV2 divider circuit is System PLLCLK. … 1111 = Divide by 16 12-8 MC9328MX1 Reference Manual MOTOROLA...
Page 235: Programming Digital Phase Locked Loops
MCU PLL settings: 1. Program the desired values of PD, MFD, MFI, and MFN into the MPCTL0. 2. Set the MPLL_RESTART bit in the CSCR (it will self-clear). 3. New PLL settings will take place. MOTOROLA Phase-Locked Loop and Clock Controller 12-9...
Page 236: Table 12-9 Mcu Pll Control Register 0 Description
BRM value for the MF. When a new value is written into the MFN bits, 0x001 = 1 the PLL loses its lock; after a time delay, the PLL re-locks. 0x3FE = 1022 0x3FF = Reserved 12-10 MC9328MX1 Reference Manual MOTOROLA...
Page 237: Mcu Pll And System Clock Control Register 1
Table 12-11. System PLL Multiplier Factor Input Premultiplier Output USBDIV Clock Frequency Frequency Frequency 32 kHz 16.384 MHz 96 MHz 48 MHz The default setting exception is USB_DIV. The user must program this to 010. MOTOROLA Phase-Locked Loop and Clock Controller 12-11...
Page 238: System Pll Control Register 0
BRM value for the MF. When a new value is written into the MFD9–MFD0 0x001 = 1 bits, the PLL loses its lock: after a time delay, the PLL re-locks. … 0x3FF = 1023 Reserved Reserved—These bits are reserved and should read 0. Bits 15–14 12-12 MC9328MX1 Reference Manual MOTOROLA...
Page 239: System Pll Control Register 1
System PLL clock output is valid. When cleared, the 1 = System PLL is locked System PLL clock output remains at logic high. Reserved Reserved—These bits are reserved and should read 0. Bits 14–7 MOTOROLA Phase-Locked Loop and Clock Controller 12-13...
Page 240 1 = BRM has second order 9/10. In other cases, the second order BRM is used. The BRMO bit is cleared by a hardware reset. Reserved Reserved—These bits are reserved and should read 0. Bits 5–0 12-14 MC9328MX1 Reference Manual MOTOROLA...
Page 241: Features
The DMA controller provides an acknowledge signal to the peripheral after a DMA burst is complete. This signal is sometimes used by the peripheral to clear some status bits. • Repeat data transfer function supports automatic USB host–USB device bulk/iso data stream transfer. MOTOROLA DMA Controller 13-1...
Page 242: Figure 13-1 Dmac In Mc9328Mx1
Cntl Signal Generation DMA_ACK DMA_ACK, AHB I/F DMA_EOBO, and DMA_EOBO AHB_A [31:0] Address DMA_EOBO_CNT Generation Generation DMA_EOBO_CNT DMA_ERR AHB I/F Interrupt AHB_D [31:0] Data Buffer DMA_INT Generation × 32 Data FIFO Figure 13-2. DMAC Block Diagram 13-2 MC9328MX1 Reference Manual MOTOROLA...
Page 243: Figure 13-3 Dma Request And Acknowledge Timing Diagram
This signal must be negated by the peripheral automatically before the rising edge of DMA_ACK. It is usually negated when the FIFO is read. DMA_ACK DMA request acknowledge generated by the DMA controller to signal the end of a DMA burst. MOTOROLA DMA Controller 13-3...
Page 244: Big Endian And Little Endian
Table 13-2. DMA Module Register Memory Map Description Name Address General Registers DMA Control Register 0x00209000 DMA Interrupt Status Register DISR 0x00209004 DMA Interrupt Mask Register DIMR 0x00209008 DMA Burst Time-Out Status Register DBTOSR 0x0020900C 13-4 MC9328MX1 Reference Manual MOTOROLA...
Page 245 Channel 2 Control Register CCR2 0x0020910C Channel 2 Request Source Select Register RSSR2 0x00209110 Channel 2 Burst Length Register BLR2 0x00209114 Channel 2 Request Time-Out Register RTOR2 0x00209118 Channel 2 Bus Utilization Control Register BUCR2 0x00209118 MOTOROLA DMA Controller 13-5...
Page 246 Channel 8 Control Register CCR8 0x0020928C Channel 8 Request Source Select Register RSSR8 0x00209290 Channel 8 Burst Length Register BLR8 0x00209294 Channel 8 Request Time-Out Register RTOR8 0x00209298 Channel 8 Bus Utilization Control Register BUCR8 0x00209298 13-6 MC9328MX1 Reference Manual MOTOROLA...
Page 247 Channel 10 Control Register CCR10 0x0020930C Channel 10 Request Source Select Register RSSR10 0x00209310 Channel 10 Burst Length Register BLR10 0x00209314 Channel 10 Request Time-Out Register RTOR10 0x00209318 Channel 10 Bus Utilization Control Register BUCR10 0x00209318 MOTOROLA DMA Controller 13-7...
Page 248: General Registers
DRST always reads 0. 1 = Generates a 3-cycle reset pulse DMA Enable—Enables/Disables the system clock to the DMA module. 0 = DMA disable Bit 0 1 = DMA enable 13-8 MC9328MX1 Reference Manual MOTOROLA...
Page 249: Dma Interrupt Status Register
Reserved Reserved—These bits are reserved and should read 0. Bits 31–11 CH10–CH0 Channel 10 to 0 Interrupt Status—Indicates the interrupt status for 0 = No interrupt Bits 10–0 each DMA channel. 1 = Interrupt is pending MOTOROLA DMA Controller 13-9...
Page 250: Dma Interrupt Mask Register
Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–11 CH10–CH0 Channel 10 to 0—Controls the interrupts for each DMA channel. 0 = Enables interrupts Bits 10–0 1 = Disables interrupts 13-10 MC9328MX1 Reference Manual MOTOROLA...
Page 251: Dma Burst Time-Out Status Register
Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–11 CH10–CH0 Channel 10 to 0—Indicates the burst time-out status of each DMA 0 = No burst time-out Bits 10–0 channel. 1 = Burst time-out MOTOROLA DMA Controller 13-11...
Page 252: Dma Request Time-Out Status Register
Reserved—These bits are reserved and should read 0. Bits 31–11 CH10–CH0 Channel 10 to 0—Indicates the request time-out status of each 0 = No DMA request time-out Bits 10–0 DMA channel. 1 = DMA request time-out 13-12 MC9328MX1 Reference Manual MOTOROLA...
Page 253: Dma Transfer Error Status Register
Reserved Reserved—These bits are reserved and should read 0. Bits 31–11 CH10–CH0 Channel 10 to 0—Indicates the DMA transfer error status of each 0 = No transfer error Bits 10–0 DMA channel. 1 = Transfer error MOTOROLA DMA Controller 13-13...
Page 254: Dma Buffer Overflow Status Register
Reserved—These bits are reserved and should read 0. Bits 31–11 CH10–CH0 Channel 10 to 0—Indicates the buffer overflow error status 0 = No buffer overflow occurred Bits 10–0 of each DMA channel. 1 = Buffer overflow occurred 13-14 MC9328MX1 Reference Manual MOTOROLA...
Page 255: Dma Burst Time-Out Control Register
Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 Enable—Enables/Disables the burst time-out. 0 = Disables burst time-out Bit 15 1 = Enables burst time-out Count—Contains the time-out count down value. Bits 14–0 MOTOROLA DMA Controller 13-15...
Page 256: D Memory Registers (A And B)
0x0000 TYPE RESET 0x0000 Table 13-11. W-Size Registers Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 W-Size—Contains the number of bytes that make up the display width. Bits 15–0 13-16 MC9328MX1 Reference Manual MOTOROLA...
Page 257: X-Size Registers
Table 13-12. X-Size Registers Description Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 X-Size—Contains the number of bytes per row that define the X-Size of the 2D memory. Bits 15–0 MOTOROLA DMA Controller 13-17...
Page 258: Y-Size Registers
A DMA request time-out is true • A DMA burst time-out is true during a burst cycle • The internal buffer overflows during a burst cycle • A transfer error acknowledge is asserted during a burst cycle 13-18 MC9328MX1 Reference Manual MOTOROLA...
Page 259: Channel Source Address Register
0. These bits will be read/write as any value if and only if running in big endian and source mode set to FIFO. This is to allow FIFO to use offset address during big endian mode. MOTOROLA DMA Controller 13-19...
Page 260: Destination Address Registers
Destination Address—Contains the destination address to which data is written to during a DMA Bits 31–2 transfer. DA [1], DA [0] Destination Address [1] and Destination Address [0]—To ensure that all addresses are Bits 1–0 word-aligned, these bits are set internally to 0. 13-20 MC9328MX1 Reference Manual MOTOROLA...
Page 261: Channel Count Registers
Channel 9 Count Register 0x002092C8 CNTR10 Channel 10 Count Register 0x00209308 TYPE RESET 0x0000 TYPE RESET 0x0000 Table 13-16. Channel Count Registers Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–24 MOTOROLA DMA Controller 13-21...
Page 262: Channel Control Registers
0x0020924C CCR8 Channel 8 Control Register 0x0020928C CCR9 Channel 9 Control Register 0x002092CC CCR10 Channel 10 Control Register 0x0020930C TYPE RESET 0x0000 DMOD SMOD MDIR MSEL DSIZ SSIZ REN RPT FRC CEN TYPE RESET 0x0000 13-22 MC9328MX1 Reference Manual MOTOROLA...
Page 263: Table 13-17 Channel Control Registers Description
Interrupt Mask Register is cleared. The address is reloaded from the source and destination address register for the next DMA burst. Data transfer is carried out continuously until the channel is disabled or it completes the last cycle after RPT is cleared. MOTOROLA DMA Controller 13-23...
Page 264: Table 13-18 Dma_Eobo_Cnt And Dma_Eobi_Cnt Settings
FIFO of a USB device. Table 13-18. DMA_EOBO_CNT and DMA_EOBI_CNT Settings DMA_EOBI_CNT [1:0] or Number of Bytes Per Transfer DMA_EOBO_CNT [1:0] 13-24 MC9328MX1 Reference Manual MOTOROLA...
Page 265: Channel Request Source Select Registers
Bits 31–5 Request Source Select—Selects one of the 32 DMA_REQ 00000 = select DMA_REQ [0] Bits 4–0 signals that initiates a DMA transfer cycle for the channel. 00001 = select DMA_REQ [1] 11111 = select DMA_REQ [31] MOTOROLA DMA Controller 13-25...
Page 266: Channel Burst Length Registers
0x002092D4 BLR10 Channel 10 Burst Length Register 0x00209314 TYPE RESET 0x0000 TYPE RESET 0x0000 Table 13-20. Channel Burst Length Registers Description Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–6 13-26 MC9328MX1 Reference Manual MOTOROLA...
Page 267: Channel Request Time-Out Registers
Channel 6 Request Time-Out Register 0x00209218 RTOR7 Channel 7 Request Time-Out Register 0x00209258 RTOR8 Channel 8 Request Time-Out Register 0x00209298 RTOR9 Channel 9 Request Time-Out Register 0x002092D8 RTOR10 Channel 10 Request Time-Out Register 0x00209318 TYPE RESET 0x0000 TYPE RESET 0x0000 MOTOROLA DMA Controller 13-27...
Page 268: Channel 0 Bus Utilization Control Register
In this case, the user must be careful not to violate the maximum bus request latency of other devices. NOTE: This register shares the same address of request time-out register. 13-28 MC9328MX1 Reference Manual MOTOROLA...
Page 269: Table 13-22 Channel 0 Bus Utilization Control Registers Description
Reserved—These bits are reserved and should read 0. Bits 31–16 CCNT Clock Count—Sets the number of system clocks that must occur before the memory channel Bits 15–0 releases the AHB, before the next DMA request for the channel. MOTOROLA DMA Controller 13-29...
Page 270: Table 13-23 Dma Request Table
DMA_REQ [10] DSPA DCT DIN DMA Request DMA_REQ [9] DSPA DCT DOUT DMA Request DMA_REQ [8] MSHC DMA Request DMA_REQ [7] CSI Receive FIFO DMA Request DMA_REQ [6] CSI Statistic FIFO DMA Request DMA_REQ [5] Reserved 13-30 MC9328MX1 Reference Manual MOTOROLA...
Page 271 DMA Request Table Table 13-23. DMA Request Table (Continued) DMA Request Peripheral DMA_REQ [4] Reserved DMA_REQ [3] Reserved DMA_REQ [2] Reserved DMA_REQ [1] Reserved DMA_REQ [0] Reserved MOTOROLA DMA Controller 13-31...
Page 272 DMA Controller 13-32 MC9328MX1 Reference Manual MOTOROLA...
Page 273: General Overview
7-bit counter to obtain a range of 0.5 to 64 seconds. The user can determine the time-out period by writing to the watchdog time-out field (WT[6:0]) in the Watchdog Control Register (WCR). WHALT (Time-Out) 7-bit Counter CLK2HZ CLK32K Test Mode (TMD bit) Figure 14-1. Watchdog Timer Functional Block Diagram MOTOROLA Watchdog Timer Module 14-1...
Page 274: Watchdog During Reset
If the WSR is not loaded with a $5555 prior to a write of $AAAA to the WSR, the counter will not be reloaded. If any value other than $AAAA is written to the WSR after $5555, the counter will not be reloaded. 14-2 MC9328MX1 Reference Manual MOTOROLA...
Page 275: Time-Out
Reading the TINT bit clears the interrupt and this status bit. 14.4.2 Reset Sources The watchdog timer generates reset signal WDT_RST as a result of a WDOG time-out. This signal is an output to the Reset Module for system reset generation. MOTOROLA Watchdog Timer Module 14-3...
Page 276: Figure 14-2 Counter State Machine
Start Counter Decrement Counter Counting Resumed (fiq, irq, reset) Counting Halted (WHALT=1) Counter Suspended Reload Counter Serviced Count Assert Time-out Indication Interrupt Request Assert wdt_rst Assert wdt_int Reset Interrupt Module Handler Figure 14-2. Counter State Machine 14-4 MC9328MX1 Reference Manual MOTOROLA...
Page 277: Table 14-1 Watchdog Timer I/O Signals
Module read/write signal IPS_ADDR[11:2] Module address bus IPS_WDATA[31:0] Module write data bus SCAN_MODE Indicates scan mode selection SCAN_RESET Indicates scan reset IPS_CONT_CLK_EN ips_cont_clk enable IPS_XFR_ERR Transfer error acknowledge IPS_XFR_WAIT Transfer wait acknowledge IPS_RDATA[31:0] Module read data bus MOTOROLA Watchdog Timer Module 14-5...
Page 278: Watchdog Control Register
1 = Counter is halted The WHALT bit can be cleared by writing 0 to it or it can be automatically cleared by the occurrence of any of three system events, fast interrupt, slow interrupt, or system reset. 14-6 MC9328MX1 Reference Manual MOTOROLA...
Page 279: Watchdog Service Register
The Watchdog Service register contains the watchdog service sequence. When Watchdog is enabled, the Watchdog requires that a service sequence be written to the Watchdog Service Register (WSR) as described in Table 14-3. Addr Watchdog Service Register 0x00201004 TYPE RESET 0x0000 TYPE RESET 0x0000 MOTOROLA Watchdog Timer Module 14-7...
Page 280: Watchdog Status Register
1 = Time-out interrupt generated Reserved Reserved—These bits are reserved and should read 0. Bits 7–1 TOUT Time-Out—Indicates whether the watchdog timer times 0 = Watchdog timer does not time-out. Bit 0 out. 1 = Watchdog timer times out. 14-8 MC9328MX1 Reference Manual MOTOROLA...
Page 281 Programming Model MOTOROLA Watchdog Timer Module 14-9...
Page 282 Watchdog Timer Module 14-10 MC9328MX1 Reference Manual MOTOROLA...
Page 283: Asp Signal Description
SAMPLE RATE CTRL REG Detect LOGIC COMPARE CONTROL REG PADC SWITCH INPUT SELECT From Touch PEN SAMPLE REG (12X16-bit) CIRCUIT Panel comp_int touch_int pen_up_int For Touch Interrupt Generation INTERRUPT GENERATOR pen_data_int Figure 15-1. ASP System Block Diagram MOTOROLA Analog Signal Processor (ASP) 15-1...
Page 284: Figure 15-2 Simplified Asp Signal Path Diagram
Read Y: SW[8..1] = 0011 1001 Auto zero: SW[8..1] = 0000 0000 Auto Calibration X SW[8..1] = 1100 1100 Auto Calibration Y SW[8..1] = 0011 0011 Default: SW [8:1] = 0010 000 Figure 15-2. Simplified ASP Signal Path Diagram 15-2 MC9328MX1 Reference Manual MOTOROLA...
Page 285: Interrupt Generation
FIFO will overflow and old data will be overwritten. When an overflow occurs, the POV status bit is set in the Interrupt/Error Status Register. MOTOROLA Analog Signal Processor (ASP)
Page 286: Current-Mode Operation
= (Vm - V2b) / R2 Where ip and im are limited to ≤ ≤ • -2.5µA +9.5µA ≤ ≤ • -2.5µA +9.5µA Calculation for ∆ i is as follows: ≤ ≤ ∆ i -12µA +12µA Eqn. 15-1 15-4 MC9328MX1 Reference Manual MOTOROLA...
Page 287: Sample Rate Control
DSCNT (t1)—Data setup count: This controls the time for the MUX and touch panel to settle. The max value is 1.575ms at ACLK = 12MHz. • DMCNT (t2)—Decimation count: This controls the number of samples to be averaged, which effectively performs a simple comb filter as the second-stage decimation filter. MOTOROLA Analog Signal Processor (ASP) 15-5...
Page 288: Table 15-5 Output Data Rate Equations
9.6 kHz when DMCNT = 0 and IDLECNT = 0. DSCNT can be set to 0 as there is no need for the settling time for the touch panel and MUX. To get a 200Hz output data rate, set DSCNT = 0, DMCNT = 0, and IDLECNT = 47. 15-6 MC9328MX1 Reference Manual MOTOROLA...
Page 289: Auto-Zero Function
Because a temperature compensation circuit does not exist in the ASP module, software must be used for compensation. Auto calibration mode provides the necessary switch settings to help software provide temperature compensation. MOTOROLA Analog Signal Processor (ASP) 15-7...
Page 290: Table 15-6 Asp Module Register Memory Map
Pen A/D Sample Rate Control Register ASP_PSMPLRG 0x00215014 Compare Control Register ASP_CMPCNTL 0x00215030 Interrupt Control Register ASP_ICNTLR 0x00215018 Interrupt/Error Status Register ASP_ISTATR 0x0021501C Pen Sample FIFO ASP_PADFIFO 0x00215000 Clock Divide Register ASP_CLKDIV 0x0021502C ASP FIFO Pointer Register ASP_FIFO_PTR 0x00215034 15-8 MC9328MX1 Reference Manual MOTOROLA...
Page 291: Asp Control Register
Reserved—This bit is reserved and should read 0. Bit 22 U_SEL U-Channel Resistor Selection—Selects which external 0 = Resistor at UIN and UIP pins Bit 21 resistor to use for U-channel measurement. 1 = Resistor at R1a and R2a pins MOTOROLA Analog Signal Processor (ASP) 15-9...
Page 292 X is [11000110]; Y is [00111001]. Bit 8 Exception cases occur when ACAL bit or ASWB bits are set. Bit 7 Bit 6 Bit 5 Bit 4 Reserved Reserved—These bits are reserved and should read 0. Bits 3–2 15-10 MC9328MX1 Reference Manual MOTOROLA...
Page 293: Pen A/D Sample Rate Control Register
010 = Decimation ratio is 3 011 = Decimation ratio is 4 100 = Decimation ratio is 5 101 = Decimation ratio is 6 110 = Decimation ratio is 7 111 = Decimation ratio is 8 MOTOROLA Analog Signal Processor (ASP) 15-11...
Page 294: Compare Control Register
Reserved—These bits are reserved and should read 0. Bits 31–20 Interrupt Status—Sets when a trigger event is 0 = No trigger event was detected Bit 19 detected. Write 1 to clear. 1 = A trigger event was detected 15-12 MC9328MX1 Reference Manual MOTOROLA...
Page 295: Table 15-10 Interrupt Control Register Description
Reserved—These bits are reserved and should read 0. Bits 9 - 7 Pen Interrupt Polarity—Selects the polarity of the TOUCH_INT 0 = Active low, or falling edge Bit 6 input signal for interrupt trigger. 1 = Active high, or rising edge MOTOROLA Analog Signal Processor (ASP) 15-13...
Page 296: Interrupt/Error Status Register
Pen-up Status—Bit is set when a pen-up event is pending. 0 = No pen-up interrupt is pending Bit 10 Clear by writing ‘1’. 1 = Pen-up interrupt is pending Reserved Reserved—These bits are reserved and should read 0. Bits 9–8 15-14 MC9328MX1 Reference Manual MOTOROLA...
Page 297: Pen Sample Fifo
The 12x16 Pen Sample FIFO holds the sample data after Pen A/D sampling. The data structure is controlled by the MOD bits of control register. Addr ASP_PADFIFO Pen Sample FIFO 0x00215000 TYPE RESET 0X0000 SAMPLE TYPE RESET 0X0000 MOTOROLA Analog Signal Processor (ASP) 15-15...
Page 298: Clock Divide Register
PADC_CLK PADC Clock Divider—Selects the divide ratio to generate the 0x00 = Clock disabled Bits 4–0 clock for use by the pen ADC. 0x01 = Divider ratio is 2 0x1F = Divider ratio is 32 15-16 MC9328MX1 Reference Manual MOTOROLA...
Page 299: Asp Fifo Pointer Register
Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–5 PEN_FIFO_READ_POINTER PEN_FIFO_READ_POINTER—Holds the read pointer of PADC FIFO. Bit 7–4 PEN_FIFO_WRITE_POINTER PEN_FIFO_WRITE_POINTER—Holds the write pointer of PADC FIFO. Bit 3–0 MOTOROLA Analog Signal Processor (ASP) 15-17...
Page 300 Analog Signal Processor (ASP) 15-18 MC9328MX1 Reference Manual MOTOROLA...
Page 301: Bluetooth Primer
A Bluetooth system consists of a radio unit, a link control unit, and a support unit for link management and host terminal interface functions (see Figure 16-1 on page 16-2). The radio, link controller, and link manager are described in the Specification of the Bluetooth System, version 1.1. MOTOROLA Bluetooth Accelerator (BTA) 16-1...
Page 302: Bta Overview
Sequence Estimation (MLSE/JD) pre-processor for improved RF performance • Bluetooth Application Timer (BAT) • Low-power support IP-bus interface (16-bit Blue-line Standard, version 2.0) • Bluetooth Bluetooth Link Manager Bluetooth Radio Link Controller and I/O Figure 16-1. Functional Blocks in a Bluetooth System 16-2 MC9328MX1 Reference Manual MOTOROLA...
Page 303: Module Descriptions
Bluetooth core can be accessed to write to the control words and to retrieve the status of the Bluetooth core. Within the Bluetooth core, the main functional blocks are: • IP bus interface • Sequencer • Bluetooth pipeline processor MOTOROLA Bluetooth Accelerator (BTA) 16-3...
Page 304: Ip Bus Interface
Refer to Section 16.5.9.1, “Clock Control Register.” Table 16-1. CLK_CONTROL Register Settings for Synchronization BT1_CLK_IN_DIV Value ips_clk (MHz) BT1_WSLOT Value BT1_RSLOT Value 2, (6) 2, (6) 2, (3) 2, (3) 16-4 MC9328MX1 Reference Manual MOTOROLA...
Page 305: Sequencer
Difference between NativeCount and EstimatedCount. NativeClk 3.2 kHz Low (power down) Free-running native clock of the unit. High (operation) When the unit is the master of a communication, the remote slave must synchronize to this clock. MOTOROLA Bluetooth Accelerator (BTA) 16-5...
Page 306: Interrupt Generation
This one-shot interrupt is termed “BTsys.” 2. An interrupt triggered by the Bluetooth application timer termed “BTtim.” 3. An interrupt generated during the wake-up sequence termed “BTwui.” The interrupts are summarized and described in Table 16-3 on page 16-7. 16-6 MC9328MX1 Reference Manual MOTOROLA...
Page 307: Bluetooth Pipeline Processor
HEC/CRC generator and checker • Encryption and decryption engine • Whitening and de-whitening logic • FEC coding and decoding The four units process incoming or outgoing Bluetooth packets. Figure 16-3 shows the format of a Bluetooth packet. MOTOROLA Bluetooth Accelerator (BTA) 16-7...
Page 308: Hec/Crc Generator And Checker
The type information is available from the packet header and length information fields in the payload header field, which is the first one or two bytes of the payload, depending on the packet 16-8 MC9328MX1 Reference Manual MOTOROLA...
Page 309: Table 16-4 Packet Types And Fec/Crc Processing
Disabled Disabled 1100 Disabled Disabled Disabled 1101 Disabled Disabled Disabled 1110 Enabled Disabled Enabled 1111 Enabled Disabled Disabled CRC and 2/3 FEC are performed on the data field only. Not defined in the standard yet. MOTOROLA Bluetooth Accelerator (BTA) 16-9...
Page 310: Encryption And Decryption Engine
Table 16-5. Writing Sequence for Encryption Engine Initialization Word Number Bits 15–8 Bits 7–0 Kc’[1] Kc’[0] Kc’[3] Kc’[2] Kc’[5] Kc’[4] Kc’[7] Kc’[6] Kc’[9] Kc’[8] Kc’[11] Kc’[10] Kc’[13] Kc’[12] Kc’[15] Kc’[14] Addr[1] Addr[0] Addr[3] Addr[2] Addr[5] Addr[4] 16-10 MC9328MX1 Reference Manual MOTOROLA...
Page 311: Whitening/De-Whitening
64-bit “long words,” designated LW0 through LW7. Software views each long word as four concatenated 16 bit words that are accessed independently. Figure 16-4 illustrates the arrangement of the long words in the bit buffer. MOTOROLA Bluetooth Accelerator (BTA) 16-11...
Page 312: Correlator
The threshold for the correlator is programmable via the THRESHOLD register. The correlation peak value in the most recent correlation window can be read from the same register. Software access to the bit buffer is prohibited during correlation because of the bit buffer time sharing (see section 16.3.1.4). 16-12 MC9328MX1 Reference Manual MOTOROLA...
Page 313: Bluetooth Application Timer
In) Register,” on page 16-84 16.3.1.8 Radio Control The radio interface supports two RF front ends: • Motorola Radio, MC13180, SPI Interface • SiliconWave Radio, SiW1502, SPI Interface The selection of the used interface is determined via software by writing to the RF_CONTROL register.
Page 314: Frequency Synthesizer And Timing Control
PWM_TX register while the RSSI value is written to the PWM_RSSI register. 16.3.1.8.3 Radio Module Interfaces MC13180 Radio (3 Wire SPI) The MC13180 radio is programmed via a three wire serial programming interface (SPI) comprised of the spi_data, spi_en, and spi_clk lines. 16-14 MC9328MX1 Reference Manual MOTOROLA...
Page 315: Figure 16-5 Programming Interfaces For The Mc13180 Radio
SPI. Writing to the SPI_READ_ADDR or SPI_WRITE_ADDR register overrides any previous SPI address maintained in that register by the Bluetooth core. The timing of the MC13180 radio is shown in Figure 16-6 on page 16-16. MOTOROLA Bluetooth Accelerator (BTA) 16-15...
Page 316: Figure 16-6 Timing Of The Rf Module Control Signals For The Mc13180 Radio
The radio increments the address of the radio register by one after each write. The mapping of the data written to the SPI_WORD0 through SPI_WORD3 registers in the programming sequence illustrated in Figure 16-7. 16-16 MC9328MX1 Reference Manual MOTOROLA...
Page 317: Figure 16-7 Programming Interface For The Siwave Radio
( 1) Ca n be t ristated depe nding on RF_ Contro l Register BT pa cket dat a Sa me as (1) BT packet data Rx_data SysTick SysTick Idle Idle Figure 16-8. Timing of RF Module Control Signals for the SiWave Radio MOTOROLA Bluetooth Accelerator (BTA) 16-17...
Page 318: Figure 16-9 Block Diagram Of The Wake-Up Module
3. The WAKEUP_4 register holds the value at which the Bluetooth clock is enabled again (BT1ClkHold goes high). After receiving a WU2 event, WAKEUP_4 is updated with the sum of the WU_COUNT and WAKEUP_DELTA4 registers. The WAKEUP_DELTA4 value 16-18 MC9328MX1 Reference Manual MOTOROLA...
Page 319: Pin Configuration For Bta
BTA operation. NOTE: The user must ensure that the data direction bits in the GPIO are set to the correct direction for proper operation. See Section 32.5.1, “Data Direction Registers,” on page 32-9 for details. MOTOROLA Bluetooth Accelerator (BTA) 16-19...
Page 320: Table 16-9 Pin Configuration
For clarification, when the behavior changes significantly, the same address is given two different names. Table 16-10 on page 16-21 summarizes these registers and their addresses. Table 16-11 on page 16-23 provides an alternate view of the memory map 16-20 MC9328MX1 Reference Manual MOTOROLA...
Page 321: Table 16-10 Bta Module Register Memory Map
RF Control Register RF_CONTROL 0x0021605C Write RF Status Register RF_STATUS 0x0021605C Read RX Time Register RX_TIME 0x00216060 Write TX Time Register TX_TIME 0x00216064 Write Bluetooth Application Timer Register 0x00216068 Write Threshold Register THRESHOLD 0x0021606C Write MOTOROLA Bluetooth Accelerator (BTA) 16-21...
Page 322 Write SPI Write Address Register SPI_WRITE_ADDR 0x00216130 Write SPI Read Address Register SPI_READ_ADDR 0x00216134 Write SPI Control Register SPI_CONTROL 0x00216138 Write SPI Status Register SPI_STATUS 0x00216138 Read Hop 0 (Frequency In) Register HOP0 0x00216140 Write 16-22 MC9328MX1 Reference Manual MOTOROLA...
Page 323: Table 16-11 Bta Module Register Overview
NATIVE_COUNT NATIVE_COUNT Clocks 0x00216010 ESTIMATED_COUNT ESTIMATED_COUNT 0x00216014 OFFSET_COUNT OFFSET_COUNT 0x00216018 NATIVECLK_LOW NATIVECLK_LOW 0x0021601C NATIVECLK_HIGH NATIVECLK_HIGH 0x00216020 ESTIMATED_CLK_LOW ESTIMATED_CLK_LOW 0x00216024 ESTIMATED_CLK_HIGH ESTIMATED_CLK_HIGH 0x00216028 OFFSET_CLK_LOW OFFSET_CLK_LOW 0x0021602C OFFSET_CLK_HIGH OFFSET_CLK_HIGH Bluetooth 0x00216030 HECCRC_CONTROL Pipeline 0x00216034 WHITE_CONTROL 0x00216038 ENCRYPTION_CONTROL_X13 MOTOROLA Bluetooth Accelerator (BTA) 16-23...
Page 324 BUF_WORD_2 (LW0) 0x002160F4 BUF_WORD_29 (LW7) BUF_WORD_29 (LW7) 0x002160F8 BUF_WORD_30 (LW7) BUF_WORD_30 (LW7) 0x002160FC BUF_WORD_31 (LW7) BUF_WORD_31 (LW7) Wake-Up 0x00216100 WAKEUP_1 WAKEUP_1 0x00216104 WAKEUP_2 WAKEUP_2 0x0021610C WAKEUP_DELTA4 WAKEUP_4 0x00216110 WU_CONTROL WU_STATUS 0x00216114 WU_COUNT System 0x00216118 CLK_CONTROL CLK_CONTROL 16-24 MC9328MX1 Reference Manual MOTOROLA...
Page 325 0x00216134 SPI_READ_ADDR 0x00216138 SPI_CONTROL SPI_STATUS Frequency 0x00216140 HOP0 HOP_FREQ_OUT Hopping 0x00216144 HOP1 0x00216148 HOP2 0x0021614C HOP3 0x00216150 HOP4 Interrupt 0x00216160 INTERRUPT_VECTOR INTERRUPT_VECTOR Joint 0x00216170 SYNC_METRIC Detection 0x00216174 SYNC_FC Reversing 0x00216178 WORD_REVERSE WORD_REVERSE 0x0021617C BYTE_REVERSE BYTE_REVERSE MOTOROLA Bluetooth Accelerator (BTA) 16-25...
Page 326: Sequencer Registers
Bit 12 to bypass the Bluetooth pipeline module. When bypass is 1 = Bypass Bluetooth pipeline selected (PIPE is set), data flows directly between the Bit Buffer after the header trailer bits and the RF sub-modules. 16-26 MC9328MX1 Reference Manual MOTOROLA...
Page 327: Status Register
BTA. The Status Register bits and their settings are described in Table 16-13 on page 16-28. Addr STATUS Status Register 0x00216000 TYPE RESET 0x0000 MS2LSB REC1 REC2 NREC CRC16 HEC8 STATE BUF_ADDR TYPE RESET 0x0040 MOTOROLA Bluetooth Accelerator (BTA) 16-27...
Page 328: Table 16-13 Status Register Description
(but not including) the long word currently used by the BTA. (It can read up to BUF_ADDR-1) The software must keep track of the last long word accessed. 16-28 MC9328MX1 Reference Manual MOTOROLA...
Page 329: Packet Header Register
ARQN—Defined in the Bluetooth header standard. Bit 8 FLOW FLOW—Defined in the Bluetooth header standard. Bit 7 TYPE TYPE—Defined in the Bluetooth header standard. Bits 6–3 AM_ADDR AM_Addr—Defined in the Bluetooth header standard. Bits 2–0 MOTOROLA Bluetooth Accelerator (BTA) 16-29...
Page 330: Payload Header Register
Reserved—These bits are reserved and should read 0. Bits 31–12 LENGTH Payload Length—Contains a 5- or 9-bit payload length determined by packet type. Bits 11–3 FLOW Flow—Defined in the Bluetooth standard. Bit 2 L_CH Logical Channel—Defined in the Bluetooth standard. Bits 1–0 16-30 MC9328MX1 Reference Manual MOTOROLA...
Page 331: Bluetooth Clocks Registers
Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–12 NATIVE_COUNT Native Count—Contains the NATIVECOUNT counter, which divides the high precision 8 MHz Bits 11–0 clock to generate the 3.2 kHz SYSTICK. MOTOROLA Bluetooth Accelerator (BTA) 16-31...
Page 332: Estimated Count Register
Reserved Reserved—These bits are reserved and should read 0. Bits 31–12 ESTIMATED_COUNT ESTIMATEDCOUNT—Contains the ESTIMATEDCOUNT counter, which is clocked by Bits 11–0 the high precision 8 MHz clock and preset by the access code triggering. 16-32 MC9328MX1 Reference Manual MOTOROLA...
Page 333: Offset Count Register
0x0000 OFFSET_COUNT TYPE RESET 0x0000 Table 16-18. Offset Count Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–12 OFFSET_COUNT Off Set Count—Contains the OFFSETCOUNT, which generates OFFSETCLK. Bits 11–0 MOTOROLA Bluetooth Accelerator (BTA) 16-33...
Page 334: Native Clock Low Register
Table 16-19. Native Clock Low Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 NATIVECLK_LOW Lower Two Bytes of the NATIVECLK—Contains the LSB (bits 15–0) of the 28-bit Bits 15–0 NATIVECLK. 16-34 MC9328MX1 Reference Manual MOTOROLA...
Page 335: Native Clock High Register
Table 16-20. Native Clock High Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–12 NATIVECLK_HIGH High Bits of the NATIVECLK—Contains the MSBs (bits 27–16) of the 28-bit NATIVECLK. Bits 11–0 MOTOROLA Bluetooth Accelerator (BTA) 16-35...
Page 336: Estimated Clock Low Register
Table 16-21. Estimated Clock Low Register Description Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 ESTIMATED_CLK_LOW Lower 2 Bytes of the ESTIMATEDCLK—Contains the LSB (bits 15–0) of the 28-bit Bits 15–0 ESTIMATEDCLK. 16-36 MC9328MX1 Reference Manual MOTOROLA...
Page 337: Estimated Clock High Register
Table 16-22. Estimated Clock High Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–12 ESTIMATED_CLK_HIGH High Bits of the ESTIMATEDCLK—Contains the MSBs (bits 27–16) of the 28-bit Bits 11–0 ESTIMATEDCLK. MOTOROLA Bluetooth Accelerator (BTA) 16-37...
Page 338: Offset Clock Low Register
Table 16-23. Offset Clock Low Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 OFFSET_CLK_LOW Lower 2 Bytes of OFFSETCLK—Contains the LSB (bits 15–0) of the 28-bit OFFSETCLK. Bits 15–0 16-38 MC9328MX1 Reference Manual MOTOROLA...
Page 339: Offset Clock High Register
Table 16-24. Offset Clock High Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–12 OFFSET_CLK_HIGH High Bits of OFFSETCLK—Contains the MSBs (bits 27–16) of the 28-bit OFFSETCLK. Bits 11–0 MOTOROLA Bluetooth Accelerator (BTA) 16-39...
Page 340: Bluetooth Pipeline Registers
Field—Initializes the registers for generating registers. The lower byte (bits 7:0) is the same the check bits for HEC and CRC. for both HEC and CRC while the upper byte (bits 15:8) is all 0s. 16-40 MC9328MX1 Reference Manual MOTOROLA...
Page 341: White Control Register
Reserved Reserved—These bits are reserved and should read 0. Bits 31–7 WHITE_INIT Whitening Unit Initialization Field—Initializes the registers Initialization values for the Bits 6–0 that generate the whitening sequence. registers that generate the whitening sequence. MOTOROLA Bluetooth Accelerator (BTA) 16-41...
Page 342: Encryption Control X13 Register
Reserved—These bits are reserved and should read 0. Bits 31–16 ENCRYPT Encryption Words—Receives a sequence of 13 words to initialize and To disable encryption, do Bits 15–0 set up the encryption engine. not write to this register. 16-42 MC9328MX1 Reference Manual MOTOROLA...
Page 343: Radio Control Registers
Reserved—These bits are reserved and should read 0. Bits 31–10 EST_PRELOAD_TIME Set Correlation Time—Holds the preload time value. The EST_PRELOAD_TIME value Bits 9–0 is loaded into the ESTIMATEDCLK counter when the trigger is asserted during correlation in slave mode. MOTOROLA Bluetooth Accelerator (BTA) 16-43...
Page 344: Correlation Time Stamp Register
RESET 0x0000 Table 16-29. Correlation Time Stamp Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–12 CORR_TIME Get Correlation Time—Indicates the time when the trigger was asserted. Bits 11–0 16-44 MC9328MX1 Reference Manual MOTOROLA...
Page 345: Rf Gpo Register
GPO Data Out—Holds the data value driven out to BT9 when GPO_EN2 is set to Enabled. Bit 1 GPO_DOUT1 GPO Data Out—Holds the data value driven out to BT6 when GPO_EN1 is set to Enabled. Bit 0 MOTOROLA Bluetooth Accelerator (BTA) 16-45...
Page 346: Pwm Received Signal Strength Indicator Register
MC13180 radios. When read, returns the RSSI digitized by the BTA. The returned value will either be the peak RSSI value or the current RSSI value, depending on the value of the PEAK_HLD bit in the RF Control Register. 16-46 MC9328MX1 Reference Manual MOTOROLA...
Page 347: Table 16-32 Time A & B Register Description
Time B—Sets the Timing B of the signals interfacing to the RF module. The timing unit is Bits 15–8 expressed in “µs before the next SYSTICK”. TIME_A Time A—Sets the Timing A of the signals interfacing to the RF module. Bits 7–0 MOTOROLA Bluetooth Accelerator (BTA) 16-47...
Page 348: Table 16-33 Time C & D Register Description
Time C—Sets the timing C of the signals The timing unit is expressed in “µs before the next Bits 4–0 interfacing to the RF module. SYSTICK”. See Figure 16-8 on page 16-17 for more details. 16-48 MC9328MX1 Reference Manual MOTOROLA...
Page 349: Pwm Tx Register
Table 16-34. PWM TX Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–6 PWM_TX Pulse Width Modulation—Sets the PWM for transmit power control. Bits 5–0 Note: This applies to the MC13180 radio only. MOTOROLA Bluetooth Accelerator (BTA) 16-49...
Page 350: Rf Control Register
Antenna Diversity Selection—Selects the 0 = Antenna 0 Bit 10 antenna. 1 = Antenna 1 Selection—Selects the operation (either diversity 0 = Oscillator enable operation Bit 9 selection or oscillator enable) of BT7 pin. 1 = Diversity selection 16-50 MC9328MX1 Reference Manual MOTOROLA...
Page 351 DELAY_HOP_STROBE Delay HOP Strobe—Delays the HOP strobe on 000 = No delay Bits 2–0 BT9 in the SiliconWave radio. 001 = 2µs 010 = 4µs 100 = 8µs 111 = 15µs All other settings reserved MOTOROLA Bluetooth Accelerator (BTA) 16-51...
Page 352: Rf Status Register
0 = Antenna 0 Bit 10 antenna currently used. 1 = Antenna 1 Selection—Indicates the operation (either 0 = Oscillator enable operation Bit 9 diversity selection or oscillator enable) of BT7 pin. 1 = Diversity selection 16-52 MC9328MX1 Reference Manual MOTOROLA...
Page 353 1 = Generate spike on EOF DELAY_HOP_STROBE Delay HOP Strobe—Delays the HOP strobe on 000 = No delay Bits 2–0 BT9 in the SiliconWave radio. 001 = 2µs 010 = 4µs 100 = 8µs 111 = 15µs MOTOROLA Bluetooth Accelerator (BTA) 16-53...
Page 354: Rx Time Register
00000 to 11000, which means that clock that counts from 0 (0x000) to 2499 (x9C3). The the search window start time ranges RX_TIME_START field defines the bits x. from 288µs and 312µs. MS_CLK [11:0] = 1001 xxxx x000. 16-54 MC9328MX1 Reference Manual MOTOROLA...
Page 355: Tx Time Register
00000 to 11000, which counts from 0 (0x000) to 2499 (x9C3). The means that the search window TX_TIME_START field defines the bits x. start time ranges from 288 µs MS_CLK [11:0] = 1001 xxxx x000. and 312 µs. MOTOROLA Bluetooth Accelerator (BTA) 16-55...
Page 356: Timer Register
Preset value written to the Bits 11–0 Bluetooth application timer. The timer is clocked by the 8 MHz application timer clock. An interrupt is issued after the count is reached and automatic reloading is performed. 16-56 MC9328MX1 Reference Manual MOTOROLA...
Page 357: Correlator Registers
Bits 31–8 THRESHOLD_II Signal Energy—Sets the clipping level for the access code Default setting is 0.5625 Bits 7–4 correlation. THRESHOLD_I Threshold Value—Sets the threshold value for the access code Default setting is 1.25 Bits 3–0 correlation. MOTOROLA Bluetooth Accelerator (BTA) 16-57...
Page 358: Table 16-41 Threshold Register Description (Siliconwave)
0.8125 0.68750 0.8750 0.71875 0.9375 0.75000 1.0000 0.78125 1.0625 0.81250 1.1250 0.84375 1.1875 0.87500 1.2500 0.90625 1.3125 0.93750 1.3750 0.96875 1.4375 Note: Levels vary according to the values written to the THRESHOLD_I and THRESHOLD_II fields. 16-58 MC9328MX1 Reference Manual MOTOROLA...
Page 359: Correlation Max Register
Table 16-43. Correlation Max Register Description Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–9 VALUE Maximum Correlation Value—Contains the maximum correlation value during the correlation Bits 8–0 phase. Note: N/A in MC13180 mode. MOTOROLA Bluetooth Accelerator (BTA) 16-59...
Page 360: Synch Word 0 Register
Table 16-44. Synch Word 0 Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 WORD Part of Synchronization Code—Receives bits [15:0] of the 64-bit access code for the correlation. Bits 15–0 16-60 MC9328MX1 Reference Manual MOTOROLA...
Page 361: Synch Word 1 Register
Table 16-45. Synch Word 1 Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 WORD Part of Synchronization Code—Receives bits [31:16] of the 64-bit access code for the correlation. Bits 15–0 MOTOROLA Bluetooth Accelerator (BTA) 16-61...
Page 362: Synch Word 2 Register
Part of Synchronization Code—Receives bits [47:32] of the 64-bit access code for the correlation. Bits 15–0 16.5.6.6 Synch Word 3 Register The write-only Synch Word 3 Register bits are explained in Table 16-47. Addr SYNCH_WORD_3 Synch Word 3 Register 0x0021607C TYPE RESET 0x0000 WORD TYPE RESET 0xDA25 16-62 MC9328MX1 Reference Manual MOTOROLA...
Page 363: Bit Buffer Registers
0x002160FC TYPE RESET 0x0000 WORD TYPE RESET 0x0000 Table 16-48. Buf Word 0 (LW0) Register to Buf Word 31 (LW7) Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 MOTOROLA Bluetooth Accelerator (BTA) 16-63...
Page 364: Table 16-49 Bit Buffer Registers Numbers And Addresses
Register Register Register 0x00216080 0x002160B0 0x002160E0 0x00216084 0x002160B4 0x002160E4 0x00216088 0x002160B8 0x002160E8 0x0021608C 0x002160BC 0x002160EC 0x00216090 0x002160C0 0x002160F0 0x00216094 0x002160C4 0x002160F4 0x00216098 0x002160C8 0x002160F8 0x0021609C 0x002160CC 0x002160FC 0x002160A0 0x002160D0 0x002160A4 0x002160D4 0x002160A8 0x002160D8 0x002160AC 0x002160DC 16-64 MC9328MX1 Reference Manual MOTOROLA...
Page 365: Wake-Up Registers
Reserved—These bits are reserved and should read 0. Bits 31–2 TIME Value for Wake-Up Timer 1—Sets wake-up timer 1 for low-power Recommend using Bits 1–0 operation. The timer is clocked by the 32 kHz clock. values greater than 1. MOTOROLA Bluetooth Accelerator (BTA) 16-65...
Page 366: Wake-Up 2 Register
2 for low-power operation. specified (WU_COUNT = WAKEUP_2). The timer is clocked by the 32 kHz clock. Writing 0x0000 to this register disables timed wake-up, and only an external event will wake up the BTA. 16-66 MC9328MX1 Reference Manual MOTOROLA...
Page 367: Wake-Up Delta4 Register
Reserved—These bits are reserved and should read 0. Bits 31–10 TIME Delta Value for Wake-Up Timer 4—Sets the wake-up timer delta value that is added to the Bits 9–0 WU_COUNT value after a wake-up event. MOTOROLA Bluetooth Accelerator (BTA) 16-67...
Page 368: Wake-Up 4 Register
Table 16-53. Wake-Up 4 Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 TIME Value for Wake-Up Timer 4—Contains the time value when the Bluetooth master clock was started. Bits 15–0 16-68 MC9328MX1 Reference Manual MOTOROLA...
Page 369: Wakeup Control Register
Wake-Up Counter Reset—Resets the wake-up counter in 0 = Do not reset the wake-up counter Bit 3 the wake up module. 1 = Reset the wake-up counter Reserved Reserved—These bits are reserved and should read 0. Bits 2–0 MOTOROLA Bluetooth Accelerator (BTA) 16-69...
Page 370: Wake-Up Status Register
Bluetooth Clock—Indicates the status of the Bluetooth Clock 0 = BT clock running Bit 1 1 = BT clock stopped Power Down Enable—Indicates status of power down enable 0 = Power down disabled Bit 0 function. 1 = Power down enabled 16-70 MC9328MX1 Reference Manual MOTOROLA...
Page 371: Wake-Up Count Register
Table 16-56. Wake-Up Count Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 COUNT Counter Value—Holds the count value used by the comparators in the wake-up units to trigger Bits 15–0 wake-up interrupts. MOTOROLA Bluetooth Accelerator (BTA) 16-71...
Page 372: System Register
Reserved—These bits are reserved and should read 0. Bits 3–2 BT1_CLK_IN_DIV BT1 Clock In Frequency Divider Select—Selects the frequency 00 = Idle Bits 1–0 division of the BT1 clock in. 01 = 16 10 = 24 11 = 32 16-72 MC9328MX1 Reference Manual MOTOROLA...
Page 373: Spi Registers
The start address is written to the SPI Read Address Register before reads are performed or to the SPI Write Address Register after writes are performed. MOTOROLA Bluetooth Accelerator (BTA) 16-73...
Page 374: Spi Word1 Register
Table 16-60. SPI Word1 Register Description (MC13180) Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 WORD1 Word of Data—Contains word 1 of the data read from or written to the RF module Bits 15–0 16-74 MC9328MX1 Reference Manual MOTOROLA...
Page 375: Spi Word2 Register
Word of Data—Contains word 2 of the data read from or written to the RF module. Bits 15–0 Table 16-63. SPI Word2 Register Description (SiliconWave) Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 MOTOROLA Bluetooth Accelerator (BTA) 16-75...
Page 376: Spi Word3 Register
Word of Data—Contains word 3 of the data read from or written to the RF module. Bits 15–0 Table 16-65. SPI Word3 Register Description (SiliconWave) Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 BYTE6 Byte 6—Contents vary according to the RF module used. Bits 15–8 16-76 MC9328MX1 Reference Manual MOTOROLA...
Page 377: Spi Write Address Register
Set to 0. Bit 7 ADDRESS Radio Register Address—Contains the address of the first radio register that the buffered SPI Bits 6–0 Word0 Register entries are written to. The address is automatically post-incremented in the radio register. MOTOROLA Bluetooth Accelerator (BTA) 16-77...
Page 378: Spi Read Address Register
ADDRESS (SiliconWave) TYPE RESET 0x0000 Table 16-68. SPI Read Address Register Description (MC13180) Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 Don’t Care Don’t Care—Ignored by the BTA. Bits 15–8 16-78 MC9328MX1 Reference Manual MOTOROLA...
Page 379: Spi Control Register
SPI clock. Reading address 0x00216138 returns the SPI Status Register (see section 16.5.10.8). The SPI Control Register bits are explained in Table 16-70. Addr SPI_CONTROL SPI Control Register 0x00216138 TYPE RESET 0x0000 BYTE_ONLY SPI_CLKINV SPI_CLKDIV3 SPI_CLKDIV2 SPI_CLKDIV1 SPI_MODE TYPE RESET 0x0000 MOTOROLA Bluetooth Accelerator (BTA) 16-79...
Page 380: Figure 16-11 Spi Clock Dividers Determine Duty Cycle Of Spi Clock
SPI Mode Selection—Sets SPI mode according to the radio 011 = MC13180 Bits 2–0 used. 100 = SiliconWave All Other Settings Reserved SPI State SPI_EN SPI_CLK Figure 16-11. SPI Clock Dividers Determine Duty Cycle of SPI Clock 16-80 MC9328MX1 Reference Manual MOTOROLA...
Page 381: Spi Status Register
Reading address 0x00216140 returns the Hop Frequency Out Register (see section 16.5.11.6). The read-only Hop Frequency Out Register returns the partially computed hopping frequency channel based on the sequence written to the Hopping Frequency Registers. The Register bits are explained in Table 16-72 through Table 16-76. MOTOROLA Bluetooth Accelerator (BTA) 16-81...
Page 382: Hop 1 (Frequency In) Register
CLK0 is written but ignored by the Bluetooth core as frequency. it is not required by the standard 16.5.11.2 Hop 1 (Frequency In) Register Addr HOP1 Hop 1 (Frequency In) Register 0x00216144 TYPE RESET 0x0000 CLK_HIGH TYPE RESET 0x0000 16-82 MC9328MX1 Reference Manual MOTOROLA...
Page 383: Hop 2 (Frequency In) Register
Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 LAPUAP_LOW Lower Part of the Combined LAP and 4 LSBs of UAP—Contains ADDR [15:0] of the LAP Bits 15–0 bits [15:0] of the LAP. MOTOROLA Bluetooth Accelerator (BTA) 16-83...
Page 384: Hop 4 (Frequency In) Register
UAP—Contains bits [23:16] of the LAP and bits 3-0 of the UAP. and ADDR [3:0] of the UAP 16.5.11.5 Hop 4 (Frequency In) Register Addr HOP4 Hop 4 (Frequency In) Register 0x00216150 TYPE RESET 0x0000 STATE TYPE RESET 0x0000 16-84 MC9328MX1 Reference Manual MOTOROLA...
Page 385: Hop Frequency Out Register
Hopping Frequency Registers have been Software is expected to complete the addition written. Software must complete the computation of of F (see the Bluetooth specifications) and the hop frequency channel. also the modulo operation. MOTOROLA Bluetooth Accelerator (BTA) 16-85...
Page 386: Interrupt Register
See Section 16.5.1, “Sequencer Registers.” Write 1 = EOH interrupt clear. SYSTICK SYSTICK Interrupt—Indicates whether a SYSTICK of the current clock 0 = No SYSTICK Bit 0 has occurred. Write to clear. interrupt 1 = SYSTICK interrupt 16-86 MC9328MX1 Reference Manual MOTOROLA...
Page 387: Joint Detect Registers
SYNC_METRIC TYPE RESET 0x0000 Table 16-79. Synchronization Metric Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–15 SYNC_METRIC Synchronization Metric—Indicates the peak value of the correlation energy. Bits 14–0 MOTOROLA Bluetooth Accelerator (BTA) 16-87...
Page 388: Synchronize Frequency Carrier Register
16.5.14.1 Word Reverse Register The Word Reverse Register is written with the 16-bit word to be bit reversed. When read, the register gives the bit reversed word. The Word Reverse Register bits are explained in Table 16-81. 16-88 MC9328MX1 Reference Manual MOTOROLA...
Page 389: Byte Reverse Register
The Byte Reverse Register (BYTE_REVERSE) is written with the byte to be bit reversed. On reading the register gives the bit reversed word. The Byte Reverse Register register bits are explained in Table 16-82. Addr BYTE_REVERSE Byte Reverse Register 0x0021617C TYPE RESET 0x0000 BYTE_REVERSED TYPE RESET 0x0000 MOTOROLA Bluetooth Accelerator (BTA) 16-89...
Page 390: Table 16-82 Byte Reverse Register Description
Byte to be Bit Reversed—Receives the byte This register is written with the byte to be Bits 7–0 to be bit reversed. bit reversed. Byte Reversed—Receives the bit reversed When read, it gives the bit reversed byte. byte. 16-90 MC9328MX1 Reference Manual MOTOROLA...
Page 391: Mma Operation
ARM920T processor. LCDC access to the eSRAM has the highest priority, followed by ARM920T processor access, and finally MMA access. For this reason, data access latency of the MMA to the eSRAM can be as long as the LCDC data burst access. MOTOROLA Multimedia Accelerator (MMA) 17-1...
Page 392: Basic Mac Operation
The MMA resumes operation if there are no other eSRAM access requests pending. Circular buffer operation for the X registers is shown in Figure 17-2 on page 17-3. 17-2 MC9328MX1 Reference Manual MOTOROLA...
Page 393: Cache
1 to the CACHE CLR bit. This action also registers the base address of the 2K boundary as the valid cache block address. The user must program the MMA_MAC_XBASE register and the MMA_MAC_XINDEX register before clearing the cache. MOTOROLA Multimedia Accelerator (MMA) 17-3...
Page 394: Dct/Idct
DCT/iDCT is performed automatically. When the process is complete, an interrupt is generated and the DCT ENA bit is cleared. In this way, a DCT/iDCT can be run for an entire frame of data. 17-4 MC9328MX1 Reference Manual MOTOROLA...
Page 395: Table 17-1 Mma Module Register Memory Map
MMA MAC Y Index Register MMA_MAC_YINDEX 0x00222304 MMA MAC Y Length Register MMA_MAC_YLENGTH 0x00222308 MMA MAC Y Modify Register MMA_MAC_YMODIFY 0x0022230C MMA MAC Y Increment Register MMA_MAC_YINCR 0x00222310 MMA MAC Y Count Register MMA_MAC_YCOUNT 0x00222314 MMA DCT/iDCT Registers MOTOROLA Multimedia Accelerator (MMA) 17-5...
Page 396: Mma Mac Control Registers
0x0000 Table 17-2. MMA MAC Module Register Description Name Description Settings Software Reset for the MAC—indicates whether the reset sequence 0 = Reset is complete Bit 31 is complete. 1 = Reset is in progress 17-6 MC9328MX1 Reference Manual MOTOROLA...
Page 397: Mma Mac Control Register
MMA_MAC_XINDEX register in the XDAC module is incremented incremented by the value in the MMA_MAC_XINCR 1 = MMA_MAC_XINDEX register register for every (MMA_MAC_XCOUNT + 1) iteration. is incremented X INDEX INCR is used with X INDEX LOAD. MOTOROLA Multimedia Accelerator (MMA) 17-7...
Page 398 1 = Y operand sign is alternated Y SIGN INI Y Operand Initial Sign—Determines whether the Y 0 = +(y) Bit 17 operand initial sign of the operation with y. 1 = -(y) 17-8 MC9328MX1 Reference Manual MOTOROLA...
Page 399: Mma Mac Multiply Counter Register
Reserved—These bits are reserved and should read 0. Bits 31–16 MULT COUNTER Multiply Counter—Determines the number of multiply operations that the MAC module Bits 15–0 performs. For proper operation, this value must be an integer multiple of the (MMA_MAC_ACCU + 1) value. MOTOROLA Multimedia Accelerator (MMA) 17-9...
Page 400: Mma Mac Accumulate Counter Register
1 (0x0003 for four accumulate operations). 17.3.1.5 MMA MAC Interrupt Register Addr MMA_MAC_INTR MMA MAC Interrupt Register 0x00222010 TYPE RESET 0x0000 FIFO FIFO FIFO ERROR EMPT HALF FULL TYPE RESET 0x0004 17-10 MC9328MX1 Reference Manual MOTOROLA...
Page 401: Mma Mac Interrupt Mask Register
OP ERROR Mask—Masks the OP ERROR Interrupt. 0 = Mask on/enable interrupt Bit 4 1 = Mask off/disable interrupt. OP END Operation End Interrupt Mask—Masks the OP END interrupt. 0 = Mask on/enable interrupt Bit 3 1 = Mask off/disable interrupt MOTOROLA Multimedia Accelerator (MMA) 17-11...
Page 402: Mma Mac Fifo Register
Addr MMA_MAC_FIFO MMA MAC FIFO Register 0x00222018 FIFO REGISTER TYPE RESET 0x0000 FIFO REGISTER TYPE RESET 0x0000 Table 17-8. MMA MAC FIFO Register Description Name Description FIFO REGISTER FIFO Read Register—Returns FIFO output. Bits 31–0 17-12 MC9328MX1 Reference Manual MOTOROLA...
Page 403: Mma Mac Fifo Status Register
Bit 2 interrupt. FIFO HALF FIFO Half Full Status—Indicates the status of the FIFO HALF See description Bit 1 interrupt. FIFO FULL FIFO Full Status—Indicates the status of the FIFO FULL interrupt. See description Bit 0 MOTOROLA Multimedia Accelerator (MMA) 17-13...
Page 404: Mma Mac Burst Count Register
This feature ensures that the MMA does not hold the memory bus for too long. 17.3.1.10 MMA MAC Bit Select Register Addr MMA_MAC_BITSEL MMA MAC Bit Select Register 0x00222024 TYPE RESET 0x0000 BITSEL TYPE RESET 0x0000 17-14 MC9328MX1 Reference Manual MOTOROLA...
Page 405: Mma Mac Xy Count Accumulate Register
The initial access by the XDAC is a cache miss, so the operand is fetched from memory and stored in the cache. Subsequent accesses to the same location cause cache hits, so the data is loaded from the cache instead of from memory. MOTOROLA Multimedia Accelerator (MMA) 17-15...
Page 406: Mma Mac X Base Address Register
MMA_MAC_XINDEX MMA MAC X Index Register 0x00222204 TYPE RESET 0x0000 XINDEX TYPE RESET 0x0000 Table 17-13. MMA MAC X Index Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 17-16 MC9328MX1 Reference Manual MOTOROLA...
Page 407: Mma Mac X Length Register
Writing 0 to this register will disable the wrapping of address. Note: Note: If the current Address_Index is 12 and the LENGTH is 16, MMA_MAC_XMODIFY is 8, then the next Address_Index will be (12+8)% 16 == 4. The physical address is 4 + MMA_MAC_XBASE. MOTOROLA Multimedia Accelerator (MMA) 17-17...
Page 408: Mma Mac X Modify Register
X Increment—Determines the size of the increment to the X Address Index after each iteration. Bits 15–0 17.3.3.5 MMA MAC X Increment Register Addr MMA_MAC_XINCR MMA MAC X Increment Register 0x00222210 TYPE RESET 0x0000 XINCR TYPE RESET 0x0000 17-18 MC9328MX1 Reference Manual MOTOROLA...
Page 409: Mma Mac X Count Register
17.3.4 MMA MAC Y Register Control Registers There are six registers that reside in the Y operand Data Access Controller (YDAC). The YDAC does not have a cache, so it always fetches data from memory. MOTOROLA Multimedia Accelerator (MMA) 17-19...
Page 410: Mma Mac Y Base Address Register
MMA_MAC_YINDEX MMA MAC Y Index Register 0x00222304 TYPE RESET 0x0000 YINDEX TYPE RESET 0x0000 Table 17-19. MMA MAC Y Index Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 17-20 MC9328MX1 Reference Manual MOTOROLA...
Page 411: Mma Mac Y Length Register
Writing 0 to this register will disable the wrapping of address. Note: Note: If the current Address_Index is 12 and the LENGTH is 16, MMA_MAC_YMODIFY is 8, then the next Address_Index will be (12+8)% 16 == 4. The physical address is 4 + MMA_MAC_YBASE. MOTOROLA Multimedia Accelerator (MMA) 17-21...
Page 412: Mma Mac Y Modify Register
Y Increment—Determines the size of the increment to the Y Address Index after each iteration. Bits 15–0 17.3.4.5 MMA MAC Y Increment Register Addr MMA_MAC_YINCR MMA MAC Y Increment Register 0x00222310 TYPE RESET 0x0000 YINCR TYPE RESET 0x0000 17-22 MC9328MX1 Reference Manual MOTOROLA...
Page 413: Mma Mac Y Count Register
Y INDEX LOAD bit is set) • increment MMA_MAC_YINDEX by the value in MMA_MAC_YINCR (when the Y INDEX INCR bit is set). The value written to this register is the actual value minus 1 (0x0003 for four iterations). MOTOROLA Multimedia Accelerator (MMA) 17-23...
Page 414: Mma Dct/Idct Registers
0 = No effect Bit 5 1 = Resets DCT module DCTBYPASS DCT Bypass—Enables DCT/iDCT input data to be 0 = Perform transform Bit 4 bypassed to the output without being transformed. 1 = Bypass 17-24 MC9328MX1 Reference Manual MOTOROLA...
Page 415: Dct/Idct Version Register
DCT/iDCT Version Register 0x00222404 VERSION NUMBER TYPE RESET 0x0000 VERSION NUMBER TYPE RESET 0x0000 Table 17-25. DCT/iDCT Version Register Description Name Description VERSION NUMBER Version Number—Contains the version number of the DCT/iDCT block. Bits 31–0 MOTOROLA Multimedia Accelerator (MMA) 17-25...
Page 416: Dct/Idct Irq Enable Register
1 = Interrupt enabled DCTCOMP DCT Complete—Enables/Disables interrupt generation when the DCT 0 = Interrupt disabled × Bit 0 block completes a set of 8 8 transforms. 1 = Interrupt enabled 17-26 MC9328MX1 Reference Manual MOTOROLA...
Page 417: Dct/Idct Irq Status Register
Write a 1 to clear. occurred 1 =Data In interrupt has not occurred DCTCOMP Transform Complete—Indicates whether a transform has 0 = Transform is not complete Bit 0 completed. Write a 1 to clear. 1 = Transform is complete MOTOROLA Multimedia Accelerator (MMA) 17-27...
Page 418: Dct/Idct Source Data Address
Addr MMA_DCTDESDATA Address 0x00222414 DCT_DES_ADDR TYPE RESET 0x0000 DCT_DES_ADDR TYPE RESET 0x0000 Table 17-29. DCT/iDCT Destination Data Address Register Description Name Description DCT_DES_ADDR DCT Destination Address—Determines the destination address for the transformed data. Bits 31–0 17-28 MC9328MX1 Reference Manual MOTOROLA...
Page 419: Dct/Idct X-Offset Address
[MMA_DCTSRCDATA or MMA_DCTDESDATA] + (X-OFFSET × N) where N = 1, …(X-COUNT – 1) along the X-direction. 17.3.5.8 DCT/iDCT Y-Offset Address Addr MMA_DCTYOFF DCT/iDCT Y-Offset Address 0x0022241C TYPE RESET 0x0000 Y-OFFSET TYPE RESET 0x0000 MOTOROLA Multimedia Accelerator (MMA) 17-29...
Page 420: Dct/Idct Xy Count
Y Count—Controls the number of blocks to be transformed in the Y direction. Bits 14–8 Reserved Reserved—This bit is reserved and should read 0. Bit 7 X-COUNT X Count—Controls the number of blocks to be transformed in the X direction. Bits 6–0 17-30 MC9328MX1 Reference Manual MOTOROLA...
Page 421: Dct/Idct Skip Address
Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 SKIP_ADDR SKIP_ADDR—Determines the number of bytes to skip in the X direction when accessing Bits 15–0 each successive row in a block of data. MOTOROLA Multimedia Accelerator (MMA) 17-31...
Page 422: Dct/Idct Data Fifo
Data—Stores input data to be transformed and the outputs the data after transformation. Writing to Bits 31–0 this register stores input data in the FIFO. Reading this register retrieves the results of the transformation from the FIFO. The FIFO is 32 × 32–bits. 17-32 MC9328MX1 Reference Manual MOTOROLA...
Page 423: Spi Block Diagram
The block diagram shown in Figure 18-1 on page 18-2 is the same for each SPI module, except that the SPI 2 module does not support the SPI_RDY control signal function. MOTOROLA Serial Peripheral Interface Modules (SPI 1 and SPI 2) 18-1...
Page 424: Phase And Polarity Configurations
In Phase 1 operation (PHA=1) and SCLK Polarity active high (POL=1), output data changes on falling edges of the SCLK signal and input data is shifted in on rising edges. The MSB is output when the CPU loads the transmitted data. 18-2 MC9328MX1 Reference Manual MOTOROLA...
Page 425: Signals
The user must ensure that the data direction bits in the GPIO are set to the correct direction for proper operation. See Section 32.5.1, “Data Direction Registers,” on page 32-9 for details. MOTOROLA Serial Peripheral Interface Modules (SPI 1 and SPI 2) 18-3...
Page 426: Table 18-2 Spi Pin Configuration
SPI 1 pins must only be configured if SPI 1 is being used. SPI 2 pins must only be configured if SPI 2 is being used. Only one of the two pins must be set-up for the SPI 2 signal. 18-4 MC9328MX1 Reference Manual MOTOROLA...
Page 427: Table 18-3 Spi Module Register Memory Map
0x0021900C SPI 2 Test Register TESTREG2 0x00219010 SPI 2 Sample Period Control Register PERIODREG2 0x00219014 SPI 2 DMA Control Register DMAREG2 0x00219018 SPI 2 Soft Reset Register RESETREG2 0x0021901C MOTOROLA Serial Peripheral Interface Modules (SPI 1 and SPI 2) 18-5...
Page 428: Receive (Rx) Data Registers
Bits 31–16 DATA DATA—Holds the top word of data received into the FIFO. Not valid when the Receive Data Ready Bits 15–0 (RR) bit in the corresponding Interrupt Control/Status Register (INTREG1 or INTREG2) is cleared. 18-6 MC9328MX1 Reference Manual MOTOROLA...
Page 429: Transmit (Tx) Data Registers
Bits 9-0 are shifted out and bits 15-10 are ignored. When the SPI module is operating in slave mode, ‘0’s are shifted out when the FIFO is not full. MOTOROLA Serial Peripheral Interface Modules (SPI 1 and SPI 2)
Page 430: Control Registers
SPI_RDY control signal function, DRCTL must be written with 00 in CONTROLREG2. MODE SPI Mode Select—Selects the mode for the SPI 1 0 = Slave mode Bit 10 module. In CONTROLREG2, MODE is set by the 1 = Master mode hardware. 18-8 MC9328MX1 Reference Manual MOTOROLA...
Page 431 Controls the number of bits in a receive data word (in slave mode and when the SSCTL bit is 0). When the SSCTL bit is 1, this field is “don’t care.” MOTOROLA Serial Peripheral Interface Modules (SPI 1 and SPI 2) 18-9...
Page 432: Table 18-7 Spi 1 Interrupt Control/Status Register And Spi 2 Interrupt Control/Status Register Description
TXFIFO Half Interrupt Enable—Enables/Disables the 0 = Disable interrupt Bit 9 TXFIFO Half-Empty Interrupt. 1 = Enable interrupt TEEN TXFIFO Empty Interrupt Enable—Enables/Disables the 0 = Disable interrupt Bit 8 TXFIFO Empty Interrupt. 1 = Enable interrupt 18-10 MC9328MX1 Reference Manual MOTOROLA...
Page 433 1 = The TXFIFO is empty, however data shifting may still be on-going. To be sure no data transaction is on-going, check the XCH bit(s) in the Control Register(s). MOTOROLA Serial Peripheral Interface Modules (SPI 1 and SPI 2) 18-11...
Page 434: Test Registers
0100 = 4 data words in RXFIFO 0101 = 5 data words in RXFIFO 0110 = 6 data words in RXFIFO 0111 = 7 data words in RXFIFO 1000 = 8 data words in RXFIFO 18-12 MC9328MX1 Reference Manual MOTOROLA...
Page 435: Table 18-9 Spi 1 Sample Period Control Register And Spi 2 Sample Period Control Register Description
Wait—Determines the number of clocks inserted between data 0x0000 = 0 clock Bits 14–0 transactions (when operating in master mode). 0x0001 = 1 clock 0x0002 = 2 clocks … 0x7FFF = 32768 clocks MOTOROLA Serial Peripheral Interface Modules (SPI 1 and SPI 2) 18-13...
Page 436: Dma Control Registers
Control Registers. RFDMA RXFIFO Full Status—Indicates when the 0 = There are less than 8 data words in the RXFIFO Bit 5 receive FIFO is full. 1 = There are 8 data words in the RXFIFO 18-14 MC9328MX1 Reference Manual MOTOROLA...
Page 437: Table 18-10 Spi 1 Dma Control Register
Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–1 START Start—Executes soft reset. 0 = No soft reset Bit 0 1 = Soft reset MOTOROLA Serial Peripheral Interface Modules (SPI 1 and SPI 2) 18-15...
Page 438 Serial Peripheral Interface Modules (SPI 1 and SPI 2) 18-16 MC9328MX1 Reference Manual MOTOROLA...
Page 439: Table 19-1 Supported Panel Characteristics
16, 256 12, 16 12, 16 4096, 64K • Standard panel interface for common LCD drivers • Panel interface of 16-, 12-, 8-, 4-, 2-, and 1-bit-wide LCD panel data bus for monochrome or color panels MOTOROLA LCD Controller 19-1...
Page 440: Lcdc Operation
19.3 LCDC Operation 19.3.1 LCD Screen Format The number of pixels forming the screen width and screen height of the LCD panel are software programmable. Figure 19-2 shows the relationship between the screen size and memory window. 19-2 MC9328MX1 Reference Manual MOTOROLA...
Page 441: Panning
The updates take effect on the next frame. 19.3.3 Display Data Mapping The LCDC supports 1/2/4 bpp in monochrome mode and 4/8/12/16 bpp in color mode. System memory data mapping in 2/4/8/12/16 bpp modes is shown in Figure 19-4 and in Figure 19-5. MOTOROLA LCD Controller 19-3...
Page 442: Figure 19-3 Pixel Location On Display Screen
In 12 bpp mode, 16 bits of memory are used for each set of 12 bits, leaving 4 bits unused. In 16 bpp mode, all 16 bits are used. Refer to Figure 19-5 and Table 19-7 LCD Screen Figure 19-3. Pixel Location on Display Screen 19-4 MC9328MX1 Reference Manual MOTOROLA...
Page 443: Figure 19-4 Display Data Mapping, 1/2/4/8 Bpp Modes
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P0 = Red0Green0Blue0 P1 = Red1Green1Blue1 Figure 19-4. Display Data Mapping, 1/2/4/8 bpp Modes MOTOROLA LCD Controller 19-5...
Page 444: Table 19-2 Display Mapping In 12 Bpp, Cstn Panel, Little Endian
Green1 [2] Green1 [1] Green1 [0] Blue1 [4] Blue1 [3] Blue1 [2] Blue1 [1] Blue1 [0] Table 19-3. Display Mapping in 12 bpp, CSTN Panel, Little Endian Byte Address Bit-to-Pixel Mapping – – – – – – – – PO = RGBo P1= RGB 19-6 MC9328MX1 Reference Manual MOTOROLA...
Page 445: Black-And-White Operation
A logarithmic scale such as 0, 1/4, 1/2 and 1 might be more pleasing than a linearly spaced scale such as 0, 5/16, 11/16 and 1 for certain graphics. Figure 19-6 illustrates gray-scale pixel generation. The flexible mapping scheme allows the user to optimize the visual effect for a specific panel or application. MOTOROLA LCD Controller 19-7...
Page 446: Color Generation
For active matrix displays, the 16-bit RGB code from the mapping RAM is output to the panel. For passive color display, the maximum color depth is 12-bit and 16-bit color is not supported. Figure 19-7 and Figure 19-8 on page 19-9 illustrate passive matrix and active matrix color pixel generation. 19-8 MC9328MX1 Reference Manual MOTOROLA...
Page 447: Figure 19-7 Passive Matrix Color Pixel Generation
0 1 0 1 0 1 1 0 1 1 1 0 1 Color Inside LCDC 256 rows 1 0 0 1 1 1 1 0 0 To Panel Figure 19-8. Active Matrix Color Pixel Generation MOTOROLA LCD Controller 19-9...
Page 448: Frame Rate Modulation Control (Frc)
Note: Overbars indicate repeating decimal numbers. 19.3.8 Panel Interface Signals and Timing The LCDC continuously provides pixel data to the LCD panel via the LCD panel interface. Panel interface signals are illustrated in Figure 19-9. 19-10 MC9328MX1 Reference Manual MOTOROLA...
Page 449: Pin Configuration For Lcdc
2. Clear bit 11 of Port D General Purpose Register (GPR_D) SPL_SPR Primary function of 1. Clear bit 10 of Port D GPIO In Use Register (GIUS_D) GPIO Port D [10] 2. Clear bit 10 of Port D General Purpose Register (GPR_D) MOTOROLA LCD Controller 19-11...
Page 450: Passive Matrix Panel Interface Signals
[0,236] [0,m-8] [0,m-4] [0,1] [0,5] [0,9] [0,233] [0,237] [0,m-7] [0,m-3] [0,2] [0,6] [0,10] [0,234] [0,238] [0,m-6] [0,m-2] [0,3] [0,7] [0,11] [0,235] [0,239] [0,m-5] [0,m-1] Figure 19-10. LCDC Interface Timing for 4-bit Data Width Gray-Scale Panels 19-12 MC9328MX1 Reference Manual MOTOROLA...
Page 451: Passive Panel Interface Timing
H_WIDTH (horizontal sync pulse width) defines the width of the FLM pulse, and H_WIDTH must be at least 1. • H_WAIT_2 defines the delay from the end of LP to the beginning of data output. NOTE: All parameters are defined in unit of pixel clock period, unless stated otherwise. MOTOROLA LCD Controller 19-13...
Page 452: Active Matrix Panel Interface Signals
1. LSCLK latches data into the panel on its negative edge (when positive polarity is selected). In active mode, LSCLK runs continuously. 2. HSYNC causes the panel to start a new line. 3. VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse. 19-14 MC9328MX1 Reference Manual MOTOROLA...
Page 453: Table 19-7 Tft Color Channel Assignments
The actual TFT color channel assignments are shown in Table 19-7. In 4 bpp and 8 bpp, bits LD11, LD6, LD5 and LD0 are fixed at 0. Table 19-7. TFT Color Channel Assignments – – – – 4 bpp – – – – 8 bpp – – – – 12 bpp 16 bpp MOTOROLA LCD Controller 19-15...
Page 454: Active Panel Interface Timing
H_WAIT_1 defines the delay from end of OE to the beginning of the HSYNC pulse. • XMAX defines the (total) number of pixels per line. NOTE: All parameters are defined in pixel periods, not LSCLK periods. 19-16 MC9328MX1 Reference Manual MOTOROLA...
Page 455: Figure 19-15 Horizontal Sync Pulse Timing In Tft Mode
(time = one line period) after VSYNC. The HSYNC pulse is output during the V_WAIT_2 delay. End of frame V_WIDTH Beginning of frame (lines) YMAX VSYNC HSYNC V_WAIT_1 V_WAIT_2 Figure 19-16. Vertical Sync Pulse Timing TFT Mode MOTOROLA LCD Controller 19-17...
Page 456: Table 19-8 Lcdc Register Memory Map
Figure 19-17 on page 19-19 provides a quick overview of the fields of all the registers. There are intentional gaps between the addresses for the read-write register section and the status register, and between the status register and the mapping RAM. 19-18 MC9328MX1 Reference Manual MOTOROLA...
Page 457: Figure 19-17 Register Memory Mapping Summary
DMACR 0x00205030 DMA Trigger Mark - TM RMCR 0x00205034 LCDC SELF _REF LCDICR 0x00205038 LCDISR 0x00205040 _ERR _RES 0x00205800 First RAM Location(R [3:0], G [3:0], B [3:0]) 0x00205BFC Last RAM Location(R [3:0], G [3:0], B [3:0]) MOTOROLA LCD Controller 19-19...
Page 458: Screen Start Address Register
Reserved—These bits are reserved and should read 0. Bits 1–0 19.4.2 Size Register The Size Register defines the height and width of the LCD screen. Addr SIZE Size Register 0x00205004 XMAX TYPE RESET 0x0000 YMAX TYPE RESET 0x0000 19-20 MC9328MX1 Reference Manual MOTOROLA...
Page 459: Virtual Page Width Register
Virtual Page Width—Defines the virtual page width of the LCD panel. The VPW bits represent the Bits 9–0 number of 32-bit words required to hold the data for one virtual line. VPW is used in calculating the starting address representing the beginning of each displayed line. MOTOROLA LCD Controller 19-21...
Page 460: Panel Configuration Register
011 = 8 bpp 100 = 12 bpp/16 bpp (16 bits of memory used) 11x = reserved 1x1 = reserved PIXPOL Pixel Polarity—Sets the polarity of the pixels. 0 = Active high Bit 24 1 = Active low 19-22 MC9328MX1 Reference Manual MOTOROLA...
Page 461 When PCD = O, pixel clock frequency is equal number of pixels in an output vector. to LCDC_CLK frequency. For passive matrix color panels (COLOR=1, TFT=0, PBSIZ=11) PCD must be greater than or equal to 2. MOTOROLA LCD Controller 19-23...
Page 462: Horizontal Configuration Register
Wait Between HSYNC and Start of Next Line—Specifies the number of pixel clk periods Bits 7–0 between the end of HSYNC and the beginning of the first data of next line. Total delay time equals (H_WAIT_2 + 3). 19-24 MC9328MX1 Reference Manual MOTOROLA...
Page 463: Vertical Configuration Register
OE pulse of the first line in active (TFT=1) mode. The actual delay is V_WAIT_2 ) lines. Set this field to zero for passive non-color mode. The minimum value of this field is 0x01. MOTOROLA LCD Controller 19-25...
Page 464: Panning Offset Register
Effective # of Bits to the left before processing. POS is Bits Per Pixel Panned on Image read by the LCDC once at the beginning of each frame. 19-26 MC9328MX1 Reference Manual MOTOROLA...
Page 465: Lcd Cursor Position Register
Cursor X Position—Represents the cursor’s horizontal starting position X in pixel count (from 0 to Bits 25–16 XMAX). Reserved Reserved—These bits are reserved and should read 0. Bits 15–9 Cursor Y Position—Represents the cursor’s vertical starting position Y in pixel count (from 0 to Bits 8–0 YMAX). MOTOROLA LCD Controller 19-27...
Page 466: Lcd Cursor Width Height And Blink Register
When the counter value equals BD, the cursor toggles on/off. 19.4.10 LCD Color Cursor Mapping Register The LCD Color Cursor Mapping Register defines the color of the cursor in passive or TFT color modes. 19-28 MC9328MX1 Reference Manual MOTOROLA...
Page 467: Table 19-18 Lcd Color Cursor Mapping Register Description
Cursor Blue Field—Defines the blue component For 8 bpp/12 bpp Bits 4–0 of the cursor color in color mode. 0000x = No blue 1111x = Full blue For 16 bpp 00000 = No blue 11111 = Full blue MOTOROLA LCD Controller 19-29...
Page 468: Sharp Configuration 1 Register
0000 = 1 LSCLK period Bits 11–8 transition delay of REV relative to the 0001 = 2 LSCLK periods last LD of the line. Delay is measured in LCDC_CLK (PerCLK2) periods. 1111 = 16 LSCLK periods 19-30 MC9328MX1 Reference Manual MOTOROLA...
Page 469: Figure 19-18 Horizontal Timing In Mc9328Mx1
CLS_HI_WIDTH is equal to PWM_SCR0 • 256 + PWM_WIDTH in units of LSCLK. SPL/SPR pulse width is fixed and aligned to the first data of the line. REV toggles every LP period. Figure 19-18. Horizontal Timing in MC9328MX1 MOTOROLA LCD Controller 19-31...
Page 470: Pwm Contrast Control Register
Contrast Control Enable—Enables/Disables the contrast control 0 = Contrast control is off Bit 8 function. 1 = Contrast control is on Pulse-Width—Controls the pulse-width of the built-in pulse-width modulator, which controls the Bits 7–0 contrast of the LCD screen. 19-32 MC9328MX1 Reference Manual MOTOROLA...
Page 471: Table 19-21 Refresh Mode Control Register Description
LCDC to avoid a malfunction. 3. The SSA must always match the address range of the RAM selected. If the user wants to switch between various types of RAM, the LCDC must be disabled before switching. MOTOROLA LCD Controller 19-33...
Page 472: Table 19-22 Dma Control Register Description
= 8 low mark = 4 For bus that is heavy loaded that requires SDRAM access, a dynamic burst length is recommended fixed burst length = 0 high mark = 4 low mark = 8 19-34 MC9328MX1 Reference Manual MOTOROLA...
Page 473: Interrupt Configuration Register
0 = Interrupt flag is set when the End of Bit 0 condition is set at the beginning or the end of frame Frame (EOF) is reached condition. 1 = Interrupt flag is set when the Beginning of Frame (BOF) is reached MOTOROLA LCD Controller 19-35...
Page 474: Interrupt Status Register
0 = Interrupt has not occurred Bit 0 beginning of frame has been reached. It is cleared 1 = Interrupt has occurred by reading the status register, at power on reset, or when the LCDC is disabled. 19-36 MC9328MX1 Reference Manual MOTOROLA...
Page 475: Mapping Ram Registers
16 colors can be selected out of a palette of 4096. The first 16 mapping RAM entries must be written to define the codes for the 16 available combinations. MOTOROLA LCD Controller...
Page 476: Four Bits/Pixel Active Matrix Color Mode
16 colors can be selected out of a palette of 4096. The first 16 mapping RAM entries must be written to define the codes for the 16 available combinations. 19-38 MC9328MX1 Reference Manual MOTOROLA...
Page 477: Twelve Bits/Pixel And Sixteen Bits/Pixel Active Matrix Color Mode
Blue Level (color display)—Represents the blue component level in the color. Bits 3–0 19.4.17.7 Twelve Bits/Pixel and Sixteen Bits/Pixel Active Matrix Color Mode In this mode the mapping RAM is not used, because the LCDC uses the display data in memory to drive the panel directly. MOTOROLA LCD Controller 19-39...
Page 478 LCD Controller 19-40 MC9328MX1 Reference Manual MOTOROLA...
Page 479: Introduction
Maskable hardware interrupt for card detection (insertion/removal), SD I/O interrupt, internal status, and FIFO status × • Contains an integrated 32 16-bit FIFO • Supports plug-and-play (PnP) • Supports many SD functions including multiple I/O and combined I/O and memory MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-1...
Page 480: Figure 20-1 Mmc/Sd Module Block Diagram
Supports up to seven I/O functions plus one memory on a single SD I/O card • Card can interrupt MMC/SD module • MMC/SD module is IP bus compatible with Motorola’s microcontrollers • Supports single or multiple block access, or stream access to the card for read, write, or erase operations •...
Page 481: Mmc/Sd Module And Card Information
Table 20-2. MMC/SD Card Registers Size MMC or SD Identifier Register Name Description (Bits) Both Card Identification Number Each card has a unique CID. Both Relative Card Address Assigned by the MMC/SD module during initialization. MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-3...
Page 482: Communication
See Section 20.7.8.5, “Response Formats,” for more information. Data—Data is transferred via the SD_DAT line(s) from the card to the MMC/SD module or from • the MMC/SD module to the card. Not all operations include data transfer. 20-4 MC9328MX1 Reference Manual MOTOROLA...
Page 483: Pin Configuration For The Mmc/Sd Module
Figure 20-1 on page 20-2 shows a block diagram of the MMC/SD module. The following sections provide brief functional descriptions of the major system blocks, including the DMA interface, memory controller (register handler), logic/command controller, and system clock controller. MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-5...
Page 484: Dma Interface
DATA_OUT Figure 20-3. DMAC Interface Block Diagram The DMAC interface block also handles burst requests to the external DMA controller, the internal register write-error detection, the SD I/O's ReadWait handling, and all IP-related output responses. 20-6 MC9328MX1 Reference Manual MOTOROLA...
Page 485: Dma Burst Request
// Clear DMA ISR for MMC *(P_U32)DMA_CCR1 = dir; // Ch1: FIFO as the target, Linear Mem source, // Mem inc, 16-bit target, 32-bit source, // Request Enable, DMA Disable // End of DMA usage MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-7...
Page 486: Write-Error Detection
The memory controller provides SD I/O-IRQ and ReadWait service handling, card detection, command response handling, and all MMC/SD module interrupt handling. It is the sub-module where the user must place the register table. Figure 20-5 shows the memory controller block diagram. 20-8 MC9328MX1 Reference Manual MOTOROLA...
Page 487: Sd I/O—Irq And Readwait Service Handling
SD_DAT [3] line, only single-card systems benefit from card detection. After the card is detected, the user must mask the card detection interrupt to avoid misleading interrupt generation during card access as the SD_DAT lines change. MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-9...
Page 488: Mmc/Sd Module Interrupt Handling
The command controller handles all interrupts related to the command line (SD_CMD) including command data sequence generation, command response extraction, CRC generation and checking, and response time-out. A state machine, logic controller, and CRC accelerator control these functions. 20-10 MC9328MX1 Reference Manual MOTOROLA...
Page 489: Figure 20-7 Block Diagram For Logic And Command Interpreters
Generator polynomial: G(x) = x M(x) = (first bit) • x + (second bit) • x + … + (last bit) • x CRC [15:0] = Remainder [(M(x) • x ) / G(x)] Eqn. 20-2 MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-11...
Page 490: System Clock Controller
The clock is turned off by setting the STOP_CLK bit in the MMC/SD Clock Control Register (STR_STP_CLK) and is turned on by setting the START_CLK bit. To change the clock rate, the application writes new prescaler and divider values in the CLK_RATE register. 20-12 MC9328MX1 Reference Manual MOTOROLA...
Page 491: Card Clock Control
MMC/SD Status Register STATUS 0x00214004 MMC/SD Clock Rate Register CLK_RATE 0x00214008 MMC/SD Command and Data Control Register CMD_DAT_CONT 0x0021400C MMC/SD Response Time-Out Register RES_TO 0x00214010 MMC/SD Read Time-Out Register READ_TO 0x00214014 MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-13...
Page 492: Mmc/Sd Clock Control Register
The programmer must first write the value 0x0008 then , and then write eight times. 0x000D 0x0005 Addr STR_STP_CLK MMC/SD Clock Control Register 0x00214000 TYPE RESET 0x0000 MMCSD MMCSD_ START STOP ENDIAN _RESET ENABLE _CLK _CLK TYPE RESET 0x0000 20-14 MC9328MX1 Reference Manual MOTOROLA...
Page 493: Table 20-5 Mmc/Sd Clock Control Register Description
Otherwise, the clock halts immediately. Setting a value of on Bits 1:0 is prohibited. Note: A transmission period is defined as the time from a card data-access-related command is submitted to the end of the data access operation. MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-15...
Page 494: Mmc/Sd Status Register
1 = Write operation complete MMC/SD module to wait until the card writes the buffered data to the inner flash memory. The MMC/SD module automatically detects the status. WRITE_OP_DONE determines the end of the write operation. 20-16 MC9328MX1 Reference Manual MOTOROLA...
Page 495 1 = CRC write error occurred write. See the WR_CRC_ERROR_CODE field for more information. Note: CRC_WRITE_ERR is cleared only by an internal status change or by removing the source of the error. MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-17...
Page 496 1 = Time-out read data error time specified in the READ_TO register. occurred TIME_OUT_READ is cleared only by an internal status change or by removing the source of the error. 20-18 MC9328MX1 Reference Manual MOTOROLA...
Page 497: Mmc/Sd Clock Rate Register
011 = CLK_DIV is CLK_20M ÷ 8 100 = CLK_DIV is CLK_20M ÷ 16 101 = CLK_DIV is CLK_20M ÷ 32 110 = CLK_DIV is CLK_20M ÷ 64 111 = CLK_DIV is CLK_20M ÷ 64 MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-19...
Page 498: Mmc/Sd Command And Data Control Register
Initialize—Specifies whether the optional 80 clock 0 = Disable 80 clocks Bit 7 cycle prefix (to initialize the card) will occur before 1 = Enable 80 clocks every command. INIT enables/disables the 80 clock initialization time. 20-20 MC9328MX1 Reference Manual MOTOROLA...
Page 499: Mmc/Sd Response Time-Out Register
20.6.5 MMC/SD Response Time-Out Register The MMC/SD Response Time-Out Register defines the time-out error for a received response. Addr RES_TO MMC/SD Response Time-Out Register 0x00214010 TYPE RESET 0x0000 RESPONSE TIME OUT TYPE RESET 0x0040 MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-21...
Page 500: Mmc/Sd Read Time-Out Register
Received Data Time-Out—Specifies the number of clocks between the command and Bits 15–0 when the MMC/SD module turns on the time-out error for the received data. The unit is CLK_20M ÷ 256. A value of 0x2DB4 is recommended. 20-22 MC9328MX1 Reference Manual MOTOROLA...
Page 501: Mmc/Sd Block Length Register
0x000 = 0 byte Bits 9–0 normally set to 0x200 for MMC/SD module data transactions. The 0x001 = 1 byte value is specified in the card’s CSD. 0x3FF = 1023 bytes MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-23...
Page 502: Mmc/Sd Number Of Blocks Register
Reserved—These bits are reserved and should read 0. Bits 31–16 Block Length—Specifies the number of blocks in a data transfer. One 0x0000 = 0 block Bits 15–0 block is a possibility. 0x0001 = 1 block 0xFFFF = 65535 blocks 20-24 MC9328MX1 Reference Manual MOTOROLA...
Page 503: Mmc/Sd Revision Number Register
Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 REVISION NUMBER Module Revision Number—Specifies the revision number of the Fixed at 0x0390 Bits 15–0 MMC/SD module. MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-25...
Page 504: Mmc/Sd Interrupt Mask Register
1 = SD I/O’s Interrupt detection based on SD_DAT [3:0] = 1101 SDIO MMC/SD I/O—Masks the interrupt from the SD I/O 0 = Not masked Bit 4 card to the MMC/SD module I/O interrupt mask. 1 = Masked 20-26 MC9328MX1 Reference Manual MOTOROLA...
Page 505: Table 20-15 Interrupt Mechanisms
BUF_READY (3) Clear interrupt by writing to INT_MASK bit Clear status by writing to BUFFER_ACCESS APPL_BUFF_FF (7) BUF_READY (3) Clear interrupt by writing to INT_MASK bit Clear status by reading BUFFER_ACCESS MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-27...
Page 506: Commands And Arguments
The command to send is set in the MMC/SD Command Number Register (CMD), and the argument is defined in two registers, the MMC/SD Higher Argument Register (ARGH) and the MMC/SD Lower Argument Register (ARGL). The full list of commands is shown in Table 20-25 on page 20-56. 20-28 MC9328MX1 Reference Manual MOTOROLA...
Page 507: Mmc/Sd Command Number Register
0x00 = CMD0 Bits 5–0 executed. 0x01 = CMD1 0x3F = CMD63 20.6.11.2 MMC/SD Higher Argument Register Addr ARGH MMC/SD Higher Argument Register 0x0021402C TYPE RESET 0x0000 ARGUMENT HIGH TYPE RESET 0x0000 MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-29...
Page 508: Mmc/Sd Lower Argument Register
Table 20-18. MMC/SD Lower Argument Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 ARGUMENT LOW Lower Argument—Specifies the lower word of the argument for the current command. Bits 15–0 20-30 MC9328MX1 Reference Manual MOTOROLA...
Page 509: Mmc/Sd Response Fifo Register
Reserved—These bits are reserved and should read 0. Bits 31–16 RESPONSE CONTENT Response Content—Contains the responses to every command that is sent by the Bits 15–0 MMC/SD module. This size of this FIFO register is 8x16-bit. MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-31...
Page 510: Mmc/Sd Buffer Access Register
The MMC and the SD are similar products and with the exception of the 4x bandwidth and the built-in encryption, they are programmed similarly. The following sections illustrate how to initialize, access, and protect the cards. 20-32 MC9328MX1 Reference Manual MOTOROLA...
Page 511: Basic Operation
The Code Example 20-3 demonstrates how to detect a card via the MMC/SD module. Code Example 20-3. Card_Detect card_detect() while(irq_status); // Wait interrupt generated (Card Presence) while(!STATUS[15]) Read_reg(STATUS); // Wait until card is detected Write_reg(INT_MASK, 0x40); MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-33...
Page 512: Reset
This query is used when the MMC/SD module is able to select a common voltage range or when the user requires notification that cards are not usable. 20-34 MC9328MX1 Reference Manual MOTOROLA...
Page 513: Card Registry
. The SD_CMD line output drivers are open-drain and allow parallel card operation during this process. The registration process is accomplished as follows: 1. The bus is activated. 2. The MMC/SD module broadcasts (CMD1) to receive operation SEND_OP_COND conditions. MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-35...
Page 514 CID and addresses the card. The assigned card changes to standby state. The MMC/SD module can re-issue this command to change the RCA. The RCA of the card is the last assigned value. 8. The MMC/SD module repeats steps 5 through 7 with all active cards. 20-36 MC9328MX1 Reference Manual MOTOROLA...
Page 515: Card Access
When a part of the CSD or CID register is stored in ROM, this unchangeable part must match the corresponding part of the receive buffer or the card reports an error and does not change any register contents. MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-37...
Page 516 Enable DMA operation; while(!Access Operation Done in STATUS true); while(!card bus is stop); if(nob > 1) send_cmd_wait_resp(STOP_TRANS, 0x00, 0x00, 0x41, 0x40); Code Example 20-8 on page 20-39 provides the program code for the block write with polling. 20-38 MC9328MX1 Reference Manual MOTOROLA...
Page 517: Block Read
Card Status Register, abort transmission, and wait in the data state for a stop command. Code Example 20-9 provides the program code for the block read with DMA. MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD)
Page 518 Enable DMA operation; while(!Data Transfer Done in STATUS true); while(!card bus is stop); if(nob > 1) send_cmd_wait_resp(STOP_TRANS, 0x00, 0x00, 0x41, 0x40); Code Example 20-10 on page 20-41 provides the program code for the block read with polling. 20-40 MC9328MX1 Reference Manual MOTOROLA...
Page 519 STATUS);// polling instead of irq or dma req for(j=0;j<8;j++) SDRAM_ADDR[i*8+j] = BUFFER_ACCESS; send_cmd_wait_resp(IO_RW_DIRECT, arg_h, arg_l, 0x5, 0x40); while(!Data Transfer Done in STATUS true); while(!card bus is stop); if(nob > 1) send_cmd_wait_resp(STOP_TRANS, 0x00, 0x00, 0x41, 0x40); MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-41...
Page 520: Stream Access—Stream Write And Stream Read (Mmc Only)
WP_VIOLATION bit in the Card Status Register. Code Example 20-11 on page 20-43 provides the program code for the stream write. 20-42 MC9328MX1 Reference Manual MOTOROLA...
Page 521: Stream Read
TRAN_SPEED = Maximum Data Transfer Rate • READ_BL_LEN = Maximum Read Data Block Length • NSAC = Data Read Access Time 2 in CLK Cycles • TAAC = Data Read Access Time 1 MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-43...
Page 522: Erase—Group Erase And Sector Erase (Mmc Only)
TAG_SECTOR_END TAG_ERASE_GROUP_END erase groups within the range are selected. The user can deselect a sector or erase group using the (CMD34) or (CMD37) commands. UNTAG_SECTOR UNTAG_ERASE_GROUP To erase by sectors, perform the following command sequence: 20-44 MC9328MX1 Reference Manual MOTOROLA...
Page 523: Wide Bus Selection Or Deselection
CSD, portions of the data can be protected, and the write-protection can be changed by the application. The write-protection is in units of WP_GRP_SIZE sectors as specified in the CSD. The commands control the protection of the addressed group. SET_WRITE_PROT CLR_WRITE_PROT MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-45...
Page 524: Mechanical Write Protect Switch
ERASE—Setting forces an erase operation. All other bits must be zero, and only the command byte • is sent. LOCK_UNLOCK—Setting locks the card. LOCK_UNLOCK can be set simultaneously with • SET_PWD, however not with CLR_PWD. CLR_PWD—Setting clears the password data. • SET_PWD—Setting saves the password data to memory. • 20-46 MC9328MX1 Reference Manual MOTOROLA...
Page 525: Setting The Password
2. Define the block length ( , CMD16) to send, given by the 8-bit card SET_BLOCKLEN lock/unlock mode (Byte 0 in Table 20-21), the 8-bit PWD_LEN, and the number of bytes of the current password. MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-47...
Page 526: Unlocking The Card
(Byte 0 in Table 20-21) is sent. 3. Send (CMD42) with the appropriate data byte on the data line including the LOCK/UNLOCK 16-bit CRC. The data block indicates the mode (ERASE = 1). All other bits must be zero. 20-48 MC9328MX1 Reference Manual MOTOROLA...
Page 527: Card Status Register
The selected sectors or groups for erase _PARAM 1 = Error are invalid. E R X 0 = No error An attempt is made to program a write _VIOLATION 1 = Protected Block protected block. MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-49...
Page 528 _DISABLED 1 = Internal ECC the internal ECC. disabled ERASE 0 = Erase completed An out-of-sequence erase command is _RESET 1 = Erase sequence not received, so the erase sequence is completed cleared before executing. 20-50 MC9328MX1 Reference Manual MOTOROLA...
Page 529: Sd Status Register
A—According to the card current state. • B—Always related to the previous command. Reception of a valid command clears it (with a delay • of one command). C—Clear by read • MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-51...
Page 530: Sd I/O
MMC/SD module provides pull-up resistors on all data lines (SD_DAT [3:0]). The MMC/SD module samples the level of Pin 8 (SD_DAT [1]/IRQ) into the interrupt detector only during the interrupt period. At all other times, the MMC/SD module ignores this value. 20-52 MC9328MX1 Reference Manual MOTOROLA...
Page 531: Sd I/O Suspend And Resume
ReadWait protocol, the MMC/SD module must test capability bits in the card internal registers. The timing for ReadWait is based on the interrupt period. Code Example 20-13 on page 20-54 provides the programming code for the SD I/O RW operation. MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-53...
Page 532: Commands And Responses
This section describes application-specific and general commands in addition to the command types and formats. Table 20-25 on page 20-56 is a list of all the MMC/SD module commands. Section 20.7.8.5, “Response Formats,” identifies and describes all command response formats. 20-54 MC9328MX1 Reference Manual MOTOROLA...
Page 533: Application-Specific And General Commands
SD_DAT line(s). 20.7.8.3 Command Formats All commands are sent over the SD_CMD line, are a fixed length of 48 bits, and are in the format shown in Table 20-24. MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-55...
Page 534: Commands For The Mmc/Sd Module
[15:0] stuff bits DESELECT transfer states or between _CARD programming and disconnect states. The card is selected by its own relative address and is deselected by any other address. Address 0 deselects all cards. CMD8 Reserved 20-56 MC9328MX1 Reference Manual MOTOROLA...
Page 535 WRITE_BLOCK Writes a block of the size selected by address SET_BLOCKLEN command. CMD25 ADTC [31:0] data WRITE_ Writes blocks of data continuously address MULTIPLE_ until a STOP_TRANSMISSION BLOCK command is issued. MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-57...
Page 536 CMD37 [31:0] data UNTAG_ERASE Removes one previously selected address _GROUP erase group from the erase selection. CMD38 [31:0] stuff bits ERASE Erases all selected sectors. 20-58 MC9328MX1 Reference Manual MOTOROLA...
Page 537 00 = 1-bit and 10 = 4-bit bus (The allowed data bus widths are given in the SCR Register.) ACMD13 ADTC [31:0] stuff bits SD_STATUS Sends the SD memory card status. MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-59...
Page 538: Response Formats
When data transfer to the card is involved, a busy signal can appear on the data line after the transmission of each block of data. The MMC/SD module must check for busy after data block transmission. 20-60 MC9328MX1 Reference Manual MOTOROLA...
Page 539: R1B—Normal Response With Busy
20.7.8.5.5 R4—Fast I/O for MMC Only • Response length is 48 bits • Argument field contains the RCA of the addressed card, the register address to be read-out or written-to, and the registers’ contents MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-61...
Page 540: R4B—Sd I/O Only
Card status bits change when (CMD3) is sent to an I/O only card. In this case, the SET_RELATIVE_ADDR 16 bits of response are the SD I/O-only values: • Bit [15]—COM_CRC_ERROR • Bit [14]—ILLEGAL_COMMAND • Bit [13]—ERROR • Bit [12:0]—Reserved 20-62 MC9328MX1 Reference Manual MOTOROLA...
Page 541: Table 20-32 R6 Response
Table 20-32. R6 Response Argument Bits 39-8 Bit 47 Bit 46 Bits 45-40 Bits 7-1 Bit 0 Bits 39-24 Bits 23-8 Start Bit Direction Bit CMD3 Card Status CRC7 End Bit Description 000011 Value MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-63...
Page 542 Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20-64 MC9328MX1 Reference Manual MOTOROLA...
Page 543: Block Diagram And Description
Two integrated general purpose input ports • 16-bit host bus access (byte access not supported) 21.3 Block Diagram and Description Figure 21-1 on page 21-2 shows a high-level block diagram of the MSHC module. MOTOROLA Memory Stick Host Controller (MSHC) Module 21-1...
Page 544: Memory Stick Interface
The MC9328MX1 provides support for the standard Memory Stick interface. Devices that conform to both the Memory Stick form factor and protocol are supported. Figure 21-2 on page 21-3 shows the interface signals required by the Memory Stick hardware. 21-2 MC9328MX1 Reference Manual MOTOROLA...
Page 545: Pin Configuration For The Mshc Module
The user must ensure that the data direction bits in the GPIO are set to the correct direction for proper operation. See Section 32.5.1, “Data Direction Registers,” on page 32-9 for details. MOTOROLA Memory Stick Host Controller (MSHC) Module 21-3...
Page 546: Memory Stick Host Controller Operation
When TBE = 0, the transmit buffer contains data that is pending transmission and when TBE = 1 the buffer is empty. When TBF = 1, the transmit buffer is full and data writes to the buffer are ignored. When TBF = 0, there is room for data in the transmit buffer. 21-4 MC9328MX1 Reference Manual MOTOROLA...
Page 547: Bus State Control Operation
Write TPC Read MSRDATA for Read TPC Read MSRDATA for Read TPC PIN (MSICS) MSICS [INTEN] = 1 MSICS [INTEN] = 0 Read MSPPCD Read MSICS MSICS [PINEN] = 1 MSPPCD [PIENx] MOTOROLA Memory Stick Host Controller (MSHC) Module 21-5...
Page 548: Sdio Interrupt Operation
Memory Stick Interrupt Control/Status Register and SDIO is asserted high (interrupt) by the Memory Stick. When SDIO = HIGH (INT) is detected during BS0 the INT bit of the Memory Stick Interrupt Control/Status Register (MSCR) is read and the interrupt status is checked. 21-6 MC9328MX1 Reference Manual MOTOROLA...
Page 549: Reset Operation
3. Internal operation — Internal Interrupt Request signal (MSIRQ) —> High level (Negated) — Internal DMA Request signal —> High level (Negated) — The Transmit/Receive FIFOs are cleared 4. The executing protocol is terminated MOTOROLA Memory Stick Host Controller (MSHC) Module 21-7...
Page 550: Power Save Mode Operation
Table 21-3. Interrupt Detect Capability on Power Save Mode MC9328MX1 MSHC Module MS_PI [1:0] MS_SDIO Interrupt Interrupt Power Save Mode Doze 0 (No PWS) Detectable Detectable Doze 1 (PWS) Detectable Not detectable Sleep Not detectable Not detectable 21-8 MC9328MX1 Reference Manual MOTOROLA...
Page 551: Register Access During Power Save Mode
Be sure that READ_SIZE is set to 4 half-words or less when executing READ_REG using the ACD. Figure 21-5 on page 21-10 indicates the ARM920T core processing and host interface operations when the ACD is used. This figure illustrates BLOCK_READ in SET_CMD execution. MOTOROLA Memory Stick Host Controller (MSHC) Module 21-9...
Page 552: Figure 21-5 Auto Command Function Operation
ACD (in Figure 21-5 on page 21-10, immediately before executing BLOCK_READ). The ACD bit of Memory Stick Control register 2 is automatically set to 0 after ACD ends (in Figure 21-5 on page 21-10, after GET_INT ends). 21-10 MC9328MX1 Reference Manual MOTOROLA...
Page 553: Serial Clock Divider Operation
DMA transfer—that is, it cannot use 2 DMA channels to handle Rx and Tx separately. This implies that the every time the MSHC module is switched from the transmit to the receive operation or the vice versa, the DMA registers need to be reconfigured. MOTOROLA Memory Stick Host Controller (MSHC) Module 21-11...
Page 554: Table 21-5 Mshc Module Dma Configuration Options
Memory Stick Interrupt Control/Status Register MSICS 0x0021A006 Memory Stick Parallel Port Control/Data Register MSPPCD 0x0021A008 Memory Stick Control 2 Register MSC2 0x0021A00A Memory Stick Auto Command Register MSACD 0x0021A00C Memory Stick FIFO Access Error Control/Status Register MSFAECS 0x0021A00E 21-12 MC9328MX1 Reference Manual MOTOROLA...
Page 555: Memory Stick Command Register
1110 = SET_CMD 1111 = Reserved Reserved Reserved—These bits are reserved and should read 0. Bits 11–10 DATA SIZE Data Size—Sets the data size, in bytes, based on the PID code. Bits 9–0 MOTOROLA Memory Stick Host Controller (MSHC) Module 21-13...
Page 556: Memory Stick Control/Status Register
NOCRC No CRC—Controls whether a CRC will be added to the 0 = CRC on Bit 11 end of the data array. Normally, this bit remains at 0 1 = CRC off during operation. 21-14 MC9328MX1 Reference Manual MOTOROLA...
Page 557: Memory Stick Transmit Fifo Data Register
MSCS register’s DRQ bit or MSICS register’s DRQ bit is 1, and must not be written before setting a write command to the Memory Stick Command Register. MOTOROLA Memory Stick Host Controller (MSHC) Module...
Page 558: Memory Stick Receive Fifo Data Register
When RBE is 1, invalid data is read and the FIFO read operation is ignored. The receive FIFO DATA register must be read only when the MSCS register’s DRQ bit or MSICS register’s DRQ bit is 1. Memory Stick Receive FIFO Data Addr MSRDATA Register 0x0021A004 RX DATA BUFFER TYPE RESET 0x0000 21-16 MC9328MX1 Reference Manual MOTOROLA...
Page 559: Memory Stick Interrupt Control/Status Register
PINEN = 1. To avoid this, the user must wait more than 32 HCLKs before setting PINEN to 1 after setting the PIENx bit of MSPPCD register to 1. MOTOROLA Memory Stick Host Controller (MSHC) Module 21-17...
Page 560 BS output is set to Low level when a CRC error occurs. Also, RDY becomes 1 and an interrupt signal is output. An internal interrupt request (MSIRQ) for this bit is negated by reading the MSICS register (when INTEN = 1). 21-18 MC9328MX1 Reference Manual MOTOROLA...
Page 561: Memory Stick Parallel Port Control/Data Register
0 = Parallel input port disabled Bit 13 MS_PI1. 1 = Parallel input port enabled PIEN0 PIEN0—Enables/Disables parallel port data input on 0 = Parallel input port disabled Bit 12 MS_PI0. 1 = Parallel input port enabled MOTOROLA Memory Stick Host Controller (MSHC) Module 21-19...
Page 562: Memory Stick Control 2 Register
1 = Little endian MSCEN MSHC Enable—Enables/Disables the MSHC module. 0 = MSHC module is disabled Bit 0 1 = MSHC module is enabled Note: MSCEN bit is NOT reset by setting RST bit of MSCS register. 21-20 MC9328MX1 Reference Manual MOTOROLA...
Page 563: Memory Stick Auto Command Register
The bit position assignments for this register are shown in the following register display. The settings for this register are described in Table 21-15. Memory Stick FIFO Access Error Addr MSFAECS Control/Status Register 0x0021A00E FAEEN TYPE RESET 0x0000 MOTOROLA Memory Stick Host Controller (MSHC) Module 21-21...
Page 564: Memory Stick Serial Clock Divider Register
This register is initialized on power up. NOTE: This register is not initialized by the RST bit of the Memory Stick Control/Status Register. Memory Stick Serial Clock Divider Addr MSCLKD Register 0x0021A010 TYPE RESET 0x0002 21-22 MC9328MX1 Reference Manual MOTOROLA...
Page 565: Memory Stick Dma Request Control Register
Read type TPC. This DMA request capability is needed to communicate with DMA Controller. Memory Stick DMA Request Control Addr MSDRQC Register 0x0021A012 DRQEN TYPE RESET 0x0000 MOTOROLA Memory Stick Host Controller (MSHC) Module 21-23...
Page 566: Programmer's Reference
BS0 state has no packet communication going on while three states (BS1, BS2, and BS3) have packet communication being executed. BS1 through BS3 are regarded as one packet and one communication transfer is always completed within one packet (in Four State Access Mode). 21-24 MC9328MX1 Reference Manual MOTOROLA...
Page 567: Figure 21-7 Memory Stick Bus Four State Access Protocol
Two State Access Mode in which states BS0 and BS1 are automatically repeated to avoid bus collision on SDIO. See Section 21.8.3, “Transfer Protocol Command (TPC).” MOTOROLA Memory Stick Host Controller (MSHC) Module 21-25...
Page 568: Protocol
INT (HIGH signal) is output on SDIO. During BS0 period, SDIO signal line is used as INT signal line which does not synchronize with SCLK. 21.8.2.2 Read Packet SDIO RDY/BSY Data Memory Stick Host Memory Stick SCLK Figure 21-9. Read Packet 21-26 MC9328MX1 Reference Manual MOTOROLA...
Page 569: Transfer Protocol Command (Tpc)
WRITE_REG Write register TPC for writing to the register whose address was set. Address and Data length are set by SET_R/W_REG_ADRS. Actual Data length: the value which was set + CRC (16-bit). MOTOROLA Memory Stick Host Controller (MSHC) Module 21-27...
Page 570: Protocol Error
Stick shifts to Two State Access Mode automatically when an error occurs in a packet. SDIO Host Memory Stick Host SCLK Figure 21-10. Two State Access Mode In Two State Access Mode, operation is performed with recognition that MS_BS = LOW is BS0 and MS_BS = HIGH is BS1. 21-28 MC9328MX1 Reference Manual MOTOROLA...
Page 571: Figure 21-11 Write Packet Time-Out
Time-out on Host Memory Stick–BS0 SDIO Memory Stick Host SCLK Figure 21-12. Read Packet Time-Out NOTE: When a time-out occurs in BS2 of a read packet, the bus state does not shift to BS3. MOTOROLA Memory Stick Host Controller (MSHC) Module 21-29...
Page 572: Figure 21-13 Signal Timing
Figure 21-13. Signal Timing • Timing of SCLK, SDIO and BS — Sender outputs SDIO signal at SCLK fall (output side), and latches it at SCLK rise (input side). • BS signal is output synchronizing with SCLK fall 21-30 MC9328MX1 Reference Manual MOTOROLA...
Page 573: Data Transfer Extension
Memory Stick to the MSHC module cannot be received from the rise of next SCLK because the MSHC module buffer is full, the next data transfer can be delayed by keeping SCLK high. SDIO SCLK Figure 21-15. SCLK Extension for Data Wait MOTOROLA Memory Stick Host Controller (MSHC) Module 21-31...
Page 574 Memory Stick Host Controller (MSHC) Module 21-32 MC9328MX1 Reference Manual MOTOROLA...
Page 575: Pwm Signals
For 16 kHz audio applications, CLKSEL = 01, divide by 4. For DC-level applications, CLKSEL = 11, divide by 16. See Table 22-7 on page 22-8 for a complete list of settings for the PWMC register. MOTOROLA Pulse-Width Modulator (PWM)
Page 576: Pin Configuration For Pwm
The prescaler clock (PCLK) runs 256 times faster than the sampling rate when the PERIOD field of the PWM period (PWMP) register is at its maximum value. Figure 22-2 illustrates how variable width pulses affect an audio waveform. Pulse-Width Modulation Stream Filtered Audio Figure 22-2. Audio Waveform Generation 22-2 MC9328MX1 Reference Manual MOTOROLA...
Page 577: Tone Mode
The PWM Control Register controls the operation of the pulse-width modulator, and it also contains the status of the PWM FIFO. The register bit assignments are shown in the following register display. The register settings are described in Table 22-3 on page 22-4. MOTOROLA Pulse-Width Modulator (PWM) 22-3...
Page 578: Table 22-3 Pwm Control Register Description
PWM interrupt. IRQEN Interrupt Request Enable—Enables/Disables the pulse-width 0 = PWM interrupt is disabled Bit 6 modulator interrupt. When IRQEN is low, the interrupt is 1 = PWM interrupt is enabled disabled. 22-4 MC9328MX1 Reference Manual MOTOROLA...
Page 579: Hctr And Bctr Bit Description
When the endian format of the wave data stored in external memory is not compatible to the system endian format, these two bits control the swapping of the data to the PWM FIFO. The data port size used by the external memory must be used in conjunction with these two bits. MOTOROLA Pulse-Width Modulator (PWM) 22-5...
Page 580: Pwm Sample Register
0xXXXX Table 22-5. PWM Sample Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 SAMPLE Sample—Contains a two-sample word. This word is written to the pulse-width modulator. Bits 15–0 22-6 MC9328MX1 Reference Manual MOTOROLA...
Page 581: Pwm Period Register
RESET 0x0000 PERIOD TYPE RESET 0xFFFE Table 22-6. PWM Period Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 PERIOD Period—Represents the pulse-width modulator’s period control value. Bits 15–0 MOTOROLA Pulse-Width Modulator (PWM) 22-7...
Page 582: Pwm Counter Register
0x0020800C TYPE RESET 0x0000 COUNT TYPE RESET 0x0000 Table 22-7. PWM Counter Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 COUNT Count—Represents the current count value. Bits 15–0 22-8 MC9328MX1 Reference Manual MOTOROLA...
Page 583 As shown in the RTC block diagram (Figure 23-1), the real-time clock module consists of the following blocks: • Prescaler • Time-of-day (TOD) clock counter • Alarm • Sampling timer • Minute stopwatch • Associated control and bus interface hardware MOTOROLA Real-Time Clock (RTC) 23-1...
Page 584: Prescaler And Counter
59 to 00, the minute counter increments and the MIN interrupt flag is set. The same is true for the minute counter with the HR signal, and the hour counter with the DAY signal. 23-2 MC9328MX1 Reference Manual MOTOROLA...
Page 585: Alarm
At each minute, the value in the stopwatch is decremented. When the stopwatch value reaches -1, the interrupt occurs. The value of the register does not change until it is reprogrammed. Note that the actual delay includes the seconds from setting the stopwatch to the next minute tick. MOTOROLA Real-Time Clock (RTC) 23-3...
Page 586: Rtc Days Counter Register
NOTE: This day counter only supports halfword and word write operations. That means that all 9 bits must be set simultaneously. Addr DAYR RTC Days Counter Register 0x00204020 TYPE RESET 0x0000 DAYS TYPE RESET 0x0??? 23-4 MC9328MX1 Reference Manual MOTOROLA...
Page 587: Rtc Hours And Minutes Counter Register
Bits 12–8 between 0 and 23. Reserved Reserved—These bits are reserved and should read 0. Bits 7–6 MINUTES Minute Setting—Indicates the current minute. MINUTES can be set to any Bits 5–0 value between 0 and 59. MOTOROLA Real-Time Clock (RTC) 23-5...
Page 588: Rtc Seconds Counter Register
Table 23-5. RTC Seconds Counter Register Description Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–6 SECONDS Seconds Setting—Indicates the current second. SECONDS can be set to any value Bits 5–0 between 0 and 59. 23-6 MC9328MX1 Reference Manual MOTOROLA...
Page 589: Rtc Day Alarm Register
Reserved—These bits are reserved and should read 0. Bits 31–9 DAYSAL Day Setting of the Alarm—Indicates the current day DAYSAL can be set to any value Bits 8–0 setting of the alarm. between 0 and 511. MOTOROLA Real-Time Clock (RTC) 23-7...
Page 590: Rtc Hours And Minutes Alarm Register
Reserved—These bits are reserved and should read 0. Bits 7–6 MINUTES Minute Setting of the Alarm—Indicates the current MINUTES can be set to any value Bits 5–0 minute setting of the alarm. between 0 and 59. 23-8 MC9328MX1 Reference Manual MOTOROLA...
Page 591: Rtc Seconds Alarm Register
Reserved—These bits are reserved and should read 0. Bits 31–6 SECONDS Seconds Setting of the Alarm—Indicates the current SECONDS can be set to any value Bits 6–0 seconds setting of the alarm. between 0 and 59. MOTOROLA Real-Time Clock (RTC) 23-9...
Page 592: Rtc Control Register
These bits are cleared by writing a value of 1, which also clears the interrupt. Interrupts may occur when the system clock is idle or in sleep mode. For more information about the frequency of the sampling timer interrupts (SAM7-SAM0), refer to Table 23-1. 23-10 MC9328MX1 Reference Manual MOTOROLA...
Page 593: Table 23-10 Rtc Interrupt Status Register Description
1 = A SAM3 interrupt occurred enabled, this bit is periodically set at a rate of 32, 31.25, or 37.5 Hz. The actual rate of the interrupt depends on the input clock value. See Table 23-1. MOTOROLA Real-Time Clock (RTC) 23-11...
Page 594 1 = A 1-minute interrupt occurred the minute counter in the time-of-day clock. Stopwatch Flag—Indicates that the stopwatch countdown 0 = The stopwatch did not time-out. Bit 0 timed out. 1 = The stopwatch timed out. 23-12 MC9328MX1 Reference Manual MOTOROLA...
Page 595: Rtc Interrupt Enable Register
Sampling Timer Interrupt Flag at SAM2 Interrupt 0 = SAM2 interrupt is disabled Bit 10 Enable—Enables/Disables the real-time sampling timer interrupt 2. 1 = SAM2 interrupt is enabled The frequency of this interrupt is shown in Table 23-1. MOTOROLA Real-Time Clock (RTC) 23-13...
Page 596 Note: The stopwatch counts down and remains at decimal -1 until enabled it is reprogrammed. If this bit is enabled with -1 (decimal) in the STPWCH register, an interrupt will be posted on the next minute tick. 23-14 MC9328MX1 Reference Manual MOTOROLA...
Page 597: Stopwatch Minutes Register
0.5 minutes. For better accuracy, enable the stopwatch by will not change until a polling the MIN bit of the RTCISR register or by polling the minute nonzero value (1–62) is interrupt service routine. written. MOTOROLA Real-Time Clock (RTC) 23-15...
Page 598 Real-Time Clock (RTC) 23-16 MC9328MX1 Reference Manual MOTOROLA...
Page 599: Features
Software configurable bus width, row and column sizes, and delays for differing system requirements • Built in auto-refresh timer and state machine • Hardware supported self-refresh entry and exit which keeps data valid during system reset and low-power modes • Auto-powerdown (clock suspend) timer MOTOROLA SDRAM Memory Controller 24-1...
Page 600: Figure 24-1 Sdram Controller Block Diagram
Powerdown Timer SDWE SDWE m_rst m_rst SDRAM Command SDCKE0 SDCKE0 sd_rst Controller SDCKE1 SDCKE1 SDCLK SDCLK p_lpmd[1:0] RESET_SF RESET_SF sd_lpack sf_wack prefetch x1clk p_data[31:0] Data Aligner DQ[31:0] D[31:0] bigendian Figure 24-1. SDRAM Controller Block Diagram 24-2 MC9328MX1 Reference Manual MOTOROLA...
Page 601: Functional Overview
SDRAM memories require a periodic refresh to retain data. The refresh request counter generates requests to the SDRAM Command Controller to perform these refresh cycles. Requests are scheduled according to a 32 kHz clock input with 1, 2, or 4 refresh cycles generated per clock. MOTOROLA SDRAM Memory Controller 24-3...
Page 602: Powerdown Timer
Clock enable to SDRAM 0 Output High SDCKE1 SDCLKE1 Clock enable to SDRAM 1 Output High CSD0 Chip-select to SDRAM array 0 Output High CSD1 Chip-select to SDRAM array 1 Output High MA [11:10] MA [11:10] Multiplexed Address Output 24-4 MC9328MX1 Reference Manual MOTOROLA...
Page 603: Sdclk—Sdram Clock
CSD0 and CSD1 are used to select SDRAM array 0 and SDRAM array 1, respectively. When a valid command is present on the other control signals, the chip-select signals are used to indicate which device the command is directed towards. MOTOROLA SDRAM Memory Controller 24-5...
Page 604: Dq [31:0]—Data Bus (Internal)
Row address strobe is also part of the SDRAM command field. It is generally used to indicate an operation affecting an entire bank or row. When RAS is asserted (low), a new SDRAM row address must be latched. Table 24-51 on page 24-69 provides details on SDRAM command encoding. 24-6 MC9328MX1 Reference Manual MOTOROLA...
Page 605: Cas—Column Address Strobe
Alternate function of CS3/CSD1 Set bit 1 (SDCS1_SEL) in the Function Multiplexing Control register of the System Control module. MA [11:10] Not multiplexed MA [9:0] Multiplexed with Internal signal from SDRAMC, asserted for SDRAM accesses A [10:1] MOTOROLA SDRAM Memory Controller 24-7...
Page 606: Table 24-5 Sdram Module Register Memory Map
(SP bit of the SDCTL = 1) region will result in a transfer error. Table 24-6. SDRAM Array Memory Map Address Access 0x0800 0000 – 0x0BFF FFFF SDRAM 0 Memory array 0x0C00 0000 – 0x0FFF FFFF SDRAM 1 Memory array 24-8 MC9328MX1 Reference Manual MOTOROLA...
Page 607: Sdram Control Registers
Operating mode details are provided in Section 24.8, “SDRAM Operation,” and Section 24.9, “SyncFlash Operation.” Reset initializes the operating mode to “Normal Read/Write”. MOTOROLA SDRAM Memory Controller 24-9...
Page 608 10 = 10 Column width is the number of multiplexed column 11 = 11 addresses and does not include bank and row addresses, or addresses used to generate the DQM signals. 24-10 MC9328MX1 Reference Manual MOTOROLA...
Page 609 32 kHz clock. At each rising edge, 1, 2, or 4 rows will be refreshed. Multiple refresh cycles are separated by the row cycle delay specified in the SRC control field. MOTOROLA SDRAM Memory Controller 24-11...
Page 610 Placing the MC9328MX1 SDRAM controller in Bank Interleaved mode is not the same as SDRAM Interleaved mode. For Bank Interleaved mode, the SDRAM memory must be programmed to sequential or linear mode in the SDRAM mode register. 24-12 MC9328MX1 Reference Manual MOTOROLA...
Page 611: Figure 24-2 Memory Bank Interleaving Options
32.768 kHz 32.768 kHz 38.4 kHz Clock Refresh disabled µ µ µ 2048 2097 2457 31.25 30.52 26.04 µ µ µ 4096 4194 4915 15.62 15.26 13.02 µ µ µ 8192 8388 9830 7.81 7.63 6.51 MOTOROLA SDRAM Memory Controller 24-13...
Page 612: Figure 24-3 Cas Latency Timing
SDRAM Memory Controller SDCLK COMMAND READ CAS Latency = 1 SDCLK READ COMMAND DATA CAS Latency = 2 SDCLK COMMAND READ DATA CAS Latency = 3 Figure 24-3. CAS Latency Timing 24-14 MC9328MX1 Reference Manual MOTOROLA...
Page 613: Figure 24-4 Precharge Delay Timing
Programming Model SDCLK COMMAND Figure 24-4. Precharge Delay Timing SDCLK ACTIVE READ/WRITE COMMAND SDCLK COMMAND ACTIVE READ/WRITE SDCLK ACTIVE READ/WRITE COMMAND Figure 24-5. Row-to-Column Delay Timing MOTOROLA SDRAM Memory Controller 24-15...
Page 614: Sdram Reset Register
SDRAM/SyncFlash controller. 01 = One HCLK cycle reset pulse 10 = One HCLK cycle reset pulse 11 = Two HCLK cycle reset pulse Reserved Reserved—These bits are reserved and should read 0. Bits 29–0 24-16 MC9328MX1 Reference Manual MOTOROLA...
Page 615: Miscellaneous Register
Code Example 24-1. Read-Device HWSF_read_device_ID r2, 0x80000001 //force ma0 to 1 r8, 0x00221014 r2,(r8) r8, 0x0c000000 //read SyncFlash device ID ldrh r2, (r8,0) r1, 0x00d3 r1, r2 ERROR_OUT r2, 0x00000000 //release ma0 r8, 0x00221014 r2,(r8) MOTOROLA SDRAM Memory Controller 24-17...
Page 616: Operating Modes
The reset state of the control register allows for basic read/write operations sufficient to fetch the reset vector and execute the initialization code. A complete initialization of the controller must be performed as part of the start-up code sequence. 24-18 MC9328MX1 Reference Manual MOTOROLA...
Page 617: Normal Read/Write Mode (Smode = 000)
Write command is issued. The SDRAM controller only supports single burst writes and does not issue a burst terminate after each write. Therefore, the user MOTOROLA SDRAM Memory Controller...
Page 618: Figure 24-7 Off-Page Single Read Timing Diagram (32-Bit Memory)
DATA Figure 24-7. Off-Page Single Read Timing Diagram (32-Bit Memory) SDCLK ADDR COLUMN COLUMN COLUMN CAS Latency RAS, READ TBST READ CAS, SDWE CSDx DATA DATA Figure 24-8. On-Page Single Read Timing Diagram (32-Bit Memory) 24-20 MC9328MX1 Reference Manual MOTOROLA...
Page 619: Figure 24-9 Off-Page Burst Read Timing Diagram (32-Bit Memory)
Da1 Da2 Da3 Da4 Figure 24-10. On-Page Burst Read Timing Diagram (32-Bit Memory) SDCLK COLUMN COLUMN ADDR RAS, WRIT WRIT CAS, SDWE CSDx DATA DATA DATA Figure 24-11. Off-Page Write Followed by On-Page Write Timing Diagram MOTOROLA SDRAM Memory Controller 24-21...
Page 620: Figure 24-12 Off-Page Burst Write Timing Diagram
CSDx DATA Figure 24-13. On-Page Burst Write Timing Diagram SDCLK BANK, COL1 BANK, COL2 ADDR RAS, CAS, WRIT READ TBST SDWE CAS Latency CSDx DATA Figure 24-14. Single Write Followed by On-Page Read Timing Diagram 24-22 MC9328MX1 Reference Manual MOTOROLA...
Page 621: Precharge Command Mode (Smode = 001)
The Precharge Command Mode (SMODE = 001) is used during SDRAM device initialization, and to manually deactivate any and all active banks. While in this mode, an access (either read or write) to the SDRAM address space will generate a precharge command cycle. SDRAM address bit A10 determines MOTOROLA SDRAM Memory Controller 24-23...
Page 622: Auto-Refresh Mode (Smode = 010)
The lower address lines are ignored. Either a read or write cycle may be used. If a write is used, the data will be ignored and the external data bus will not be driven. The cycle will be 2 clocks on the AHB and a single clock to the SDRAM device. 24-24 MC9328MX1 Reference Manual MOTOROLA...
Page 623: Set Mode Register Mode (Smode = 011)
) must be met before the mode register set command is issued. Section 24.8.4, “Mode Register Programming,” provides a detailed example of the mode register data value calculation and mapping to the ARM920T processor’s address. MOTOROLA SDRAM Memory Controller 24-25...
Page 624: Syncflash Load Command Mode
Although not shown in the diagram, the device configuration data would be returned across the data bus after the CAS latency had been met. 24-26 MC9328MX1 Reference Manual MOTOROLA...
Page 625: Syncflash Program Mode
Addr = * Bank = A Bank = * WRITE READ Addr = Col Addr = * Bank = A Bank = * * — Any address within memory region Figure 24-24. SyncFlash Program Mode State Diagram MOTOROLA SDRAM Memory Controller 24-27...
Page 626: General Operation
The general operation of the SDRAM controller is discussed in this section and includes address multiplexing, refresh and self-refresh modes. The SDRAM Controller is designed to support a broad range of JEDEC standard SDRAM configurations including devices of 64-, 128-, and 256-Mbit densities. Given 24-28 MC9328MX1 Reference Manual MOTOROLA...
Page 627: Address Multiplexing
This is demonstrated in the last two rows of Table 24-13 by the grayed-out boxes. Note that the AP signal is duplicated in two bit positions to permit this signal to always appear on memory pin A10. Table 24-14 lists the SDRAM interface connections for different configurations of JEDEC SDRAM. MOTOROLA SDRAM Memory Controller 24-29...
Page 628: Table 24-13 Address Multiplexing By Column Width
(16 Mbyte) (32 Mbyte) (64 Mbyte) (8 Mbyte) (16 Mbyte) (32 Mbyte) MC9328MX1 Pins SDRAM Memory Address Pins Rows Columns Data size Refresh rows 4096 4096 8192 2048 4096 8192 MC9328MX1 Pins SDRAM Memory Address Pins 24-30 MC9328MX1 Reference Manual MOTOROLA...
Page 629: Non-Multiplexed Address Bus
These configuration-dependent connections are handled through the design of the external hardware. Examples are provided in Section 24.8, “SDRAM Operation,” and Section 24.9, “SyncFlash Operation.” MOTOROLA SDRAM Memory Controller 24-31...
Page 630: Bank Addresses
SDRAM and other devices are required for the refresh operation. 32KHz SDCLK ADDR A10 = 1 >= t >= t RAS, PRE-ALL REF A REF A CAS, SDWE CSDx DATA DATA Figure 24-27. Hardware Refresh Timing Diagram 24-32 MC9328MX1 Reference Manual MOTOROLA...
Page 631: Self-Refresh
Because powerdown can only be entered if all banks are idle, a Precharge All command must be issued to the memories prior to stopping the clock. Figure 24-31 illustrates the powerdown sequence following assertion of system reset. MOTOROLA SDRAM Memory Controller 24-33...
Page 632: Figure 24-29 Self-Refresh Entry Due To Low-Power Mode Timing Diagram
Figure 24-29. Self-Refresh Entry Due to Low-Power Mode Timing Diagram Low-Power Mode Signal from CPU SDRAM Low-Power Mode Acknowledge Signal SDCLK SDCKEx ADDR >= t + 1 Clock RAS, CAS, REF A SDWE CSDx DATA Figure 24-30. Low-Power Mode Self-Refresh Exit Timing Diagram 24-34 MC9328MX1 Reference Manual MOTOROLA...
Page 633: Clock Suspend Low-Power Mode
This operation does not cause the clocks to stop, nor does manually precharging only a single bank within the memory. All banks within the memory must be inactive before the powerdown mode is invoked. MOTOROLA SDRAM Memory Controller 24-35...
Page 634: Clock Suspend
REF A CAS, SDWE CSDx DATA Figure 24-32. Powerdown Mode Entry Timing Diagram SDCLK SDCKEx ADDR COLUMN COLUMN COLUMN SDRAMx Minimum RAS, READ TBST READ CAS, SDWE CSDx DATA DATA Figure 24-33. Powerdown Exit Timing Diagram 24-36 MC9328MX1 Reference Manual MOTOROLA...
Page 635: Sdram Operation
Physical Characteristics: row and column address bus widths, data bus width, and interleave mode • Timing Parametrics: CAS latency, row precharge and cycle delays, and refresh rate • Functional Features: clock suspend timer and supervisor/user protection MOTOROLA SDRAM Memory Controller 24-37...
Page 636: Cas Latency
AUTO REFRESH cycles every 64 ms, then the refresh rate can be calculated as 64 ms / 8192 rows = 7.81 µs per row. Therefore the user programs the SREFR field with 11. Refer to Section 24.7.2, “Refresh,” on page 24-32 for more information. 24-38 MC9328MX1 Reference Manual MOTOROLA...
Page 637: Memory Configuration Examples
Bank Interleaved MA[11:10],A[10:1]: A[11:0] CS2/CSD0 SDWE DQM3 DQM2 DQMH DQM1 DQML DQM0 DQ[15:0] DQ[15:0] SDCLK SDCKE SDRAM 4M x 16 CONTROLLER SDRAM Figure 24-35. Single 64 Mbit (4M x 16) Connection Diagram (IAM = 1) MOTOROLA SDRAM Memory Controller 24-39...
Page 638: Figure 24-36 Single 64 Mbit (4M X 16 X 1) Connection Diagram (Iam = 0)
MA[11:10],A[10:1]: A[11:0] CS2/CSD0 SDWE DQM3 DQM2 DQMH DQM1 DQML DQM0 DQ[15:0] DQ[15:0] SDCLK SDCKE SDRAM 4M x 16 CONTROLLER SDRAM Figure 24-36. Single 64 Mbit (4M x 16 x 1) Connection Diagram (IAM = 0) 24-40 MC9328MX1 Reference Manual MOTOROLA...
Page 639: Figure 24-37 Single 128 Mbit (8M X 16) Connection Diagram (Iam = 1)
Bank Interleaved MA[11:10],A[10:1]: A[11:0] CS2/CSD0 SDWE DQM3 DQM2 DQMH DQM1 DQML DQM0 DQ[15:0] DQ[15:0] SDCLK SDCKE SDRAM 8M x 16 CONTROLLER SDRAM Figure 24-37. Single 128 Mbit (8M x 16) Connection Diagram (IAM = 1) MOTOROLA SDRAM Memory Controller 24-41...
Page 640: Figure 24-38 Single 128 Mbit (8M X 16) Connection Diagram (Iam = 0)
Non-bank Interleaved MA[11:10],A[10:1]: A[11:0] CS2/CSD0 SDWE DQM3 DQM2 DQMH DQM1 DQML DQM0 DQ[15:0] DQ[15:0] SDCLK SDCKE SDRAM 8M x 16 CONTROLLER SDRAM Figure 24-38. Single 128 Mbit (8M x 16) Connection Diagram (IAM = 0) 24-42 MC9328MX1 Reference Manual MOTOROLA...
Page 641: Figure 24-39 Single 256 Mbit (16M X 16) Connection Diagram (Iam = 1)
A[14] A[12] MA[11:10],A[10:1 A[11:0] CS2/CSD0 SDWE DQM3 DQM2 DQMH DQM1 DQML DQM0 DQ[15:0] DQ[15:0] SDCLK SDCKE SDRAM 16M x 16 CONTROLLER SDRAM Figure 24-39. Single 256 Mbit (16M x 16) Connection Diagram (IAM = 1) MOTOROLA SDRAM Memory Controller 24-43...
Page 642: Figure 24-40 Single 256 Mbit (16M X 16) Connection Diagram (Iam = 1)
A[12] A[12] MA[11:10],A[10:1 A[11:0] CS2/CSD0 SDWE DQM3 DQM2 DQMH DQM1 DQML DQM0 DQ[15:0] DQ[15:0] SDCLK SDCKE SDRAM 16M x 16 CONTROLLER SDRAM Figure 24-40. Single 256 Mbit (16M x 16) Connection Diagram (IAM = 1) 24-44 MC9328MX1 Reference Manual MOTOROLA...
Page 643: Figure 24-41 Dual 64 Mbit (4M X 16 X 2) Connection Diagram (Iam = 1)
DQM2 DQML DQM1 DQM0 D[31:16] DQ[15:0] D[15:0] MC9328MX1 4M x 16 SDRAM A[10:0] DQMH DQML DQ[15:0] 4M x 16 SDRAM Figure 24-41. Dual 64 Mbit (4M x 16 x 2) Connection Diagram (IAM = 1) MOTOROLA SDRAM Memory Controller 24-45...
Page 644: Figure 24-42 Dual 64 Mbit (4M X 16 X 2) Connection Diagram (Iam = 0)
DQM2 DQML DQM1 DQM0 D[31:16] DQ[15:0] D[15:0] 4M x 16 MC9328MX1 SDRAM A[10:0] DQMH DQML DQ[15:0] 4M x 16 SDRAM Figure 24-42. Dual 64 Mbit (4M x 16 x 2) Connection Diagram (IAM = 0) 24-46 MC9328MX1 Reference Manual MOTOROLA...
Page 645: Figure 24-43 Dual 128 Mbit (8M X 16 X 2) Connection Diagram (Iam = 1)
DQM2 DQML DQM1 DQM0 D[31:16] DQ[15:0] D[15:0] 8M x 16 MC9328MX1 SDRAM A[10:0] DQMH DQML DQ[15:0] 8M x 16 SDRAM Figure 24-43. Dual 128 Mbit (8M x 16 x 2) Connection Diagram (IAM = 1) MOTOROLA SDRAM Memory Controller 24-47...
Page 646: Figure 24-44 Dual 128 Mbit (8M X 16 X 2) Connection Diagram (Iam = 0)
DQM2 DQML DQM1 DQM0 D[31:16] DQ[15:0] D[15:0] 8M x 16 MC9328MX1 SDRAM A[10:0] DQMH DQML DQ[15:0] 8M x 16 SDRAM Figure 24-44. Dual 128 Mbit (8M x 16 x 2) Connection Diagram (IAM = 0) 24-48 MC9328MX1 Reference Manual MOTOROLA...
Page 647: Figure 24-45 Dual 256 Mbit (16M X 16 X 2) Connection Diagram (Iam = 1)
DQM2 DQML DQM1 DQM0 D[31:16] DQ[15:0] D[15:0] 16M x 16 SDRAM MC9328MX1 A[10:0] DQMH DQML DQ[15:0] 16M x 16 SDRAM Figure 24-45. Dual 256 Mbit (16M x 16 x 2) Connection Diagram (IAM = 1) MOTOROLA SDRAM Memory Controller 24-49...
Page 648: Figure 24-46 Dual 256 Mbit (16M X 16 X 2) Connection Diagram (Iam = 0)
DQM2 DQML DQM1 DQM0 D[31:16] DQ[15:0] D[15:0] 16M x 16 MC9328MX1 SDRAM A[10:0] DQMH DQML DQ[15:0] 16M x 16 SDRAM Figure 24-46. Dual 256 Mbit (16M x 16 x 2) Connection Diagram (IAM = 0) 24-50 MC9328MX1 Reference Manual MOTOROLA...
Page 649: Figure 24-47 Single 64 Mbit (2M X 32) Connection Diagram (Iam = 1)
Bank–interleaved MA11 MA10 CS2/CSD0 SDWE DQM3 DQM3 DQM2 DQM2 DQM1 DQM1 DQM0 DQM0 D[31:0] DQ[31:0] SDCLK SDCKE 2M x 32 MC9328MX1 SDRAM Figure 24-47. Single 64 Mbit (2M x 32) Connection Diagram (IAM = 1) MOTOROLA SDRAM Memory Controller 24-51...
Page 650: Figure 24-48 Single 64 Mbit (2M X 32) Connection Diagram (Iam = 0)
SDCLK SDCKE MA[11:10], A[10:2] A[10:0] CS2/CSD0 SDWE DQM3 DQM3 DQM2 DQM2 DQM1 DQM1 DQM0 DQM0 D[31:0] DQ[31:0] 2M x 32 MC9328MX1 SDRAM Figure 24-48. Single 64 Mbit (2M x 32) Connection Diagram (IAM = 0) 24-52 MC9328MX1 Reference Manual MOTOROLA...
Page 651: Figure 24-49 Single 128 Mbit (4M X 32) Connection Diagram (Iam = 1)
Bank–interleaved MA11 MA10 CS2/CSD0 SDWE DQM3 DQM3 DQM2 DQM2 DQM1 DQM1 DQM0 DQM0 D[31:0] DQ[31:0] SDCLK SDCKE 4M x 32 MC9328MX1 SDRAM Figure 24-49. Single 128 Mbit (4M x 32) Connection Diagram (IAM = 1) MOTOROLA SDRAM Memory Controller 24-53...
Page 652: Figure 24-50 Single 128 Mbit (4M X 32) Connection Diagram (Iam = 0)
Figure 24-50. Single 128 Mbit (4M x 32) Connection Diagram (IAM = 0) NOTE: JEDEC has not issued a standard pinout and array configuration for the 128 Mbit density memories in a x32 package option. This connection diagram is based on the PC100 Standard. 24-54 MC9328MX1 Reference Manual MOTOROLA...
Page 653: Figure 24-51 Single 256 Mbit (8M X 32) Connection Diagram (Iam = 1)
Bank-interleaved MA11 MA10 CS2/CSD0 SDWE DQM3 DQM3 DQM2 DQM2 DQM1 DQM1 DQM0 DQM0 D[31:0] DQ[31:0] SDCLK SDCKE 8M x 32 MC9328MX1 SDRAM Figure 24-51. Single 256 Mbit (8M x 32) Connection Diagram (IAM = 1) MOTOROLA SDRAM Memory Controller 24-55...
Page 654: Sdram Reset Initialization
4. After all banks are in the idle state for a minimum time of t , issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. 24-56 MC9328MX1 Reference Manual MOTOROLA...
Page 655: Figure 24-53 Sdram Power-On Initialization Sequence
Although the initialization sequence described in the previous paragraphs is only required at power-on, it may be repeated at any time the programmer deems necessary. Code Example 24-2 on page 24-58 provides the code necessary for the initialization sequence. MOTOROLA SDRAM Memory Controller 24-57...
Page 656: Mode Register Programming
MC9328MX1 external address pins. Table 24-39 on page 24-60 provides an example of which mode bits are mapped to which internal address bit for each of the given memory densities. Table 24-33. 4M x 16 Memory Configuration SDRAM Address Mode Register Bit Reserved Reserved CAS latency Burst length Content 24-58 MC9328MX1 Reference Manual MOTOROLA...
Page 657: Table 24-34 8M X 16 Memory Configuration
Table 24-37. 4M x 32 Memory Configuration SDRAM Address Mode Register Bit Reserved Reserved CAS latency Burst length Content Table 24-38. 8M x 32 Memory Configuration SDRAM Address Mode Register Bit Reserved Reserved CAS latency Burst length Content MOTOROLA SDRAM Memory Controller 24-59...
Page 658: Table 24-39 Mc9328Mx1 Sdram Memory Configuration
Table 24-39. MC9328MX1 SDRAM Memory Configuration MC9328MX1 Internal Address Bus (internal address bits are differentiated using the nomenclature A’x) Memory Config. 4Mx16Bit x 2 Chips (16Mbyte) 8Mx16Bit x 2 Chips (32 Mbyte) 16Mx16Bit x 2 Chips (64 Mbyte) 2Mx32Bit x 1 Chip (8 Mbtye) 4Mx32Bit x 1 Chip...
Page 659: Mode Register Programming Examples
Burst Length—A burst length of 8 matches the 000 = 1 Bits M2–M0 ARM920T cache line length. 001 = 2 010 = 4 011 = 8 111 = Full page (if BT = 0) 10x = Reserved 1x0 = Reserved MOTOROLA SDRAM Memory Controller 24-61...
Page 660: Table 24-42 256 Mbit Sdram Mode Register With Values
MC9328MX1 internal address for proper translation to the SDRAM memory mode register is 0x08111800. The procedure would then be to issue a Set Mode Register Command to the SDRAM memory, followed by an access (either READ or WRITE) to the SDRAM memory at address 0x08111800. 24-62 MC9328MX1 Reference Manual MOTOROLA...
Page 661: Example 2—64 Mbit Sdram Mode Register
10x = Reserved 1x0 = Reserved The values programmed into the SDRAM mode register for Example 2 are as follows: • Sequential burst (BT = 0) • Burst length of 8 (BL = 011), not optional MOTOROLA SDRAM Memory Controller 24-63...
Page 662: Table 24-46 64 Mbit Sdram Mode Register With Values
“MODE_REG_VAL0” variable of Code Example 24-2 on page 24-58. Refer to Section 24.6.5, “Set Mode Register Mode (SMODE = 011),” for more information on the Set Mode Register Command. 24-64 MC9328MX1 Reference Manual MOTOROLA...
Page 663: Syncflash Operation
5. Initialization is now complete. The SDRAM Controller asserts RESET_SF low anytime sd_rst is asserted. The 200 µs delay between the negation of sd_rst and negation of m_rst easily meets the 100 µs stabilization requirement of the SyncFlash. MOTOROLA SDRAM Memory Controller 24-65...
Page 664: Syncflash Mode Register Programming
The only significant difference in the software configuration is that refresh must be disabled. SyncFlash maps the control register access commands to the same basic commands as SDRAM refresh. Enabling hardware refresh would most likely result in unexpected behavior. 24-66 MC9328MX1 Reference Manual MOTOROLA...
Page 665: Figure 24-55 Single 64 Mbit Syncflash Connection Diagram (Iam = 0)
CONTROLLER SyncFlash Figure 24-55. Single 64 Mbit SyncFlash Connection Diagram (IAM = 0) Table 24-50. Dual 4M x 16 SyncFlash Control Register Values (IAM = 0) Control Field Value Density 16 Mbyte Page size 1024 MOTOROLA SDRAM Memory Controller 24-67...
Page 666: Syncflash Programming
Table 24-51 provides a quick reference of the available commands for SyncFlash operation. The detailed command encoding for SDRAM compatibility, is located in Table 24-11. All SyncFlash operations with LCR (LOAD COMMAND REGISTER), LCR/ACTIVE/READ, or LCR/ACTIVE/WRITE commands and command sequences are defined in Table 24-51 and Table 24-11. 24-68 MC9328MX1 Reference Manual MOTOROLA...
Page 667: Clock Suspend Timer Use With Syncflash
CLKST = 11). When CLKST is set to 10 or 11, the active bank is not closed (no Precharge command is issued) before the entry into the clock suspend mode. Figure 24-57 illustrates this timing relationship. MOTOROLA SDRAM Memory Controller...
Page 668: Deep Powerdown Operation With Syncflash
MC9328MX1 exits stop mode (when the MCU PLL and System PLL have waken up) and the clock to the SyncFlash is stable. The RESET_SF signal is then deasserted. Figure 24-59 illustrates the operation of the SyncFlash when entering deep powerdown mode. 24-70 MC9328MX1 Reference Manual MOTOROLA...
Page 669: Figure 24-59 Syncflash Deep Powerdown Operation Timing Diagram
Deep Powerdown Operation with SyncFlash Low-Power normal MC9328MX1 Stop Mode (PLLs shutdown) normal Mode Signal from CPU SDCLK SDCKEx ADDR RP (Minimum) RAS, PRE-ALL CAS, SDWE CSDx reset_sf Figure 24-59. SyncFlash Deep Powerdown Operation Timing Diagram MOTOROLA SDRAM Memory Controller 24-71...
Page 670 SDRAM Memory Controller 24-72 MC9328MX1 Reference Manual MOTOROLA...
Page 671: Module Overview
The IP bus provides the interface between the ARM920T processor of the MC9328MX1 and the SIM. Communication between the SIM and the rest of the module is handled by internal signals that are not available to or programmable by the user. MOTOROLA SmartCard Interface Module (SIM) 25-1...
Page 672: Sim Clock Generator
(inverse convention or direct convention). NACK detection, eleven elementary time unit (ETU) character support, and a character wait time counter are provided. The SIM receiver generates the three interrupts shown in Table 25-2. 25-2 MC9328MX1 Reference Manual MOTOROLA...
Page 673: Sim Port Control
The SIM generates linear redundancy check (LRC) information for both received and transmitted characters. The LRC portion of the SIM contains a valid LRC detector and produces an 8-bit LRC value. The LRC does not generate any interrupts. MOTOROLA SmartCard Interface Module (SIM) 25-3...
Page 674: Functional Description
50% duty at all divide values to meet the requirements of the ISO 7816 specification. The baud_clk that is used internal to the SIM is generated as a gated version of the IPS_CONT_CLK clock. The resultant clock is a pulse of one-half IPS_CONT_CLK period in width with the expected frequency. 25-4 MC9328MX1 Reference Manual MOTOROLA...
Page 675: Transmitter Clock Generation
The transmit state machine is the heart of the transmitter block. The state machine is responsible for sequencing through a transmit operation while reacting to inputs from the receiver, the transmit FIFO, and the guard time circuit. Figure 25-3 below depicts the transmit state machine operation. MOTOROLA SmartCard Interface Module (SIM) 25-5...
Page 676: Figure 25-3 Transmit State Machine Operation Diagram
— The state machine remains in the GUARD_WAIT state until the guard time counter has expired. – When a transmit NACK error occurred on the last transmission, jump to RTX_MAIN_XMIT and re-transmit. – When no transmit NACK error occurred and the FIFO is not empty, load the shift register 25-6 MC9328MX1 Reference Manual MOTOROLA...
Page 677: Transmit Shift Register
(ETUs). The duration of the count is controlled by the GUARD_CNTL register (GETU). Figure 25-4 depicts three transmit operations that demonstrate the effect of the guard time generator logic. MOTOROLA SmartCard Interface Module (SIM) 25-7...
Page 678: Transmit Nack Generator
P Stop Bits Start Byte Without NACK NACK sample time 11 ETUs 2 min Retransmission Error Byte Byte Start Start Signal 10.5 ETUs NACK With NACK 1 min, 2 max Figure 25-5. Transmit NACK Operation 25-8 MC9328MX1 Reference Manual MOTOROLA...
Page 679: Transmit Data Convention Logic
This mode is used only when the BAUD_SEL bits in the CNTL register are set to 000. The number following the oversampling mode identifier represents the state number in the current mode. There are 12 MOTOROLA SmartCard Interface Module (SIM)
Page 680 — This state represents the end of the current receive input bit. This state increments the bit counter, performs a majority vote on the NACK samples, and notifies the transmitter when a NACK pulse was detected. 25-10 MC9328MX1 Reference Manual MOTOROLA...
Page 681: Data Sampling / Voting
10th bit of the received data. The parity of the 2nd through 10th received bits is calculated by the receiver parity logic. This logic determines if the parity of the 9 received bits is correct. Figure 25-9 shows a typical SIM data transaction with the parity bit identified. MOTOROLA SmartCard Interface Module (SIM) 25-11...
Page 682: Framing Error Detection
An ETU is equivalent in time to one transmit clock period. Once the receiver detects a NACK, it signals the transmitter that an error occurred. The transmitter waits for at least another two ETUs before initiating retransmission, as required by the ISO 7816 specification. 25-12 MC9328MX1 Reference Manual MOTOROLA...
Page 683: Initial Character Detection
FIFO, the receive FIFO write pointer is incremented. When the difference between the read and write pointers equals the value in the receive data threshold (RDT) bits in MOTOROLA SmartCard Interface Module (SIM) 25-13...
Page 684: Overrun Detection
2.7V operation, method 1. The 3VOLT bit in the port control (PORT_CNTL) register configures the SIM port transmit output as bi-directional. This frees up the SIM port receive pin for use as a general purpose I/O. 25-14 MC9328MX1 Reference Manual MOTOROLA...
Page 685: Smartcard Presence Detect
The powerdown sequence is specified in ISO 7816 as: 1. RST transitions from high to low. 2. CLK is turned off to a low. 3. I/O transitions from tri-state to low. 4. SIM Vcc is turned off. MOTOROLA SmartCard Interface Module (SIM) 25-15...
Page 686: Sim General Purpose Counter
FIFO is sent when XMT_EN_LRC_CRC is clear), the LRC value is automatically reset by the SIM hardware. Finally, when setting the XMT_EN bit in the ENABLE register, the SIM hardware resets the LRC value. 25-16 MC9328MX1 Reference Manual MOTOROLA...
Page 687: Sim Crc Block
CRC block updates the current value of each character in the CRC residual. When the XMT_EN_LRC_CRC bit in the CNTL register is set, the CRC value is automatically inverted and sent by the SIM transmitter as the final two characters when the transmit FIFO empties. MOTOROLA SmartCard Interface Module (SIM) 25-17...
Page 688: Pin Configuration For Sim
25.5 Pin Configuration for SIM Figure 25-13 on page 25-15 shows the pins used for the SIM module. These pins are multiplexed with other functions on the device, and must be configured for SIM operation. 25-18 MC9328MX1 Reference Manual MOTOROLA...
Page 689: Table 25-6 Pin Configuration
Receive Threshold Register RCV_THRESHOLD 0x00211008 Transmit/Receive Enable Register ENABLE 0x0021100C Transmit Status Register XMT_STATUS 0x00211010 Receive Status Register RCV_STATUS 0x00211014 Interrupt Mask Register INT_MASK 0x00211018 Port Transmit Buffer Register XMT_BUF 0x0021101C Receive Buffer Register RCV_BUF 0x00211020 MOTOROLA SmartCard Interface Module (SIM) 25-19...
Page 690: Table 25-8 Register Field Summary
0x00211038 General Purpose Counter Register GPCNT 0x0021103C Divisor Register DIVISOR 0x00211040 Table 25-8. Register Field Summary Register 31:16 Name PORT_CNTL 0x000 CNTL 0x000 RCV_THRESH 0x000 ENABLE 0x000 XMT_STATUS 0x000 RCV_STATUS 0x000 INT_MASK 0x000 XMT_BUF 0x000 25-20 MC9328MX1 Reference Manual MOTOROLA...
Page 691 Programming Model Table 25-8. Register Field Summary (Continued) Register 31:16 Name RCV_BUF 0x000 PORT_DETEC 0x000 XMT_THRESH 0x000 GUARD_CNTL 0x000 OD_CONFIG 0x000 RESET_CNTL 0x000 CHAR_WAIT 0x000 CHARACTER WAIT TIME GPCNT 0x000 GPCNT DIVISOR 0x000 DIVISOR MOTOROLA SmartCard Interface Module (SIM) 25-21...
Page 692: Port Control Register
0 = Transmit data is forced to Bit 2 data to the SIM card. It can be forced low by hardware during the zero auto powerdown sequence. 1 = Transmit data controlled by SIM module 25-22 MC9328MX1 Reference Manual MOTOROLA...
Page 693: Control Register
Transmit CRC or LRC—Controls whether or not 1 = Transmit CRC or LRC (whichever is to transmit the redundancy check data at the end Bit 15 of a transmission (when the FIFO becomes enabled) info when the FIFO empties empty). MOTOROLA SmartCard Interface Module (SIM) 25-23...
Page 694 010 = IPG_CLK / 8 SmartCard. 011 = IPG_CLK / 12 100 = IPG_CLK / 16 101 = M_CLK / 20 110 = M_CLK / 25 111 = Reserved 25-24 MC9328MX1 Reference Manual MOTOROLA...
Page 695: Receive Threshold Register
FIFO to trigger the receive data register full (RDRF) interrupt flag. The RDT field description for the Receive Threshold Register is provided in Table 25-11. Addr RCV_THRESHOLD Receive Threshold Register 0x00211008 TYPE RESET 0x0000 TYPE RESET 0x0001 MOTOROLA SmartCard Interface Module (SIM) 25-25...
Page 696: Transmit/Receive Enable Register
When the transmitter has completed enabled sending the last character, the receiver is automatically enabled. This bit also enables the RCV_CLK input to the general purpose counter. 25-26 MC9328MX1 Reference Manual MOTOROLA...
Page 697: Transmit Status Register
1 = A transmit FIFO overfill error has creates an interrupt when the TFOM bit in the INT_MASK register is low. The TFO bit is cleared by writing 1 to it. occurred MOTOROLA SmartCard Interface Module (SIM) 25-27...
Page 698 Note: The TC, ETC, and TFE flags reflect the actual conditions after at least 1 byte of data is written to the transmit FIFO. Clearing these bits (write 1 to clear) when the FIFO is empty does not cause them to set to high (actual condition). 25-28 MC9328MX1 Reference Manual MOTOROLA...
Page 699: Receive Status Register
(zero) • Clear the LRCEN bit in CNTL register • Set the XMT_EN bit in the ENABLE register • Automatically reset by hardware when ETC flag is set at the end of a transmission. MOTOROLA SmartCard Interface Module (SIM) 25-29...
Page 700 OEF flag set are lost (including the byte that caused the bit to set). The OEF flag causes an interrupt when the OIM bit is set in the INT_MASK register. The OEF flag is a write-one-to-clear bit. 25-30 MC9328MX1 Reference Manual MOTOROLA...
Page 701: Interrupt Mask Register
SIM interrupts. 0 = ETC interrupt enabled ETCIM Early Transmit Complete Interrupt Mask—Enables/Disables 1 = ETC interrupt masked Bit 3 the ability of the ETC flag in the RCV_STATUS register to generate SIM interrupts. MOTOROLA SmartCard Interface Module (SIM) 25-31...
Page 702: Port Transmit Buffer Register
Transmit Buffer—Holds data for transmitting. This register contains the last data written to it. Upon Bits 7–0 reset the value of the data in this register is undefined. Note: Writing more data to the transmit FIFO than it can hold (16 bytes) causes a transmit FIFO overfill error. 25-32 MC9328MX1 Reference Manual MOTOROLA...
Page 703: Receive Buffer Register
It need not be cleared because it is overwritten parity error by the next byte received into that location of the FIFO. Receive Buffer—Contains data from the next location in the receive buffer. Bits 7–0 MOTOROLA SmartCard Interface Module (SIM) 25-33...
Page 704: Port Detect Register
1 = Insertion or removal of when SDIM is low. Write 1 to clear. SmartCard detected 0 = SDI enabled SDIM SIM Detect Interrupt Mask—Masks the SDI interrupt flag. 1 = SDI masked Bit 0 25-34 MC9328MX1 Reference Manual MOTOROLA...
Page 705: Transmit Threshold Register
Transmit Data Threshold—Sets the threshold value for the Transmit FIFO at which the TDTF bit in Bits 3–0 the XMT_STATUS register is set. When the number of bytes in the Transmit FIFO is less than or equal to TDT, TDTF is set. MOTOROLA SmartCard Interface Module (SIM) 25-35...
Page 706: Transmit Guard Control Register
The guard time has no effect on the SIM receiver. A value of 0x00 inserts no additional ETUs, while a value of 0xFE inserts 254 additional ETUs. A value of 0xFF subtracts one ETU by reducing the number of STOP bits from two to one. 25-36 MC9328MX1 Reference Manual MOTOROLA...
Page 707: Open-Drain Configuration Control Register
Reserved—These bits are reserved and should read 0. Bits 31–1 0 = XMT pin on is push-pull OD_P Open Drain/Push-Pull Control—Controls whether the XMT 1 = XMT pin on is open-drain Bit 0 data line is open-drain. MOTOROLA SmartCard Interface Module (SIM) 25-37...
Page 708: Table 25-22 Reset Control Register Description
Flush Receiver—Operates as a SIM receiver reset. The 1 = SIM receiver held in reset Bit 0 transmit portion of the SIM is not affected. The software must clear FLUSH_RCV before the SIM receiver can operate. 25-38 MC9328MX1 Reference Manual MOTOROLA...
Page 709: Character Wait Timer Register
Table 25-23. Character Wait Timer Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 CHARACTER WAIT TIME Character Wait Time—Specifies the number of ETUs allowed between Bits 15–0 characters. MOTOROLA SmartCard Interface Module (SIM) 25-39...
Page 710: General Purpose Counter Register
This counter is intended for use on any events that must be monitored for duration based on the card clock, receiver sample rate, or ETU rate (such as ATR arrival time, ATR duration, and so on). 25-40 MC9328MX1 Reference Manual MOTOROLA...
Page 711: Divisor Register
Table 25-26. Configuring the SIM for Operation Step Action Reference Enable the SIM through the SIM_EN bit in the ENABLE register. Section 25.6.4, “Transmit/Receive Enable Register,” on page 25-26 MOTOROLA SmartCard Interface Module (SIM) 25-41...
Page 712: Table 25-27 Configuring The Sim Receiver
ONACK bit in the CNTL register. Select the desired receive FIFO threshold by programming the RDT Section 25.6.3, “Receive Threshold bits in the RCV_THRESHOLD register to the threshold at which the Register,” on page 25-25 RDRF flag is set. 25-42 MC9328MX1 Reference Manual MOTOROLA...
Page 713: Table 25-28 Configuring The Sim Transmitter
Enable the transmit FIFO empty interrupt through the TFEIM bit. d. Enable the transmit threshold error interrupt through the XTM bit. e. Enable the transmit FIFO threshold interrupt through the TDTFM bit. f. Enable the transmit FIFO overfill interrupt through the TFOM bit. MOTOROLA SmartCard Interface Module (SIM) 25-43...
Page 714: Table 25-29 Configuring The Sim General Purpose Counter
Use the XMT_EN_LRC_CRC bit to enable the transmission of the Section 25.10.2.3 on page 25-54 LRC Character after the last character in the Transmit FIFO is sent. See the T = 1 programming model for more details. 25-44 MC9328MX1 Reference Manual MOTOROLA...
Page 715: Using The Sim Receiver
RDRF to cause an interrupt (RIM clear), and then read bytes out of the receive FIFO as long as RFD is high. In addition to checking RFD between every byte, it is also recommended that software check for the existence of a set OEF flags as well. MOTOROLA SmartCard Interface Module (SIM) 25-45...
Page 716: Receive Parity Errors And Parity Nack Generation
NACK other than to disable ONACK itself. When generating a NACK pulse, the SIM generates the low pulse starting at 10.5 ETUs and lasting for 1 ETU (see Figure 25-5 on page 25-8). 25-46 MC9328MX1 Reference Manual MOTOROLA...
Page 717: Using Initial Character Mode And Resulting Receive Data Formats
(0x3F). The SIM does not recognize this as a valid initial character for inverse convention and marks the character by setting the parity error flag. The software must check for the existence of a parity error before recognizing a character as a valid initial character. MOTOROLA SmartCard Interface Module (SIM) 25-47...
Page 718: Automatic Receiver Mode
FIFO, the transmitter begins to send the first character. When no data is written to the transmit FIFO before enabling the transmitter, then the transmitter waits until the first 25-48 MC9328MX1 Reference Manual MOTOROLA...
Page 719: Transmit Data Formats
The only way to clear XTE is to write 1 to the XTE bit in the XMT_THRESHOLD register (see page 25-35). The XTE flag can create an interrupt when the XTM mask in the XMT_THRESHOLD register is clear. MOTOROLA SmartCard Interface Module (SIM) 25-49...
Page 720: Transmit Guard Time
The value of BGT is 22 ETUs. The SIM supports the BGT by providing the ability to generate an interrupt when the last byte is received, and transmitting within 2 ETUs after the XMT_EN bit in the ENABLE register is set. The BGT 25-50 MC9328MX1 Reference Manual MOTOROLA...
Page 721: Answer To Reset (Atr) Detection
SIM to NACK any communication errors that occur during the initial communication at 12 ETUs. NOTE: The Europay Mastercard and VISA (EMV) cards are similar to T = 1, however, they do not allow the SIM to NACK during the initial MOTOROLA SmartCard Interface Module (SIM) 25-51...
Page 722: Programming Considerations
ATR is received, the software knows from the ATR information the specific characteristics for this card (see the ISO 7816-3 specification for details). 25.10.2 Programming Considerations This section provides specific considerations when programming the Geldkate, T = 1, and T = 0 SmartCards. 25-52 MC9328MX1 Reference Manual MOTOROLA...
Page 723: Geldkate Cards
2. Adjust the guard time between characters by changing the value of GETU in the GUARD_CNTL register. 3. Adjust NACK capability by modifying the values of the ONACK and ANACK bits in the CNTL register. MOTOROLA SmartCard Interface Module (SIM) 25-53...
Page 724: T = 1 Smartcards
For T = 1 cards, the ATR is sent through a T = 0 type of structure (12 ETU, no LRC or CRC). When a negotiation with the SmartCard is desired, the software sends a PPS response to the SmartCard. Otherwise, 25-54 MC9328MX1 Reference Manual MOTOROLA...
Page 725 When the transmission is complete, the SIM is completely configured for standard operation with the T = 1 SmartCard. The software can continue to service RDRF interrupts for received characters, and TDTF interrupts for transmitted characters. MOTOROLA SmartCard Interface Module (SIM) 25-55...
Page 726 SmartCard Interface Module (SIM) 25-56 MC9328MX1 Reference Manual MOTOROLA...
Page 727: Figure 26-1 General-Purpose Timers Block Diagram
10 ns resolution at 100 MHz • Programmable sources for the clock input, including external clock • Input capture capability with programmable trigger edge • Output compare with programmable mode • Free-run and restart modes • Software reset function MOTOROLA General-Purpose Timers 26-1...
Page 728: Pin Configuration For General-Purpose Timers
2. Clear bit 1 of Port A General Purpose Register (GPR_A) TMR2OUT Primary function of 1.Clear bit 31 of Port D GPIO In Use Register (GIUS_D) GPIO Port D [31] 2. Clear bit 31 of Port D General Purpose Register (GPR_D) 26-2 MC9328MX1 Reference Manual MOTOROLA...
Page 729: Timer Control Registers 1 And 2
Selecting the free-running or restart mode after a compare event • Selecting the capture trigger event • Controlling the output compare mode • Enabling the compare event interrupt • Selecting the prescaler clock source • Enabling and disabling the GP timer MOTOROLA General-Purpose Timers 26-3...
Page 730: Table 26-3 Timer 1 And 2 Control Registers Description
This bit has no period function unless the CAP field is set to 0. When the 1 = Toggle output counter value (COUNT) period is less than 40 ns, timer out (TMR2OUT) is not valid. 26-4 MC9328MX1 Reference Manual MOTOROLA...
Page 731: Timer Prescaler Registers 1 And 2
Reserved—These bits are reserved and should read 0. Bits 31–8 PRESCALER Prescaler—Determines the division value (1–256) of the prescaler. 0x00 = Divide by 1 Bits 7–0 0x01 = Divide by 2 0xFF = Divide by 256 MOTOROLA General-Purpose Timers 26-5...
Page 732: Timer Compare Registers 1 And 2
TYPE RESET 0xFFFF COMPARE VALUE TYPE RESET 0xFFFF Table 26-5. Timer 1 and 2 Compare Registers Description Name Description COMPARE VALUE Compare Value—Holds the value at which a compare event will be triggered. Bits 31–0 26-6 MC9328MX1 Reference Manual MOTOROLA...
Page 733: Timer Capture Registers 1 And 2
RESET 0x0000 CAPTURE VALUE TYPE RESET 0x0000 Table 26-6. Timer 1 and 2 Capture Registers Description Name Description CAPTURE VALUE Capture Value—Stores the counter value that existed at the time of the capture event. Bits 31–0 MOTOROLA General-Purpose Timers 26-7...
Page 734: Timer Counter Registers 1 And 2
0x00202010 TCN2 Timer 2 Counter Register 0x00203010 COUNT TYPE RESET 0x0000 COUNT TYPE RESET 0x0000 Table 26-7. Timer 1 and 2 Counter Registers Description Name Description COUNT Counter Value—Contains the current count value. Bits 31–0 26-8 MC9328MX1 Reference Manual MOTOROLA...
Page 735: Timer Status Registers 1 And 2
0 = No capture event occurred Bit 1 1 = A capture event occurred COMP Compare Event—Indicates when a compare event occurs. 0 = No compare event occurred Bit 0 1 = A compare event occurred MOTOROLA General-Purpose Timers 26-9...
Page 736 General-Purpose Timers 26-10 MC9328MX1 Reference Manual MOTOROLA...
Page 737: Introduction
Software flow control support for data set ready (DSR), data carrier detect (DCD), and ring indicator (RI) signals on UART 2 • Edge selectable RTS and data terminal ready (DTR) edge detect interrupts 1. UART GPIO pins must be used for DTR, DSR, DCD, and RI functions. MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-1...
Page 738: Module Interface
ARM9 core from STOP mode on its assertion. When RTS is negated during a transmission, the UART transmitter finishes transmitting the current character and shuts off. The contents of the TxFIFO (characters to be transmitted) remain undisturbed. 27-2 MC9328MX1 Reference Manual MOTOROLA...
Page 739: Pin Configuration For Uart1 And Uart2
2.Clear bit 30 of Port B General Purpose Register (GPR_B) UART2_RTS Primary function of 1.Clear bit 29 of Port B GPIO In Use Register (GIUS_B) GPIO Port B [29] 2.Clear bit 29 of Port B General Purpose Register (GPR_B) MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-3...
Page 740: Table 27-3 Interrupts And Dma
USR1_1/USR1_2 (bit 5) AWAKEN UCR3_1/UCR3_2 (bit 4) AWAKE USR1_1/USR1_2 (bit 4) UART_MINT_PFRERR FRAERREN UCR3_1/UCR3_2 (bit 11) FRAERR USR1_1/USR1_2 (bit 10) PARERREN UCR3_1/UCR3_2 (bit 12) PARITYERR USR1_1/USR1_2 (bit 15) UART_RX_DMAREQ RDMAEN UCR1_1/UCR1_2 (bit 8) RRDY USR1_1/USR1_2 (bit 9) 27-4 MC9328MX1 Reference Manual MOTOROLA...
Page 741: General Uart Definitions
UART receive buffer (RxFIFO). An overrun error indicates that the software reading the buffer (RxFIFO) is not keeping up with the actual reception of characters on the RXD input. MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-5...
Page 742: Rts—Uart Request To Send
Table 27-4. RTS Edge Triggered Interrupt Truth Table RTSEN RTEC [1] RTEC [0] RTSF Interrupt Occurs On… UART_MINT_RTS Interrupt disabled 1–>0 Rising edge 0–>1 Rising edge 1–>0 Falling edge 0–>1 Falling edge 27-6 MC9328MX1 Reference Manual MOTOROLA...
Page 743: Dtr—Data Terminal Ready
Table 27-5. DTR Edge Triggered Interrupt Truth Table DTREN DPEC [1] DPEC [0] DTRF Interrupt Occurs On… UART_MINT_DTR Interrupt disabled 1–>0 Rising edge 0–>1 Rising edge 1–>0 Falling edge 0–>1 Falling edge 1–>0 Either edge 0–>1 Either edge MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-7...
Page 744: Dsr—Data Set Ready
0 bit received and no pulse is expected for each 1 bit received. External circuitry must convert the IR signal to an electrical signal. RS-232 applications require an external RS-232 receiver to convert voltage levels. 27-8 MC9328MX1 Reference Manual MOTOROLA...
Page 745: Sub-Block Description
(USR1_1/USR1_2 and USR2_1/USR2_2) and control (UCR1_1/UCR1_2, UCR2_1/UCR2_2, UCR3_1/UCR3_2, and UCR4_1/UCR4_2) functions. A separate test register is provided for applications that require it. The binary rate multiplier registers (UBIR_1/UBIR_2, UBMR_1/UBMR_2—and includes BMPR1_1/BMPR1_2 and BMPR4_1/BMPR4_2) control the UART bit rate. MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-9...
Page 746: Transmitter
Transmitter Shift Register become empty until another character is written to the Transmitter FIFO • The last character in the TxFIFO is transferred to the shift register, when TxFIFO contains two or more characters. See Figure 27-3 on page 27-11. 27-10 MC9328MX1 Reference Manual MOTOROLA...
Page 747: Receiver
(USR2_1/USR2_2) is asserted and an interrupt is posted (if DREN = 1). If the receiver trigger level is set to 0, the receiver ready interrupt flag (RRDY) is asserted and an interrupt is posted if the receiver ready MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules...
Page 748: Idle Line Detect
32 idle frames Note: This table assumes that no other interrupt is set at the same time this interrupt is set for the MINT_RX signal. This table shows how this interrupt affects the MINT_RX signal. 27-12 MC9328MX1 Reference Manual MOTOROLA...
Page 749: Receiver Wake
VOTE_CLK. The receiver is provided with the majority vote value, which is 2 out of the 3 samples. Examples of the majority vote results of the vote logic are shown in Table 27-7. MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-13...
Page 750: Binary Rate Multiplier (Brm)
The following equation can be used to help determine these values: [(Desired Baud Rate)*16]/(reference frequency)=NUM/DENOM Eqn. 27-1 UBIR = NUM - 1 Eqn. 27-2 UBMR = DENOM - 1 Eqn. 27-3 reference frequency = PERCLK1 / RFDIV [2:0] Eqn. 27-4 27-14 MC9328MX1 Reference Manual MOTOROLA...
Page 751 DENOM = 10000 (decimal) = 0x2710 NOTE: The ratio is derived directly from the division with no factoring (easiest). To derive the exact ratio, some factoring must be perform. Factoring the above ratio produces: MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-15...
Page 752: Baud Rate Automatic Detection Logic
BPEN = 1). These registers are written by software before the start of automatic baud sequence detection. After the auto baud count value is divided by 16 and a remainder higher than 3 is detected, the appropriate 27-16 MC9328MX1 Reference Manual MOTOROLA...
Page 753: Baud Rate Automatic Detection Protocol
UART Baud Rate Count Register retains its value until the next automatic baud rate detection sequence is initiated. The read only Baud Rate Count Register counts only when auto detection is enabled. MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-17...
Page 754: Escape Sequence Detection
The escape sequence detection feature is available for 16 MHz, 25 MHz or 30 MHz reference frequencies only. Enabling this feature with any other reference frequency is not supported and is undefined.Set the corresponding reference frequency bits (REF16 in UCR4_1/UCR4_2, REF25 or REF30 in UCR3_1/UCR3_2). 27-18 MC9328MX1 Reference Manual MOTOROLA...
Page 755: Infrared Interface
UART1 Transmitter Register n UTXnD_1 0x00206040+4*n UART1 Control Register 1 UCR1_1 0x00206080 UART1 Control Register 2 UCR2_1 0x00206084 UART1 Control Register 3 UCR3_1 0x00206088 UART1 Control Register 4 UCR4_1 0x0020608C UART1 FIFO Control Register UFCR_1 0x00206090 MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-19...
Page 756 UART2 FIFO Control Register UFCR_2 0x00207090 UART2 Status Register 1 USR1_2 0x00207094 UART2 Status Register 2 USR2_2 0x00207098 UART2 Escape Character Register UESC_2 0x0020709C UART2 Escape Timer Register UTIM_2 0x002070A0 UART2 BRM Incremental Register UBIR_2 0x002070A4 27-20 MC9328MX1 Reference Manual MOTOROLA...
Page 757 UART2 BRM Modulator Preset Register 1 BMPR1_2 0x002070C0 UART2 BRM Modulator Preset Register 2 BMPR2_2 0x002070C4 UART2 BRM Modulator Preset Register 3 BMPR3_2 0x002070C8 UART2 BRM Modulator Preset Register 4 BMPR4_2 0x002070CC UART2 Test Register 1 UTS_2 0x002070D0 MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-21...
Page 758: Uart Receiver Registers
0 = An error status was detected Bit 14 the RX_DATA field has an error (OVRRUN, FRMERR, 1 = No error status was detected BRK or PRERR) status. The ERR bit is updated and valid for each received character. 27-22 MC9328MX1 Reference Manual MOTOROLA...
Page 759: Table 27-12 Uart1 Receiver Register N
Reserved—These bits are reserved and should read 0. Bits 9–8 RX_DATA Received Data—Holds the received character. In 7-bit mode, the most significant bit (MSB) is Bits 7–0 forced to 0. In 8-bit mode, all bits are active. MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-23...
Page 760: Uart Transmitter Registers
Data is transmitted least significant bit (LSB) first. A new character is transmitted when the TX_DATA field is written. The TX_DATA field must be written only when the TRDY bit is high to ensure that corrupted data is not sent. 27-24 MC9328MX1 Reference Manual MOTOROLA...
Page 761: Uart Control Register 1
IDEN Idle Condition Detected Interrupt 0 = Disable the IDLE bit Bit 12 Enable—Enables/Disables the IDLE bit to generate an 1 = Enable the IDLE bit interrupt (UART_MINT_RX = 0). MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-25...
Page 762 The fill level in the TxFIFO that generates the UART_TX_DMAREQ is controlled by the TXTL bits. 0 = Disable UART clocks UARTCLKEN UART Clock Enable—Enables/Disables all of the Bit 2 1 = Enable UART clocks internal clocks of the UART module 27-26 MC9328MX1 Reference Manual MOTOROLA...
Page 763 UART Enable—Enables/Disables the UART. If UARTEN 1 = Enable the UART Bit 0 is negated in the middle of a transmission, the transmitter stops and pulls the TXD line to a logic 1. MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-27...
Page 764: Uart Control Register 2
On reset, because CTSC is cleared to 0, the UARTx_CTS pin is controlled by the CTS bit, which again is cleared to 0 on reset. This means that on reset the UARTx_CTS signal is negated. 27-28 MC9328MX1 Reference Manual MOTOROLA...
Page 765 1 = Enable the transmitter UARTEN and TXEN bits are set the transmitter is enabled. If TXEN is negated in the middle of a transmission, the UART disables the transmitter immediately, and starts marking 1s. MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-29...
Page 766 0 to SRST, the software reset remains active for 4 clock all status registers cycles of CKIH before the hardware deasserts SRST. The 1 = No reset software can only write 0 to SRST. Writing 1 to SRST is ignored. 27-30 MC9328MX1 Reference Manual MOTOROLA...
Page 767: Uart Control Register 3
0 = Disable the AIRINT interrupt Bit 5 Enable—Controls the asynchronous IR WAKE 1 = Enable the AIRINT interrupt interrupt. An interrupt is generated when AIRINTEN is asserted and a pulse is detected on the UART_RX pin. MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-31...
Page 768 If the criteria is not met for selecting one of the preset registers, integer division is performed by writing one less than the dividend to the UBMR_1/UBMR_2 register. 27-32 MC9328MX1 Reference Manual MOTOROLA...
Page 769: Uart2 Control Register 3
1 = The UART_DCD pin is logic 1 Ring Indicator—Selects the logic level for the 0 = The UART_RI pin is logic 0 Bit 8 UART_RI pin for the modem interface. 1 = The UART_RI pin is logic 1 MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-33...
Page 770 If the criteria is not met for selecting one of the preset registers, integer division is performed by writing one less than the dividend to the UBMR_1/UBMR_2 register. 27-34 MC9328MX1 Reference Manual MOTOROLA...
Page 771: Uart Control Register 4
0 = 16 MHz reference clock not used Bit 6 that a reference clock of 16 MHz is used. The reference 1 = 16 MHz reference clock is used clock is derived from input clock IPG_CLK via the programmable divider. MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-35...
Page 772 ORE bit to generate an interrupt (UART_MINT_UARTC 1 = Enable ORE interrupt DREN Receive Data Ready Interrupt Enable—Enables/Disables 0 = Disable RDR interrupt Bit 0 the RDR bit to generate an interrupt (MINT_RX 1 = Enable RDR interrupt 27-36 MC9328MX1 Reference Manual MOTOROLA...
Page 773: Uart Fifo Control Registers
10 1 = Divide input clock by 1 clock IPB_CLK. 11 0 = Divide input clock by 7 Reserved Reserved—This bit is reserved and should read 0. Bit 6 MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-37...
Page 774 011111 = RxFIFO has 31 characters whenever the data level in the RxFIFO 100000 = RxFIFO has 32 characters (maximum) reaches the selected threshold. The All Other Settings Reserved RXTL bits are encoded as shown in the Settings column. 27-38 MC9328MX1 Reference Manual MOTOROLA...
Page 775: Uart Status Register 1
UARTx_RTS pin is available on the RTSS bit. 1 = UARTx_RTS pin changed Clear RTSD by writing 1 to it. Writing 0 to RTSD has no effect. At state (write 1 to clear) reset, RTSD is set to 0. MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-39...
Page 776 RXD pin it. Writing 0 to AWAKE has no effect. 1 = A falling edge was detected on the RXD pin Reserved Reserved—These bits are reserved and should read 0. Bits 3–0 27-40 MC9328MX1 Reference Manual MOTOROLA...
Page 777: Uart Status Register 2
The UART_MINT_RX interrupt generated by this IDLE bit is 1 to clear) cleared by writing 1 to IDLE. Writing 0 to IDLE has no effect. Reserved Reserved—These bits are reserved and should read 0. Bits 11–9 MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-41...
Page 778 0 = No receive data ready Bit 0 received and written to the RxFIFO. If the URXDn_1 or 1 = Receive data ready URXDn_2 register is read and there is only 1 character in the RxFIFO, RDR is automatically cleared. 27-42 MC9328MX1 Reference Manual MOTOROLA...
Page 779: Table 27-22 Uart1 Escape Character Register And Uart2 Escape Character Register Description
Reserved Reserved—These bits are reserved and should read 0. Bits 31–8 ESC_CHAR UART Escape Character—Holds the selected escape character that all received characters Bits 7–0 are compared against to detect an escape sequence. MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-43...
Page 780: Uart Escape Timer Registers
Table 27-23. UART1 Escape Timer Register and UART2 Escape Timer Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–12 UART Escape Timer—Holds the maximum interval allowed between escape characters. Bits 11–0 27-44 MC9328MX1 Reference Manual MOTOROLA...
Page 781: Uart Brm Incremental Registers
Incremental Numerator —Holds the numerator value minus one of the BRM ratio (see Section Bits 15–0 27.5.8). Updating this field using byte accesses is not recommended and is undefined. This register cannot be written to by the user if ADBR=1. MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-45...
Page 782: Uart Brm Modulator Registers
Reserved—These bits are reserved and should read 0. Bits 31–16 Modulator Denominator—Holds the value of the denominator minus one of the BRM ratio (see Bits 15–0 Section 27.5.8). Updating this register using byte accesses is not recommended and undefined. 27-46 MC9328MX1 Reference Manual MOTOROLA...
Page 783: Uart Baud Rate Count Registers
Bits 31–16 BCNT Baud Rate Count Register—Counts or measures the length of the incoming baud rate start bit Bits 15–0 when in automatic baud rate detection mode. This register is clocked by the BRM_CLK. MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-47...
Page 784: Uart Brm Incremental Preset Registers 1–4
Bits 15–0 when in automatic detect mode. BIPR1 register is for the 920 Kbps BIPR2 register is for the 460 Kbps BIPR3 register is for the 230 Kbps BIPR4 register is for the 115.2 Kbps 27-48 MC9328MX1 Reference Manual MOTOROLA...
Page 785: Uart Brm Modulator Preset Registers 1-4
BRM MOD Preset Registers—Holds the appropriate numerator for the special baud rates when in Bits 15–0 automatic detect mode. BMPR1_1/BMPR1_2 register is for 920 Kbps BMPR2_1/BMPR2_2 register is for 460 Kbps BMPR3_1/BMPR3_2 register is for 230 Kbps BMPR4_1/BMPR4_2 register is for 115.2 Kbps MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-49...
Page 786: Uart Test Register 1
Bit 4 RXFULL RxFIFO FULL—Indicates the RxFIFO is full. 0 = The RxFIFO is not full 1 = The RxFIFO is full Bit 3 Reserved Reserved—These bits are reserved and should read 0. Bits 2–1 27-50 MC9328MX1 Reference Manual MOTOROLA...
Page 787: Uart Operation In Low-Power System States
After the settling time of the USB_PLL, actual characters can be sent to the UART. Even though the dummy character is written to RxFIFO, just ignore it. MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules 27-51...
Page 788: Figure 27-5 Majority Vote Results
111 111 111 111 111 111 110 100 000 000 000 000 000 000 000 000 000 000 000 000 000 001 011 111 110 VOTE start bit RECEIVE_SR [7:0] 00000000 UBRC 09 0A 0B 0C 0D 0E 0F 10 10 10 10 Figure 27-6. Baud Rate Detection of Divisor 27-52 MC9328MX1 Reference Manual MOTOROLA...
Page 789: Introduction
0 to 1023 bytes. • Remote wake-up feature is supported through a register bit. • The USB module operation is programmable as self-powered or bus-powered. • Full speed (12 MHz) operation. MOTOROLA USB Device Port 28-1...
Page 790: Table 28-1 Endpoint Configurations
Ctrl, Int, Bulk, or Iso Optional IN or OUT 32 bytes Ctrl, Int, Bulk, or Iso Optional IN or OUT 32 bytes Ctrl, Int, Bulk, or Iso Optional IN or OUT 32 bytes Ctrl, Int, Bulk, or Iso Optional 28-2 MC9328MX1 Reference Manual MOTOROLA...
Page 791: Module Components
It provides the following features: • Complies with USB Specification revision 1.1 • Supports USB protocol handling MOTOROLA USB Device Port 28-3...
Page 792: Synchronization And Transaction Decode
This requirement results in one FIFO per USB endpoint. Depending on the traffic requirements, the FIFO sizes are adjustable to support double buffering. Typically, bulk and isochronous endpoints are double buffered, while interrupt and control endpoints usually are single buffered. 28-4 MC9328MX1 Reference Manual MOTOROLA...
Page 793: Control Logic
D+/D- signal (to the host connection) according to the signal in USBD_VPO and USBD_VMO (output signal), respectively. USBD_VMO/USBD_VPO—USB Module Data Output. These signals provide single ended data • to the USB Transceiver Transmitter differential driver. MOTOROLA USB Device Port 28-5...
Page 794: Pin Configuration For Usb
2.Clear bit 24 of Port B General Purpose Register (GPR_B) USBD_RCV Primary function of 1.Clear bit 22 of Port B GPIO In Use Register (GIUS_B) GPIO Port B [22] 2.Clear bit 22 of Port B General Purpose Register (GPR_B) 28-6 MC9328MX1 Reference Manual MOTOROLA...
Page 795: Table 28-3 Usb Module Register Memory Map
0x00212054+ (n*0x30) Endpoint n FIFO Write Pointer Register USB_EPn_FWRP 0x00212058+ (n*0x30) The parameter ‘n’ refers to the number of endpoints programmed into this device through MPP software in RTL and ranges from 0 to 5. MOTOROLA USB Device Port 28-7...
Page 796: Usb Frame Number And Match Register
MATCH field, a FRAME_MATCH interrupt is generated (if not masked). Reserved Reserved—These bits are reserved and should read 0. Bits 15–11 FRAME Frame Field—Holds the frame number decoded from the SOF (Start of Frame) packet that leads Bits 10–0 each USB frame. 28-8 MC9328MX1 Reference Manual MOTOROLA...
Page 797: Usb Specification And Release Number Register
Reserved—These bits are reserved and should be set to 0. Bits 31–12 SPEC Specification Number—Contains the version of USB These 12 bits represent the version Bits 11–0 specification with which the underlying USB core number of the specification. complies. 0x110 = version 1.1 MOTOROLA USB Device Port 28-9...
Page 798: Usb Status Register
Bits 6–5 “Configuration Download.” INTF Interface—Identifies the USB interface in the current configuration that is associated with the Bits 4–3 Alternative Interface Indicator (AINTF). ALTSET Alternate Setting—Contains the currently selected USB alternate setting. Bits 2–0 28-10 MC9328MX1 Reference Manual MOTOROLA...
Page 799: Usb Control Register
1 = USB module front-end logic is registers are programmed appropriately before enabling enabled and ready to communications. USB_ENA does not affect the underlying communicate with the host. UDC core, only the front-end logic’s ability to communicate with the core. MOTOROLA USB Device Port 28-11...
Page 800: Table 28-8 Device Request Status
RESUME has no effect. Table 28-8. Device Request Status Result of Transfer CMD_OVER CMD_ERROR Application processed the device request successfully Application encountered an error while processing the request Application is busy completing the request 28-12 MC9328MX1 Reference Manual MOTOROLA...
Page 801: Usb Descriptor Ram Address Register
Desired RAM Address—Holds the desired RAM address. The user programs a desired descriptor Bits 8–0 RAM address into the DADR field and follows it with a read or write to the USB_DDAT register to complete the access. MOTOROLA USB Device Port 28-13...
Page 802: Usb Descriptor Ram/Endpoint Buffer Data Register
DDAT—Allows user access to the endpoint buffer in the UDC module when the endpoint Bits 7–0 configuration is happening. (When the CFG bit in the USB_DADR is set) Writing to this field loads the data written into the UDC endpoint buffers. 28-14 MC9328MX1 Reference Manual MOTOROLA...
Page 803: Usb Interrupt Status Register
Start-of-Frame Interrupt—Indicates if a 0 = No start-of-frame received Bit 6 start-of-frame was received. 1 = The UDE module received a start-of-frame token (the USB frame number is current) MOTOROLA USB Device Port 28-15...
Page 804 Configuration Change—Indicates if a change 0 = No configuration change occurred Bit 0 occurred in the USB configuration (configuration, 1 = Configuration change occurred interface, alternate) which requires the software to reread the USB Status Register. 28-16 MC9328MX1 Reference Manual MOTOROLA...
Page 805: Usb Interrupt Mask Register
Frame Match Mask—Enables/Disables the 0 = Interrupt enabled (unmasked) Bit 1 FRAME_MATCH interrupt. 1 = Interrupt disabled (masked) CFG_CHG Configuration Change Mask—Enables/Disables the 0 = Interrupt enabled (unmasked) Bit 0 CFG_CHG interrupt. 1 = Interrupt disabled (masked) MOTOROLA USB Device Port 28-17...
Page 806: Usb Enable Register
USB_EPn_FDAT Register Size—Determines the 0 = USB_EPn_FDAT is 32 bits Bit 0 size of the Endpoint n FIFO Data Register wide (USB_EPn_FDAT). This bit must always be set to 0. 1 = USB_EPn_FDAT is 8 bits wide 28-18 MC9328MX1 Reference Manual MOTOROLA...
Page 807: Endpoint N Status/Control Registers
1 = Setup data is currently being transferred from host to device Transfer Direction—Sets the endpoint direction (DIR is 0 = OUT endpoint Bit 7 ignored for control endpoints). (from host to device) 1 = IN endpoint (from device to host) MOTOROLA USB Device Port 28-19...
Page 808: Endpoint N Interrupt Status Registers
If a register write occurs at the same time an interrupt is received, the interrupt takes precedence over the write. The number of Endpoint n Interrupt Status Registers in the MC9328MX1 depends on the number of endpoints configured. 28-20 MC9328MX1 Reference Manual MOTOROLA...
Page 809: Table 28-15 Endpoint N Interrupt Status Registers Description
4xGR value from the transmit mode (USB IN). Endpoint n FIFO Control Register 1 = The number of data bytes in the FIFO is less than ALRM value from the Endpoint n FIFO Alarm Register MOTOROLA USB Device Port 28-21...
Page 810 FIFO and the UDC and 1 = End-of-frame (USB packet) indicates when the end of a USB packet is written into sent/received the FIFO or the UDC as the end of a frame. 28-22 MC9328MX1 Reference Manual MOTOROLA...
Page 811: Endpoint N Interrupt Mask Registers
0 = Interrupt enabled (unmasked) Bit 5 High Alarm interrupt. 1 = Interrupt disabled (masked) FIFO_LOW FIFO Low Alarm Mask—Enables/Disables the FIFO Low 0 = Interrupt enabled (unmasked) Bit 4 Alarm interrupt. 1 = Interrupt disabled (masked) MOTOROLA USB Device Port 28-23...
Page 812 Device Request Mask—Enables/Disables the Device 0 = Interrupt enabled (unmasked) Bit 1 Request interrupt. 1 = Interrupt disabled (masked) End-of-Frame Mask—Enables/Disables the end-of-frame 0 = Interrupt enabled (unmasked) Bit 0 interrupt. 1 = Interrupt disabled (masked) 28-24 MC9328MX1 Reference Manual MOTOROLA...
Page 813: Endpoint N Fifo Data Registers
TYPE RESET 0x0000 Table 28-17. Endpoint n FIFO Data Registers Description Name Description TXDATA [31:0] Transmit Data—Contains the transmit FIFO write data. Bits 31–0 RXDATA [31:0] Read Data—Contains the receive FIFO read data. Bits 31–0 MOTOROLA USB Device Port 28-25...
Page 814: Endpoint N Fifo Status Registers
Frame Status Bit 2—Indicates whether a frame boundary 0 = No frame boundary on the Bit 25 exists in bus bits [15:8] for non-DMA applications. [15:8] byte 1 = A frame boundary has occurred on the [15:8] byte of the bus 28-26 MC9328MX1 Reference Manual MOTOROLA...
Page 815 FIFO Empty—Indicates FIFO empty status. Write 1 to EMPTY 0 = The FIFO is not empty Bit 16 to clear it. 1 = The FIFO is empty Reserved Reserved—These bits are reserved and should read 0. Bits 15–0 MOTOROLA USB Device Port 28-27...
Page 816: Endpoint N Fifo Control Registers
1 = Next write to FIFO data register is the current data frame. end-of-frame Reserved Reserved—This bit is reserved and should read 0. Bit 28 28-28 MC9328MX1 Reference Manual MOTOROLA...
Page 817 GR free bytes remaining in the FIFO. The direction, type, and packet size are defined in the Endpoint n Status/Control Register. Reserved Reserved—These bits are reserved and should read 0. Bits 23–0 MOTOROLA USB Device Port 28-29...
Page 818: Endpoint N Last Read Frame Pointer Registers
LRFP indicates the point to begin retransmission of the data frame. There are no safeguards to prevent retransmitting data that was overwritten. When the FRAME bit is not set, this pointer has no meaning. 28-30 MC9328MX1 Reference Manual MOTOROLA...
Page 819: Endpoint N Last Write Frame Pointer Registers
Data between the LRFP and write pointer is an incomplete frame, while data between the read pointer and the LWFP is received as whole frames. When the FRAME bit is not set, this pointer has no meaning. MOTOROLA USB Device Port 28-31...
Page 820: Endpoint N Fifo Alarm Registers
A “high level” service request is asserted when there are less than ALRM bytes free in the FIFO. A “low level” service request asserts when there are less than ALRM bytes of data in the FIFO. 28-32 MC9328MX1 Reference Manual MOTOROLA...
Page 821: Endpoint N Fifo Read Pointer Registers
The Endpoint n FIFO Write Pointer Registers hold the location of the next FIFO location to write. The number of Endpoint n FIFO Write Pointer Registers in the MC9328MX1 depends on the number of endpoints configured. MOTOROLA USB Device Port 28-33...
Page 822: Device Initialization
USB module datapath for processing. This process is performed at two different times: at reset (hard reset or software reset via RST bit in the USB_DDAR register) and when the device is first connected to the USB. 28-34 MC9328MX1 Reference Manual MOTOROLA...
Page 823: Configuration Download
UDC module. They associate “logical” endpoint numbers in the USB software stack with hardware within the UDC. Specifically, they attach each endpoint to a USB configuration, interface, and alternate setting, and they specify transfer type, packet size, data direction, and hardware FIFO numbers. MOTOROLA USB Device Port 28-35...
Page 824: Table 28-25 Endptbuf-Udc Endpoint Buffers Format
3. After writing all endpoint buffer configuration bytes, check the CFG bit of the USB_DADR to verify that the configuration download is complete. CFG changes from 1 to 0 after the last byte is loaded into the UDC. 28-36 MC9328MX1 Reference Manual MOTOROLA...
Page 825: Usb Endpoint To Fifo Mapping
USB_SPD bit, the AFE_ENA bit and the USB_ENA bit in the USB_CTRL register. NOTE: The USB_SPD bit must be set at 1 (high speed mode, default). The USB device does not support low speed. MOTOROLA USB Device Port 28-37...
Page 826: Exception Handling
USB host to clear the stall condition. The FORCE_STALL register bit automatically clears after the stall takes effect. The application software on the host must deal with the stall condition and notify the device on how to proceed. 28-38 MC9328MX1 Reference Manual MOTOROLA...
Page 827: Catastrophic Error
When using the DMA controller for a memory I/O transfer to send packets, the sequence is as follows: 1. Program the DMA controller to write data to the endpoint FIFO and enable the DMA channel for the USB endpoint DMA. MOTOROLA USB Device Port 28-39...
Page 828: Receiving Packets
FIFOs through the USB_EPn_FCTRL register for FRAME mode. Data flow is controlled with the end-of-frame and end-of-transfer interrupts, or with the DMA request lines. For isochronous endpoints, no data retries are performed. 28-40 MC9328MX1 Reference Manual MOTOROLA...
Page 829: Usb Transfers
EOT interrupt asserts. For a bulk endpoint, until the CPU has serviced the EOT interrupt, the device Negative Acknowledges (NAKs) any further requests to that endpoint from the host. This guarantees that data from two different transfers never get intermixed within the FIFO. MOTOROLA USB Device Port 28-41...
Page 830: Control Transfers
When a transfer does not complete without errors, the hardware automatically forces the FIFO to return to the start of the current packet and re-send the data. User software is expected to write data to the FIFO data 28-42 MC9328MX1 Reference Manual MOTOROLA...
Page 831: Interrupt Traffic
The EOT interrupt asserts for isochronous packet transfers when the UDC module reports that the packet data is error free. This can be used along with the EOF interrupt to determine when a transfer error of some sort occurs on an isochronous endpoint. MOTOROLA USB Device Port 28-43...
Page 832: The Synch_Frame Standard Request
FIFOs and flushes all others. When reset signaling is detected, user software must clear any pending interrupts and ensure that the module is configured properly after the reset. 28-44 MC9328MX1 Reference Manual MOTOROLA...
Page 833: Wakeup—Resume (Wake-Up) Signaling Detected
USB_EPn_FSTAT register associated with the FIFO that had the error. 28.8.2.4 FIFO_HIGH Each FIFO has an alarm register. The FIFO_HIGH interrupt asserts when the number of free bytes in the FIFO is below the level specified by the alarm register. MOTOROLA USB Device Port 28-45...
Page 834: Fifo_Low
SOF, CFG_CHG, EOT, and DEVREQ. The missed-interrupt behaviors are discussed in the following subsections. 28.8.3.1 SOF When the device misses a start-of-frame interrupt, the MSOF bit asserts in the USB_INTR register. 28-46 MC9328MX1 Reference Manual MOTOROLA...
Page 835: Cfg_Chg
USB host. Reset signaling is discussed in chapter 7 of the USB Specification. UDC Reset can invalidate data remaining in the data FIFOs. Depending on the application, software might need to flush the data FIFOs before proceeding. MOTOROLA USB Device Port 28-47...
Page 836: Usb Reset Signaling
FIFOs and execute FIFO flush operations on all of the FIFOs. This guarantees that the datapath is empty and ready for new data transfer operations when reset signaling and re-enumeration are complete. 28-48 MC9328MX1 Reference Manual MOTOROLA...
Page 837: Interface Features
• START and STOP signal generation and detection • Repeated START signal generation • Acknowledge bit generation and detection • Bus-busy detection Figure 29-1 on page 29-2 shows a block diagram of the I C module. MOTOROLA C Module 29-1...
Page 838: Figure 29-1 I 2 C Module Block Diagram
C module is designed to be compatible with The I C Bus The I Specification, Version 2.1 (Philips Semiconductor: 2000). For detailed information on system configuration, protocol, and restrictions, see the Philips I C standard. 29-2 MC9328MX1 Reference Manual MOTOROLA...
Page 839: Figure 29-2 I 2 C Standard Communication Protocol
STOP (G)—A STOP signal is sent to free the bus after data is transmitted or when the master stops • communication. A STOP signal is defined as a low-to-high transition of the SDA while the SCL is at logical high. MOTOROLA C Module 29-3...
Page 840: Clock Synchronization
As a result, the devices with the longest low periods and shortest high periods control the SCL. Devices with shorter low periods transition to high before the SCL transitions. This wait is shown in Figure 29-4. Wait Begin Counting High Period SCL1 SCL2 Internal Counter Reset Figure 29-4. Synchronized Clock SCL 29-4 MC9328MX1 Reference Manual MOTOROLA...
Page 841: Arbitration Procedure
2. Clear bit 16 of Port A General Purpose Register (GPR_A) I2C_SDA Primary function of 1. Clear bit 15 of Port A GPIO In Use Register (GIUS_A) GPIO Port A [15] 2. Clear bit 15 of Port A General Purpose Register (GPR_A) MOTOROLA C Module 29-5...
Page 842: Table 29-2 I 2 C Module Register Memory Map
C Module Register Memory Map Description Name Address IADR 0x00217000 C Address Register IFDR 0x00217004 C Frequency Divider Register I2CR 0x00217008 C Control Register I2SR 0x0021700C C Status Register I2DR 0x00217010 C Data I/O Register 29-6 MC9328MX1 Reference Manual MOTOROLA...
Page 843: Table 29-3 I 2 C Address Register Description
Slave Address—Contains the specific slave address to be used by the I C module. Slave mode is Bits 7–1 the default I C mode for an address match on the bus. Reserved Reserved—This bit is reserved and should read 0. Bit 0 MOTOROLA C Module 29-7...
Page 844: Table 29-4 Ifdr Register Description
The input clock from the PLL is HCLK. The serial bit clock for the I C module is HCLK divided by the divider shown in Table 29-5. Note: The IC value can be changed at any point. 29-8 MC9328MX1 Reference Manual MOTOROLA...
Page 845: Table 29-5 Hclk Dividers
0x39 0x0A 0x1A 1536 0x2A 0x3A 0x0B 0x1B 1920 0x2B 0x3B 1024 0x0C 0x1C 2304 0x2C 0x3C 1280 0x0D 0x1D 2560 0x2D 0x3D 1536 0x0E 0x1E 3072 0x2E 0x3E 1792 0x0F 0x1F 3840 0x2F 0x3F 2048 MOTOROLA C Module 29-9...
Page 846 C module interrupts (currently Bit 6 pending interrupt conditions are not cleared) 1 = Enable the I C module interrupts (an I interrupt occurs when the I C interrupt (IIF) bit in the I2SR Register is also set) 29-10 MC9328MX1 Reference Manual MOTOROLA...
Page 847 Bit 2 condition. This bit always reads 0. Attempting a 1 = Generates a repeated START repeated START without bus mastership causes loss of arbitration. Reserved Reserved—These bits are reserved and should read 0. Bits 1–0 MOTOROLA C Module 29-11...
Page 848: Table 29-7 I2Sr Register Description
SDA samples low when the master drives high during the acknowledge bit of a data-receive cycle • A START is attempted when the bus is busy • A repeated START is requested in slave mode • A STOP condition is detected when the master did not request it 29-12 MC9328MX1 Reference Manual MOTOROLA...
Page 849 0 = An acknowledge signal was received Bit 0 acknowledge signal (to the data) was received on SDA. after the completion of 8-bit data transmission on the bus 1 = No acknowledge signal was detected at the ninth clock MOTOROLA C Module 29-13...
Page 850: Table 29-8 I2Dr Register Description
C Programming Examples This section describes programming sequences for I C, including initialization, START signalling, post-transfer software response, STOP signalling, and repeated START generation. The flowchart in Figure 29-5 on page 29-17 illustrates an interrupt routine. 29-14 MC9328MX1 Reference Manual MOTOROLA...
Page 851: Initialization Sequence
IIF bit. When an interrupt occurs at the end of the address cycle, the master is still in transmit mode. When master receive mode is required, toggle the MTX bit in the I2CR Register. MOTOROLA C Module 29-15...
Page 852: Generation Of Stop
ARM920T processor, and sets the Arbitration Lost bit (IAL) in the I2SR Register to indicate a failed attempt to engage the bus. The slave service routine must first test the IAL bit and clear it when it is set. 29-16 MC9328MX1 Reference Manual MOTOROLA...
Page 853 Switch to Rx Mode Rx Mode Read Data Dummy Read Dummy Read Dummy Read from I2DR Generate from I2DR from I2DR from I2DR STOP Signal and Store Figure 29-5. Flow Chart of Typical I C Interrupt Routine MOTOROLA C Module 29-17...
Page 854 C Module 29-18 MC9328MX1 Reference Manual MOTOROLA...
Page 855: Ssi Architecture
MC9328MX1 to communicate with a variety of serial devices. These serial devices include standard codecs, digital signal processors (DSPs), microprocessors, peripherals that implement the Motorola Serial Peripheral Interface (SPI), and popular industry audio codecs that implement the inter-IC sound bus standard (I The SSI typically transfers samples in a periodic manner.
Page 856: Figure 30-1 Mc9328Mx1 Input/Output Block Diagram
Figure 30-2 shows a block diagram of the SSI. It consists of three control registers to configure the port, one status register, separate transmit and receive circuits with FIFO registers, and separate serial clock and frame sync generation for the transmit and receive sections. 30-2 MC9328MX1 Reference Manual MOTOROLA...
Page 857: Figure 30-2 Ssi Block Diagram
SSI Time Slot Register (STSR) TXFIFO (8x16) SSI Transmit Data Register (STX) SSI Transmit Shift SSI_TXDAT Register (TXSR) RXFIFO (8x16) SSI Receive Data Register (SRX) SSI Receive Shift SSI_RXDAT Register (RXSR) Figure 30-2. SSI Block Diagram MOTOROLA Synchronous Serial Interface (SSI) 30-3...
Page 858: Normal Operating Mode
Figure 30-4 on page 30-5 shows a block diagram of the clock generator for the transmit section. Whether the serial bit clock is generated internally or derived from an external source depends on the transmit direction ( 30-4 MC9328MX1 Reference Manual MOTOROLA...
Page 859: Pin Configuration For Ssi
SSI operation. NOTE: The user must ensure that the data direction bits in the GPIO are set to the correct direction for proper operation. See Section 32.5.1, “Data Direction Registers,” on page 32-9 for details. MOTOROLA Synchronous Serial Interface (SSI) 30-5...
Page 860 1. Clear bit 15 of Port B GPIO In Use Register (GIUS_B) of GPIO Port B [15] 2. Set bit 15 of Port B General Purpose Register (GPR_B) 3. Set bit 6 in the Function Muxing Control Register (FMCR) in the System Control Module 30-6 MC9328MX1 Reference Manual MOTOROLA...
Page 861: Table 30-1 Pin Configuration
16 bit internal FIFOs. Table 30-2 summarizes these registers and their addresses. Table 30-2. SSI Module Register Memory Map Description Name Address SSI Transmit Data Register 0x00218000 SSI Receive Data Register 0x00218004 SSI Control/Status Register SCSR 0x00218008 MOTOROLA Synchronous Serial Interface (SSI) 30-7...
Page 862: Ssi Transmit Data Register
• When the transmit FIFO is disabled and user writes data1, data2 to the STX register, data2 is discarded. NOTE: Enable the SSI (SSI_EN = 1) in the SCSR before writing to the STX register. 30-8 MC9328MX1 Reference Manual MOTOROLA...
Page 863: Ssi Transmit Fifo Register
The WL bits in the STCCR determine the number of bits that will be shifted out of the TXSR before it is considered empty and can be written to again. This word length can be 8, 10, 12, or 16 bits. MOTOROLA Synchronous Serial Interface (SSI)
Page 864: Figure 30-6 Transmit Data Path (Txbit0 = 0, Tshfd = 0)
15 14 13 12 11 10 9 SSI_TXDAT TXSR Bit 15 is shifted out first. The number of bits shifted is based on word length. Figure 30-6. Transmit Data Path (TXBIT0 = 0, TSHFD = 0) 30-10 MC9328MX1 Reference Manual MOTOROLA...
Page 865: Figure 30-7 Transmit Data Path (Txbit0 = 0, Tshfd = 1)
15 14 13 12 11 10 9 TXSR Bit 0 is shifted out first. Number of bits shifted is based on word length. Figure 30-9. Transmit Data Path (TXBIT0 = 1, TSHFD = 1) MOTOROLA Synchronous Serial Interface (SSI) 30-11...
Page 866: Ssi Receive Data Register
When the RIE bit is enabled and the Receive FIFO Full (RFF) bit in the SCSR is set, an interrupt occurs if the data level in the receive FIFO reaches the threshold value. When the receive FIFO is full, all further received data is ignored until the data is read out. 30-12 MC9328MX1 Reference Manual MOTOROLA...
Page 867: Ssi Receive Shift Register
Bit 0 (MSB) first, bit 15 (LSB) last Bit 7 (MSB) first, bit 0 (LSB) last Bit 9 (MSB) first, bit 0 (LSB) last Bit 11 (MSB) first, bit 0 (LSB) last Bit 15 (MSB) first, bit 0 (LSB) last MOTOROLA Synchronous Serial Interface (SSI) 30-13...
Page 868: Figure 30-10 Receive Data Path (Rxbit0 = 0, Rshfd = 0)
Bit 0 is shifted in first. The number of bits shifted is based on word length. Zeros are added to end of the data string for smaller words (8, 10 or 12 bits). Figure 30-12. Receive Data Path (RXBIT0 = 1, RSHFD = 0) 30-14 MC9328MX1 Reference Manual MOTOROLA...
Page 869: Ssi Control/Status Register
SCSR SSI Control/Status Register 0x00218008 TYPE RESET 0x0000 SSI_ _CLK I2S_MODE TYPE RESET 0x0041 Table 30-7. SSI Control/Status Register Description Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 MOTOROLA Synchronous Serial Interface (SSI) 30-15...
Page 870 TXSR until the TXSR register is empty, then the clock stops. When the TE bit is set again, the gated clock starts immediately and runs during any valid time slots. 30-16 MC9328MX1 Reference Manual MOTOROLA...
Page 871 ROE bit set, the Receive Data with Exception interrupt is generated. When a receive interrupt occurs with the ROE bit cleared, the Receive Data interrupt is generated. ROE is cleared by reading this register, and then reading the SRX register. MOTOROLA Synchronous Serial Interface (SSI) 30-17...
Page 872 FIFO. Note: An interrupt is generated only when both the RFF and RIE bits in the SRCR are set and the receive FIFO (the RFEN bit in the SRCR) is enabled. 30-18 MC9328MX1 Reference Manual MOTOROLA...
Page 873: Table 30-8 I2S Mode Selection
Master or save TSHFD STCR [4] Transmission direction is MSB first Master or save RSHFD SRCR [4] Receive direction is MSB first Master or save TSCKP STCR [3] Falling edge of bit clock clocks data out MOTOROLA Synchronous Serial Interface (SSI) 30-19...
Page 874: Ssi Transmit Configuration Register
As with all on-chip peripheral interrupts for the MC9328MX1, the STCR must first be set to enable maskable interrupts. Next, the AITC (ARM9 Interrupt Controller) is configured to handle the SSI interrupts. For example, the SSI interrupt bits (bits 45 through 42) in the AITC’s Interrupt Enable High 30-20 MC9328MX1 Reference Manual MOTOROLA...
Page 875: Table 30-10 Ssi Transmit Configuration Register Description
TDE bit in the SCSR is set. The TIE bit (in this register) has higher priority than the TDMA bit. When TIE is set, an interrupt is generated to the CPU instead of the DMA. MOTOROLA Synchronous Serial Interface (SSI) 30-21...
Page 876 When the word-long frame sync long is selected, this frame sync length is determined by the WL field of the 1 = Frame sync is 1 STCCR. bit-clock long 30-22 MC9328MX1 Reference Manual MOTOROLA...
Page 877: Ssi Receive Configuration Register
(either the IRQ or FIQ interrupts). When all of these steps are complete, then an interrupt is generated when any of the desired transmit status bits of the SCSR (RDR, ROE, RFS, or RFF) are set. NOTE: SSI reset does not affect the SRCR bits. Power-on-reset clears all SRCR bits. MOTOROLA Synchronous Serial Interface (SSI) 30-23...
Page 878: Table 30-12 Ssi Receive Configuration Register Description
RDR bit in the SCSR is set. The RIE bit (in this register) has higher priority than the RDMAE bit. When the RIE bit is set, an interrupt is generated to the CPU instead of the DMA. 30-24 MC9328MX1 Reference Manual MOTOROLA...
Page 879 When the word-long frame sync long is selected, this frame sync length is determined by the WL field of the 1 = Frame sync is 1 bit-clock SRCCR. long MOTOROLA Synchronous Serial Interface (SSI) 30-25...
Page 880: Table 30-13 Ssi Receive Data Interrupts
TFS in GPIO TCK in GPIO TFS out GPIO TCK out GPIO GPIO GPIO Gated Clock in GPIO GPIO GPIO Gated Clock out See Figure 30-14 on page 30-36. See Figure 30-15 on page 30-37. 30-26 MC9328MX1 Reference Manual MOTOROLA...
Page 881: Table 30-15 Ssi Transmit Clock Control Register And Ssi Receive Clock Control Register Description
See Figure 30-4. prescaler Using this prescaler allows a 128 kHz master clock to be generated for 1 = Use divide-by-eight Motorola MC1440x series codecs. prescaler MOTOROLA Synchronous Serial Interface (SSI)
Page 882: Calculating The Ssi Bit Clock From The Input Clock Value
In this case, the bit clock rate is 12 MHz ÷ (4 × 1 × 2) = 1.5 MHz. That means that the frame sync clock (SSI_TXFS) is 1.5 MHz ÷ (2 × 16) = 46.875 kHz. 30-28 MC9328MX1 Reference Manual MOTOROLA...
Page 883: Table 30-16 Ssi Bit And Frame Clock As A Function Of Psr And Pm In Normal Mode
512.0 4.096 4.173 4.173 510.64 15.96 22.05 705.6 5.644 5.647 5.647 705.88 22.06 32.00 1024.0 8.192 8.000 8.000 1000.0 31.25 44.10 1411.0 11.289 10.677 10.677 1334.63 41.71 48.00 1536.0 12.288 12.000 12.000 1500.00 48.88 MOTOROLA Synchronous Serial Interface (SSI) 30-29...
Page 884: Ssi Time Slot Register
Table 30-18. SSI Time Slot Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 DUMMY Dummy Bits—Holds data that is not intended for transmission. This register can be used during Bits 15–0 inactive time slots. 30-30 MC9328MX1 Reference Manual MOTOROLA...
Page 885: Ssi Fifo Control/Status Register
0110 = 6 data words in the transmit FIFO TXSR. 0111 = 7 data words in the transmit FIFO 1000 = 8 data words in the transmit FIFO All other settings reserved MOTOROLA Synchronous Serial Interface (SSI) 30-31...
Page 886 0111 = TFE sets when there are 7 or more empty slots in the transmit FIFO (TFCNT = 1, 0 data words) 1000 = TFE sets when there are 8 empty slots are in the transmit FIFO (TFCNT = 0 data words) All other settings reserved 30-32 MC9328MX1 Reference Manual MOTOROLA...
Page 887: Table 30-20 Value Of Transmit Fifo Empty (Tfe) And Receive Fifo Full (Rff)
Number of Data Words in TXFIFO Number of Data Words in RXFIFO Water Mark (TFWM) Receive FIFO Water Mark (RFWM) 1 (0001) 2 (0010) 3 (0011) 4 (0100) 5 (0101) 6 (0110) 7 (0111) 8 (1000) MOTOROLA Synchronous Serial Interface (SSI) 30-33...
Page 888: Ssi Option Register
Reserved—These bits are reserved and should read 0. Bits 3–1 SYNRST Frame Sync Reset—Resets the accumulation of data in the SRX register 0 = No effect Bit 0 and receive FIFO (RXFIFO) on frame synchronization. 1 = Reset data accumulation 30-34 MC9328MX1 Reference Manual MOTOROLA...
Page 889: Ssi Data And Control Pins
During gated clock mode, the SSI_TXCLK pin is used instead for clocking in data. In I S master mode, this pin is used as an output pin for the oversampling clock, SYS_CLK (PerCLK3). MOTOROLA Synchronous Serial Interface (SSI) 30-35...
Page 890: Ssi_Txfs, Serial Transmit Frame Sync
SSI_RXFS SSI TX/RX External Continuous Clock SSI TX Internal Continuous Clock, SSI RX External (RXDIR=0, TXDIR=0, RFDIR=0, TFDIR=0, SYN=0) Continuous Clock (RXDIR=0, TXDIR=1, RFDIR=0, TFDIR=1, SYN=0) Figure 30-14. Asynchronous (SYN = 0) SSI Configurations—Continuous Clock 30-36 MC9328MX1 Reference Manual MOTOROLA...
Page 891: Figure 30-15 Synchronous Ssi Configurations-Continuous And Gated Clock
The shift direction can be defined as MSB first or LSB first. Continuous SSI_TXCLK, SSI_RXCLK Gated SSI_TXCLK, SSI_RXCLK SSI_TXFS, SSI_RXFS Early SSI_TXFS, SSI_RXFS SSI_TXDAT SSI_RXDAT 8-Bit Data Bit Length Frame Sync Word Length Frame Sync Figure 30-16. Serial Clock and Frame Sync Timing MOTOROLA Synchronous Serial Interface (SSI) 30-37...
Page 892: Table 30-23 Ssi Operating Modes
In normal mode, one data word is transferred per frame. In network mode, the frame is divided into anywhere between 2 and 32 time slots, when one data word can optionally be transferred in each time slot. 30-38 MC9328MX1 Reference Manual MOTOROLA...
Page 893: Normal Mode
1. SSI enabled (SCSR:SSI_EN 2. Receiver enabled (SCSR:RE 3. Active frame sync (required for continuous clock) 4. Active bit clock (the bit clock is active when the receiver is enabled; for a gated clock, see Table 30-14) MOTOROLA Synchronous Serial Interface (SSI) 30-39...
Page 894: Figure 30-17 Normal Mode Timing-Continuous Clock
Figure 30-18 shows a similar case for a gated clock. A pull-down resistor is required in the gated clock example because the clock pin is tri-stated between transmissions. Gated CLK TX DATA SSI_TXDAT SSI_RXDAT RX DATA Figure 30-18. Normal Mode Timing—Gated Clock 30-40 MC9328MX1 Reference Manual MOTOROLA...
Page 895: Network Mode
(or the STSR) before the TXSR is finished shifting (empty) causes a transmitter underrun. This is detected by the TUE bit of the SCSR. When this happens, the SSI_TXDAT pin continuously sends the last transmitted data. MOTOROLA Synchronous Serial Interface (SSI) 30-41...
Page 896: Network Mode Receive
Figure 30-19 on page 30-43 shows the transmitter and receiver timing for an 8-bit word with continuous clock, with the FIFO disabled, and with a frame size of three words per frame sync, operating in network mode. 30-42 MC9328MX1 Reference Manual MOTOROLA...
Page 897: Gated Clock Mode
(TSCKP=1) and a rising edge transition to latch data (RSCKP=1), the clock must be in an active high state when idle. The following diagrams illustrate the different edge clocking and latching. MOTOROLA Synchronous Serial Interface (SSI) 30-43...
Page 898: External Frame And Clock Operation
The control bits in the top half of the SCSR are also unaffected. The SSI reset is useful for selective reset of the SSI without changing the present SSI control bits and without affecting the other peripherals. 30-44 MC9328MX1 Reference Manual MOTOROLA...
Page 899: Table 30-24 Ssi Control Bits Requiring Reset Before Change
[0] = TEFS / REFS SCSR [15] = SYS_CLK_EN [14:13] = I2S_MODE [12] = SYN [11] = NET NOTE: The SSI bit clock must go low for at least one complete period to ensure proper SSI reset. MOTOROLA Synchronous Serial Interface (SSI) 30-45...
Page 900 Synchronous Serial Interface (SSI) 30-46 MC9328MX1 Reference Manual MOTOROLA...
Page 901: Csi Module Architecture
MC9328MX1 to connect directly to external CMOS image sensors. The features of the CSI module include: • Configurable interface logic to support Motorola and other commonly available CMOS sensors • 8-bit data port for YCC, YUV, or Bayer-RGB data input ×...
Page 902: Figure 31-1 Csi Module Block Diagram
This DMA request signal is asserted when RxFIFO Full condition is true and is negated when RxFIFO Full condition becomes false. STATFIFO_DMAREQ This DMA request signal is asserted when STATFIFO Full condition is true and is negated when STATFIFO Full condition becomes false. 31-2 MC9328MX1 Reference Manual MOTOROLA...
Page 903: Pin Configuration For Csi
The CSI module features an integrated 32 32-bit FIFO for the image data and a 16 32-bit FIFO for statistic data. FIFO access is achieved by reading the CSI RxFIFO Register 1 and CSI Statistic FIFO Register 1. MOTOROLA CMOS Sensor Interface Module 31-3...
Page 904: Csi Interrupt Operation
Table 31-4. CSI Module Register Memory Map Description Name Address CSI Control Register 1 CSICR1 0x00224000 CSI Control Register 2 CSICR2 0x00224004 CSI Status Register 1 CSISR 0x00224008 CSI Statistic FIFO Register 1 CSISTATR 0x0022400C CSI RxFIFO Register 1 CSIRXR 0x00224010 31-4 MC9328MX1 Reference Manual MOTOROLA...
Page 905: Csi Control Register 1
When the amount of data in the RxFIFO 01 = 8 words matches the defined RxFIFO full level, a FIFO full 10 = 16 words interrupt (when enabled) and a DMA request are 11 = 24 words generated. MOTOROLA CMOS Sensor Interface Module 31-5...
Page 906 0 = No effect Bit 5 set. The RXFIFO is cleared when a 1 is written to 1 = Clear STATFIFO this bit and when FCC is reset. This bit is auto-reset after RXFIFO is clear. 31-6 MC9328MX1 Reference Manual MOTOROLA...
Page 907 Bit 1 that latches data. CSI_PIXCLK 1 = Latches data at the rising edge of CSI_PIXCLK Enable—Enables/Disables the CMOS Sensor 0 = Disable CSI module Bit 0 Interface module. 1 = Enable CSI module MOTOROLA CMOS Sensor Interface Module 31-7...
Page 908: Csi Control Register 2
(starting with green, followed by red and then for 01 = RG next line is GB the next line, the pattern is blue followed by green). 10 = BG next line is GR 11 = GB next line is RG 31-8 MC9328MX1 Reference Manual MOTOROLA...
Page 909 512 x 384 0x02 = Skip 1 pixels pixels. See Figure 31-3 on page 31-14. SCE must be 1 or HSC is ignored. 0xFF = Skip 254 pixels MOTOROLA CMOS Sensor Interface Module 31-9...
Page 910: Csi Status Register 1
Reserved—This bit is reserved and should read 0. Bit 17 SOF_INT Start Of Frame Interrupt—Enables/Disables the 0 = Disable SOF interrupt Bit 16 SOF interrupt. When set, SOF interrupt is sampled. 1 = Enable SOF interrupt Clear by writing 1. 31-10 MC9328MX1 Reference Manual MOTOROLA...
Page 911: Csi Statistic Fifo Register 1
RESET 0x0000 Table 31-8. CSI Statistic FIFO Register 1 Description Name Description STAT Statistic Data—Contains the statistic data. For more details refer to Section 31.6.4, “Packing of Bits 31–0 Statistic Data,” on page 31-15. MOTOROLA CMOS Sensor Interface Module 31-11...
Page 912: Csi Rxfifo Register 1
CSIRXR CSI RxFIFO Register 1 0x00224010 IMAGE TYPE RESET 0x0000 IMAGE TYPE RESET 0x0000 Table 31-10. CSI RxFIFO Register 1 Description Name Description IMAGE Image Data—Contains the image data from the CMOS sensor. Bits 31–0 31-12 MC9328MX1 Reference Manual MOTOROLA...
Page 913: Statistic Data Generation
256 live view, the statistic array is only 6 4 and uses a larger block size. This is due to the 3:2 ratio of the CCD vs. the 4:3 ratio of the rest of the CCDs. MOTOROLA CMOS Sensor Interface Module 31-13...
Page 914: Figure 31-3 Statistic Blocks Example For 288 X 216 Pixels Image Size
384 pixels, the SCE bit of the CSI Control Register 2 must be set to 1. The Vertical Skip Count and Horizontal Skip Count bits of the VSC and HSC bits of the CSI Control Register 2 contain the number of pixels to be skipped. 31-14 MC9328MX1 Reference Manual MOTOROLA...
Page 915: Auto Focus
When a DMA operation is used to transfer the data to the RAM, the statistic data is placed in the RAM regardless if it is big endian (set the BIG_ENDIAN bit for correct data transfer) or little endian mode (default) as follows: MOTOROLA CMOS Sensor Interface Module 31-15...
Page 916: Sensor Interface Signals
The Statistic FIFO Full (STATS_FIFO_FULL) bit indicates that the CSI Statistic FIFO Register 1 is full and that a DMA request should be initiated. 31.6.7.3 Statistic Data Request The Statistic Data Request (STATS_DATA_REQ) bit indicates a request to read the statistic data in CSI Statistic FIFO Register 1. 31-16 MC9328MX1 Reference Manual MOTOROLA...
Page 917: General Description
• Figure 32-1 on page 32-2 depicts a top-level view of the IOMUX and GPIO modules for a single port pin. This circuitry is duplicated for each of the 110 port pins. MOTOROLA GPIO Module and I/O Multiplexer (IOMUX) 32-1...
Page 918: Gpio Module Overview
Configurability of each input port pin interrupt as positive edge triggered, negative edge triggered, positive level sensitive, negative level sensitive or as a masked interrupt • Ability to logically OR each port’s 32 interrupt lines to a single interrupt to the ARM920T processor • Software reset 32-2 MC9328MX1 Reference Manual MOTOROLA...
Page 919: Interrupts
Selects whether the port pin is pulled up to a logic high. GPIO_INT Output The OR value of all 32 interrupt lines. Each pin [i] of the port corresponds to pin [i] of the ISR register. MOTOROLA GPIO Module and I/O Multiplexer (IOMUX) 32-3...
Page 920: Gpio Module Block Diagram
These signals are routed to the GPIO module via AIN[i], BIN[i], CIN[i], AOUT[i], and BOUT[i], where “i” denotes any bit from bit 31 to bit 0. There are a 32-4 MC9328MX1 Reference Manual MOTOROLA...
Page 921: Table 32-2 Pin Configuration
Set bits [2i – 32 + 1] and [2i – 32] in the Port C Output Configuration Register 2 (OCR2_C) • Write desired output value to bit [i] of the Port C Data Register (DR_C) • Set bit [i] in the Port C Data Direction Register (DDIR_C) MOTOROLA GPIO Module and I/O Multiplexer (IOMUX) 32-5...
Page 922: Table 32-3 Gpio Multiplexing Table With Ain, Bin, Cin, Aout, And Bout
– – – – SIM_ SIM_CLK SSI_TXCLK – – – – – – SIM_ ETMTRACEPKT – – – – – – ETMTRACEPKT – – – – – – ETMTRACEPKT – – – – – – 32-6 MC9328MX1 Reference Manual MOTOROLA...
Page 923: Programming Model
The base addresses for the four GPIO ports are as follows: • GPIO Port A $BA = 0x0021C000 • GPIO Port B $BA = 0x0021C100 • GPIO Port C $BA = 0x0021C200 • GPIO Port D $BA = 0x0021C300 MOTOROLA GPIO Module and I/O Multiplexer (IOMUX) 32-7...
Page 924: Table 32-4 Gpio Module Register Memory Map
Port X Software Reset Register SWR_X $BA + $03C Port X Pull_Up Enable Register PUEN_X $BA + $040 X is a variable representing A, B, C or D. The actual register names include the port. 32-8 MC9328MX1 Reference Manual MOTOROLA...
Page 925: Data Direction Registers
Table 32-5. Data Direction Registers Description Name Description Settings DDIR [i] Data Direction—Controls the direction of the pins. 0 = Pin [i] is an input Bits 31–0 1 = Pin [i] is an output MOTOROLA GPIO Module and I/O Multiplexer (IOMUX) 32-9...
Page 926: Output Configuration Registers
GPIO-Out. Each port pin [i] (i = 0 through 15) requires two OCR1 bits to External input AIN [i] determine the output signal. External input BIN [i] External input CIN [i] Data Register [i] 32-10 MC9328MX1 Reference Manual MOTOROLA...
Page 927: Output Configuration Register 2
GPIO-Out. Each port pin [i] (i = 16 through 31) External input AIN [i] requires two OCR2 bits to determine the output signal. External input BIN [i] External input CIN [i] Data Register [i] MOTOROLA GPIO Module and I/O Multiplexer (IOMUX) 32-11...
Page 928: Input Configuration Registers
[2i] one of the four options is driven to AOUT [i]. Each port pin [i] (i = 0 through GPIO-In [i] 15) requires two ICONFA1 bits to determine the input value. Interrupt Status Register [i] 32-12 MC9328MX1 Reference Manual MOTOROLA...
Page 929: Input Configuration Register A2
AOUT [i]. Each port pin [i] GPIO-In [i] (i = 16 through 31) requires two ICONFA2 bits to determine the input Interrupt Status Register [i] value. MOTOROLA GPIO Module and I/O Multiplexer (IOMUX) 32-13...
Page 930: Input Configuration Register B1
[2i] one of the four options is driven to BOUT [i]. Each port pin [i] (i = 0 through GPIO-In [i] 15) requires two ICONFB1 bits to determine the input value. Interrupt Status Register [i] 32-14 MC9328MX1 Reference Manual MOTOROLA...
Page 931: Input Configuration Register B2
BOUT [i]. Each port pin [i] (i = 16 GPIO-In [i] through 31) requires two ICONFB2 bits to determine the input value. Interrupt Status Register [i] MOTOROLA GPIO Module and I/O Multiplexer (IOMUX) 32-15...
Page 932: Data Registers
Data—Contains the GPIO output values when the Output 0 = Drives the output signal Bits 31–0 Configuration Registers select the Data Register as the output for the pin (selection 1 = Drives the output signal high 32-16 MC9328MX1 Reference Manual MOTOROLA...
Page 933: Gpio In Use Registers
GPIO function. When the pin is used for its GPIO function, function the multiplexed functions are not available. The reset value of this 1 = Pin used for GPIO register is determined by the input value of the signal function INUSE_RESET_SEL [31:0]. MOTOROLA GPIO Module and I/O Multiplexer (IOMUX) 32-17...
Page 934: Sample Status Registers
Table 32-14. Sample Status Register Description Name Description Settings SSR [i] Sample Status—Contains the value of the GPIO pin [i]. It is sampled 0 = Pin value is low Bits 31–0 on every clock. 1 = Pin value is high 32-18 MC9328MX1 Reference Manual MOTOROLA...
Page 935: Interrupt Configuration Registers
Each interrupt [i] Positive edge sensitive (i = 0 through 15) requires two ICR1 bits to determine the sensitivity. Negative edge sensitive Positive level sensitive Negative level sensitive MOTOROLA GPIO Module and I/O Multiplexer (IOMUX) 32-19...
Page 936: Interrupt Configuration Register 2
Each interrupt [i] Positive edge sensitive (i = 16 through 31) requires two ICR2 bits to determine the sensitivity. Negative edge sensitive Positive level sensitive Negative level sensitive 32-20 MC9328MX1 Reference Manual MOTOROLA...
Page 937: Interrupt Mask Registers
0x0000 Table 32-17. Interrupt Mask Register Description Name Description Settings IMR [i] Interrupt Mask—Masks the interrupts for this module. 0 = Interrupt is masked Bits 31–0 1 = Interrupt is not masked MOTOROLA GPIO Module and I/O Multiplexer (IOMUX) 32-21...
Page 938: Interrupt Status Registers
Table 32-18. Interrupt Status Register Description Name Description Settings ISR [i] Interrupt Status—Indicates whether the interrupt [i] has occurred 0 = Interrupt has not occurred Bits 31–0 for this module. Write 1 to clear. 1 = Interrupt has occurred 32-22 MC9328MX1 Reference Manual MOTOROLA...
Page 939: General Purpose Registers
When the associated bit in the GIUS register is function set, this bit has no meaning. 1 = Select alternate pin function Note: Ensure that this bit is cleared when there is no alternate function for a particular pin. MOTOROLA GPIO Module and I/O Multiplexer (IOMUX) 32-23...
Page 940: Software Reset Registers
Software Reset—Controls software reset of the port. The reset 0 = No effect Bit 0 signal is active for 3 system clock cycles and then it is released 1 = GPIO circuitry for Port X automatically. reset 32-24 MC9328MX1 Reference Manual MOTOROLA...
Page 941: Pull_Up Enable Registers
1 = Pin [i] is pulled high causes the signal to be tri-stated when it is not enabled. when not driven internally or externally PUEN_B bit 11 is pulled down when the bit is set. MOTOROLA GPIO Module and I/O Multiplexer (IOMUX) 32-25...
Page 942 GPIO Module and I/O Multiplexer (IOMUX) 32-26 MC9328MX1 Reference Manual MOTOROLA...
Page 943 15-1 writing reentrant normal interrupt routines, 10-36 interrupt control register, ALRM_HM register see ASP_ICNTLR register HOURS field, 23-8 interrupt generation, 15-3 MINUTES field, 23-8 interrupt/error status registerA, ALRM_HM register, 23-8 see SP_ISTATR register operation, 15-1 MOTOROLA MC9328MX1 Reference Manual Index-i...
Page 944 EDGE bit, 15-14 B-record examples, 9-3 PDRE bit, 15-14 changing communication speed, 9-3 PFFE bit, 15-14 entering, 9-2 PIRQE bit, 15-14 instruction buffer, 9-3 POL bit, 15-13 operation of, 9-1 ASP_ICNTLR register, 15-13 programming notes, 9-7 Index-ii MC9328MX1 Reference Manual MOTOROLA...
Page 945 STOP_READWAIT bit, 20-20 SMOD field, 13-23 STREAM_BLOCK bit, 20-21 SSIZ field, 13-23 WRITE_READ bit, 20-21 CCRx register, 13-22 CMD_DAT_CONT register, 20-20 CGPCR register SI_PROT_EN bit, 8-5 Channel x burst length register, see BLRx register 13-26 MOTOROLA MC9328MX1 Reference Manual Index-iii...
Page 946 CSI statistic FIFO register 1, see CSISTATR register XCH bit, 18-9 Core test reset, see CORE_TRST signal CSI status register 1, see CSISR register CORE_TRST signal, 6-3 CORRELATION_MAX register VALUE field, 16-59 CORRELATION_MAX register, 16-59 Index-iv MC9328MX1 Reference Manual MOTOROLA...
Page 947 DISNUM field, 10-11 CWTM bit, 25-31 DISR register, 13-9 Cyclic redundancy check okay flag, see CRCOK bit DIVISOR field, 25-41 DIVISOR register, 25-41 Divisor register, see DIVISOR register DMA buffer overflow status register, see DBOSR register MOTOROLA MC9328MX1 Reference Manual Index-v...
Page 948 DRTOSR register, 13-12 ERR INTR bit, 17-27 DSESR register ERRINTREN bit, 17-26 bits CH10 through CH0, 13-13 Estimated count register, see ESTIMATED_COUNT register DSESR register, 13-13 DTR edge triggered interrupt, 27-7 ESTIMATED_CLK_HIGH register, 16-37 ESTIMATED_CLK_LOW register, 16-36 Index-vi MC9328MX1 Reference Manual MOTOROLA...
Page 949 Four bits/pixel grayscale mode output configuration registers, 32-10 GPM field, 19-37 pin configuration, 32-4 Free-run/restart, see FRR bit programming model, 32-5 Frequency hopping registers, 16-81 pull_up enable registers, 32-25 FRR bit, 26-4 sample status registers, 32-18 MOTOROLA MC9328MX1 Reference Manual Index-vii...
Page 950: I 2 C Frequency Divider Register
RXAK bit, 29-13 STATE field, 16-85 SRW bit, 29-13 SYS bit, 16-85 I2CSR register, 29-12 Horizontal configuration register, see HCR register I2DR register HOURMIN register D field, 29-14 HOURS field, 23-5 I2DR register, 29-14 HOURMIN register, 23-5 Index-viii MC9328MX1 Reference Manual MOTOROLA...
Page 951 INTFRCH register, 10-28 IMR field, 32-21 INTFRCL register, 10-29 Initial character mode, see ICM bit INTIN field, 10-26 10-27 INT_MASK register INTREG1 register, 18-10 AUTO_CARD_DETECT bit, 20-26 INTREG2 register, 18-10 BUF_READY bit, 20-27 DAT0_EN bit, 20-26 MOTOROLA MC9328MX1 Reference Manual Index-ix...
Page 952 19-16 GRAY 1 register, 19-31 black-and-white operation, 19-7 PS_RISE_DELAY field, 19-30 color generation, 19-8 REV_TOGGLE_DELAY field, 19-30 display data mapping, 19-3 features, 19-1 frame rate modulation control, 19-10 gray scale operation, 19-7 introduction, 19-1 Index-x MC9328MX1 Reference Manual MOTOROLA...
Page 953 FIFO data register, see MSTDATA register write-error detection, 20-8 MMC/SD block length register, see BLK_LEN register Memory stick interrupt control/status register see MSICS register MMC/SD buffer access register, see BUFFER_ACCESS register MMC/SD clock control register, 20-14 MOTOROLA MC9328MX1 Reference Manual Index-xi...
Page 954 MSPPCD register NOCRC bit, 21-14 PIEN0 bit, 21-19 PWS bit, 21-14 PIEN1 bit, 21-19 RBE bit, 21-15 XPIN0 bit, 21-20 RBF bit, 21-15 XPIN1 bit, 21-20 RST bit, 21-14 MSPPCD register, 21-19 SIEN bit, 21-14 Index-xii MC9328MX1 Reference Manual MOTOROLA...
Page 955 Normal interrupt priority level registers LD bus, 19-12 description of, 10-15 passive matrix panel interface signals, 19-12 Normal interrupt vector and status register, Payload header register, see NIVECSR register see PAYLOAD_HEADER register PAYLOAD_HEADER register FLOW bit, 16-30 MOTOROLA MC9328MX1 Reference Manual Index-xiii...
Page 956 48 MHz clocks, 12-11 Port B output configuration register 1, see OCR1_B register high frequency clock source, 12-2 introduction, 12-1 Port B output configuration register 2, see OCR1_B register low frequency clock source, 12-1 Index-xiv MC9328MX1 Reference Manual MOTOROLA...
Page 957 22-3 Port D sample status register, see SSR_D register introduction, 22-1 Port D software reset register, see SWR_D register operation, 22-2 Port detect register, see PORT_DETECT register period frequency, calculating, 22-7 MOTOROLA MC9328MX1 Reference Manual Index-xv...
Page 958 RF_STATUS register READ_TO register, 20-22 BIST bit, 16-52 Receive buffer register, see RCV_BUF register BT1_CONT bit, 16-53 Receive data register full, see RDRF bit BT11_AUTO_SPIKE bit, 16-53 Receive data threshold, see RDT field BT5_OE bit, 16-53 Index-xvi MC9328MX1 Reference Manual MOTOROLA...
Page 959 IRQ readwait feature, 20-9 SAM3 bit, 23-13 IRQ service handling, 20-9 SAM4 bit, 23-13 readwait, 20-53 SAM5 bit, 23-13 suspend/resume, 20-53 SAM6 bit, 23-13 SDCTL0 register, 24-9 SAM7 bit, 23-13 SDCTL1 register, 24-9 SW bit, 23-14 MOTOROLA MC9328MX1 Reference Manual Index-xvii...
Page 960 24-19 operating modes, 24-18 SiliconWave page and bank address comparators, 24-3 THRESHOLD register, THRESHOLD field, 16-58 pin configuration, 24-7 powerdown operation in reset and low-power Clock generation, 25-2 25-4 modes, 24-33 Functional description, 25-4 Index-xviii MC9328MX1 Reference Manual MOTOROLA...
Page 961 SPI_CLKDIV3 field, 16-80 MFD field, 12-12 SPI_CLKINV bit, 16-80 MFI field, 12-13 SPI_MODE field, 16-80 MFN field, 12-13 SPI_CONTROL register, 16-79 PD field, 12-12 SPI_READ_ADDR register SPCTL0 register, 12-12 ADDRESS field, 16-79 SPCTL1 register COMMAND field, 16-79 MOTOROLA MC9328MX1 Reference Manual Index-xix...
Page 962 TIME_OUT_RESP bit, 20-18 introduction, 30-1 WR_CRC_ERROR_CODE field, 20-17 operating modes WRITE_OP_DONE bit, 20-16 gated clock mode, 30-43 STATUS register, 16-27 20-16 Status register, see STATUS register network mode, 30-41 normal mode, 30-39 STCR register, 30-21 Index-xx MC9328MX1 Reference Manual MOTOROLA...
Page 963 Transmit guard control register, TCMP1 register, 26-6 see GUARD_CNTL register TCMP2 register, 26-6 Transmit threshold error, see XTE bit TCN1 register, 26-8 Transmit threshold register, 25-35 TCN2 register, 26-8 TRST signal, 6-3 TCR1 register, 26-7 TSR_n register MOTOROLA MC9328MX1 Reference Manual Index-xxi...
Page 964 27-2 ICD field, 27-26 operation IDEN bit, 27-25 in low-power system states, 27-51 IREN bit, 27-26 pin configuration, 27-3 RDMAEN bit, 27-26 programming model, 27-19 RRDYEN bit, 27-26 receiver RTSDEN bit, 27-26 Index-xxii MC9328MX1 Reference Manual MOTOROLA...
Page 965 UCR3_2 register, 27-33 isochronous operations, 28-43 UCR4_x register module components, 28-3 BKEN bit, 27-36 pin configuration, 28-6 CTSTL field, 27-35 programmer’s reference, 28-34 DREN bit, 27-36 programming model, 28-7 ENIRI bit, 27-35 reset operation, 28-47 MOTOROLA MC9328MX1 Reference Manual Index-xxiii...
Page 966 LRFP field, 28-30 USB_EP2_STAT register, 28-19 USB_EPx_LRFP register, 28-30 USB_EP3_STAT register, 28-19 USB_EPx_LWFP register USB_EP4_STAT register, 28-19 LWFP field, 28-31 USB_EP5_STAT register, 28-19 USB_EPx_LWFP register, 28-31 USB_EPx _STAT register USB_FRAME register BYTE_COUNT field, 28-19 FRAME field, 28-8 Index-xxiv MC9328MX1 Reference Manual MOTOROLA...
Page 967 RTSS bit, 27-39 TIME field, 16-65 RXDS bit, 27-40 WAKEUP_1 register, 16-65 USR1_x register, 27-39 WAKEUP_2 register USR2_x register TIME field, 16-66 ADET bit, 27-41 WAKEUP_2 register, 16-66 BRCD bit, 27-42 WAKEUP_4 register DTRF bit, 27-41 MOTOROLA MC9328MX1 Reference Manual Index-xxv...
Page 968 X_DATA_SEL bit, 17-8 XBASE field, 17-16 X-COUNT field, 17-30 XCOUNT field, 17-19 XINCR field, 17-19 XINDEX field, 17-17 XMODIFY field, 17-18 XMT field, 25-32 XMT_BUF register, 25-32 XMT_CRC_LRC bit, 25-23 XMT_EN bit, 25-26 XMT_STATUS register, 25-27 Index-xxvi MC9328MX1 Reference Manual MOTOROLA...

Motorola DragonBall MC9328MX1 Reference Manual

Table of Contents

Chapter 1 Introduction 1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2

Chapter 9 Bootstrap Mode

Chapter 16 Bluetooth Accelerator (BTA)

Chapter 17 Multimedia Accelerator (MMA)

Chapter 3 Memory Map 3.1 Memory Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1

Chapter 4 ARM920T Processor 4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1

Chapter 5 Embedded Trace Macrocell (ETM) 5.1 Introduction to the ETM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1

Reset Module

Chapter 6 Reset Module 6.1 Functional Description of the Reset Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1

Chapter 11 External Interface Module (EIM) 11.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1

Chapter 13 DMA Controller 13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1 13.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

Chapter 14 Watchdog Timer Module

Chapter 15 Analog Signal Processor (ASP) 15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1

Chapter 18 Serial Peripheral Interface Modules (SPI 1 and SPI 2)

Chapter 29 I C Module

Chapter 22 Pulse-Width Modulator (PWM) 22.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-1

Chapter 23 Real-Time Clock (RTC) 23.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-2

Chapter 26 General-Purpose Timers

Chapter 8 System Control

Chapter 25 Smartcard Interface

Chapter 10 Interrupt Controller (AITC) 10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1

Chapter 28 USB Device Port 28.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-1 28.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-1

Chapter 2 Signal Descriptions and Pin Assignments

Chapter 30 Synchronous Serial Interface (SSI) 30.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-1

Chapter 31 CMOS Sensor Interface Module 31.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-1

Chapter 32 GPIO Module and I/O Multiplexer (IOMUX)

Quick Links

Chapters

Related Manuals for Motorola DragonBall MC9328MX1

Summary of Contents for Motorola DragonBall MC9328MX1