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Motorola DragonBall MC9328MX1 Reference Manual

Integrated portable system processor.
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DragonBall MC9328MX1 Integrated
Portable System Processor
Reference Manual
MC9328MX1RM/D
Rev. 2, 02/2003

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   Summary of Contents for Motorola DragonBall MC9328MX1

  • Page 1

    DragonBall MC9328MX1 Integrated Portable System Processor Reference Manual MC9328MX1RM/D Rev. 2, 02/2003...

  • Page 2

    Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. All other The Bluetooth product or service names are the property of their respective owners.

  • Page 3: Table Of Contents

    Power Management Features ..........1-10 MOTOROLA...

  • Page 4: Table Of Contents

    The ARM Thumb Instruction Set ......... . 4-8 MC9328MX1 Reference Manual MOTOROLA...

  • Page 5: Table Of Contents

    System Boot Mode Selection ..........8-7 MOTOROLA...

  • Page 6: Table Of Contents

    Interrupt Force Register High ........10-28 MC9328MX1 Reference Manual MOTOROLA...

  • Page 7: Table Of Contents

    11.6.1.1 Chip Select 0 Upper Control Register ......11-11 MOTOROLA Contents...

  • Page 8: Table Of Contents

    DMA Burst Time-Out Control Register ......13-15 viii MC9328MX1 Reference Manual MOTOROLA...

  • Page 9: Table Of Contents

    Current-Mode Operation..........15-4 MOTOROLA...

  • Page 10: Table Of Contents

    Payload Header Register......... 16-30 MC9328MX1 Reference Manual MOTOROLA...

  • Page 11: Table Of Contents

    Clock Control Register ......... . 16-72 MOTOROLA...

  • Page 12: Table Of Contents

    MMA MAC Bit Select Register ........17-14 MC9328MX1 Reference Manual MOTOROLA...

  • Page 13: Table Of Contents

    Soft Reset Registers ..........18-15 MOTOROLA...

  • Page 14: Table Of Contents

    Eight Bits/Pixel Active Matrix Color Mode ......19-39 19.4.17.7 Twelve Bits/Pixel and Sixteen Bits/Pixel Active Matrix Color Mode ..19-39 MC9328MX1 Reference Manual MOTOROLA...

  • Page 15: Table Of Contents

    Card Access ........... . . 20-37 20.7.3.1 Block Access—Block Write and Block Read ......20-37 MOTOROLA Contents...

  • Page 16: Table Of Contents

    Data FIFO Operation ..........21-4 MC9328MX1 Reference Manual MOTOROLA...

  • Page 17: Table Of Contents

    22.3.3 Digital-to-Analog Converter (D/A) Mode ....... 22-3 MOTOROLA Contents xvii...

  • Page 18: Table Of Contents

    MA [11:0]—Multiplexed Address Bus ....... . . 24-6 24.4.6 SDBA [4:0], SDIBA [3:0]—Non-Multiplexed Address Bus ....24-6 xviii MC9328MX1 Reference Manual MOTOROLA...

  • Page 19: Table Of Contents

    SDRAM Memory Refresh ......... . 24-65 MOTOROLA...

  • Page 20: Table Of Contents

    SmartCard Presence Detect ......... 25-15 MC9328MX1 Reference Manual MOTOROLA...

  • Page 21: Table Of Contents

    Programming Considerations ........25-52 MOTOROLA...

  • Page 22: Table Of Contents

    Baud Rate Automatic Detection Logic ....... . . 27-16 xxii MC9328MX1 Reference Manual MOTOROLA...

  • Page 23: Table Of Contents

    USB Enable Register ..........28-18 MOTOROLA...

  • Page 24: Table Of Contents

    RESET_START—Start of USB Reset Signaling..... . 28-44 28.8.1.5 WAKEUP—Resume (Wake-Up) Signaling Detected ....28-45 xxiv MC9328MX1 Reference Manual MOTOROLA...

  • Page 25: Table Of Contents

    Generation of Repeated START........29-16 MOTOROLA...

  • Page 26: Table Of Contents

    SSI Reset and Initialization Procedure ........30-44 xxvi MC9328MX1 Reference Manual MOTOROLA...

  • Page 27: Table Of Contents

    Input Configuration Register A1 ........32-12 MOTOROLA...

  • Page 28: Table Of Contents

    Pull_Up Enable Registers ......... . . 32-25 xxviii MC9328MX1 Reference Manual MOTOROLA...

  • Page 29: Table Of Contents

    MMA Data Access ..........17-2 MOTOROLA...

  • Page 30: Table Of Contents

    MSHC Module Serial Clock Divider ....... 21-11 MC9328MX1 Reference Manual MOTOROLA...

  • Page 31: Table Of Contents

    Figure 24-27 Hardware Refresh Timing Diagram ....... . 24-32 MOTOROLA...

  • Page 32: Table Of Contents

    Receive State Machine Diagram........25-11 xxxii MC9328MX1 Reference Manual MOTOROLA...

  • Page 33: Table Of Contents

    Figure 30-16 Serial Clock and Frame Sync Timing....... 30-37 MOTOROLA...

  • Page 34: Table Of Contents

    Top Level of Circuitry for Port X, Pin [i]......32-2 Figure 32-2 GPIO Module Block Diagram for Port X, Pin [i]..... . . 32-4 xxxiv MC9328MX1 Reference Manual MOTOROLA...

  • Page 35: Table Of Contents

    Silicon ID Register Description ........8-2 MOTOROLA...

  • Page 36: Table Of Contents

    Fast Interrupt Pending Register Low Description ..... 10-33 Table 10-30 Typical Hardware Accelerated Normal Interrupt Entry Sequence ..10-35 xxxvi MC9328MX1 Reference Manual MOTOROLA...

  • Page 37: Table Of Contents

    Channel Control Registers Description ......13-23 Table 13-18 DMA_EOBO_CNT and DMA_EOBI_CNT Settings ....13-24 MOTOROLA List of Tables xxxvii...

  • Page 38: Table Of Contents

    Native Count Register Description ....... . . 16-31 xxxviii MC9328MX1 Reference Manual MOTOROLA...

  • Page 39: Table Of Contents

    Table 16-55 Wake-Up Status Register Description ......16-70 MOTOROLA List of Tables...

  • Page 40: Table Of Contents

    MMA MAC Bit Select Register Description ......17-15 Table 17-12 MMA MAC X Base Address Register Description ....17-16 MC9328MX1 Reference Manual MOTOROLA...

  • Page 41: Table Of Contents

    Display Mapping in 12 bpp, CSTN Panel, Little Endian ....19-6 Table 19-4 Display Mapping in 12 bpp, CSTN Panel, Big Endian ....19-7 MOTOROLA List of Tables...

  • Page 42: Table Of Contents

    MMC/SD Revision Number Register Description ..... 20-25 Table 20-14 MMC/SD Interrupt Mask Register Description ..... . . 20-26 xlii MC9328MX1 Reference Manual MOTOROLA...

  • Page 43: Table Of Contents

    Read Packet........... 21-27 MOTOROLA...

  • Page 44: Table Of Contents

    Single 8M x 16 Control Register Values ......24-41 xliv MC9328MX1 Reference Manual MOTOROLA...

  • Page 45: Table Of Contents

    SIM Interrupts..........25-18 MOTOROLA...

  • Page 46: Table Of Contents

    Table 27-5 DTR Edge Triggered Interrupt Truth Table ......27-7 xlvi MC9328MX1 Reference Manual MOTOROLA...

  • Page 47: Table Of Contents

    Device Request Status ......... . 28-12 MOTOROLA...

  • Page 48: Table Of Contents

    Clock Pin Configuration ......... 30-26 xlviii MC9328MX1 Reference Manual MOTOROLA...

  • Page 49: Table Of Contents

    Interrupt Mask Register Description....... . 32-21 MOTOROLA List of Tables...

  • Page 50

    Pull_Up Enable Register Description ....... 32-25 MC9328MX1 Reference Manual MOTOROLA...

  • Page 51: About This Book

    ID register, and I/O drive control registers. Bootstrap Mode Operation: The operation of bootstrap models is described in Chapter 9 detail in this chapter. This chapter describes programming information necessary MOTOROLA About This Book...

  • Page 52

    MMC, its operation and programming information. Memory Stick Host Controller (MSHC): This chapter describes how data is Chapter 21 transferred to a Memory Stick device. It also discusses how to configure and program the Memory Stick Host Controller. MC9328MX1 Reference Manual MOTOROLA...

  • Page 53

    GPIO and I/O Multiplexer (IOMUX): This chapter covers all GPIO lines Chapter 32 found in the MC9328MX1. Because each pin is individually configurable, a detailed description of the operation is provided. MOTOROLA About This Book liii...

  • Page 54: Document Revision History

    MC68SZ328 Product Brief (order number MC68SZ328P/D) MC68SZ328 User’s Manual (order number MC68SZ328UM/D) The manuals may be found at the Motorola Semiconductors World Wide Web site at http://www.motorola.com/semiconductors. These documents may be downloaded directly from the World Wide Web site, or printed versions may be ordered. The World Wide Web site also may have useful application notes.

  • Page 55

    DRAM dynamic random access memory digital signal processor EDO RAM extended data out DRAM forward error correction FIFO first in first out GPIO general purpose input/output inquiry access code: A predefined Bluetooth ID input/output in-circuit emulation MOTOROLA About This Book...

  • Page 56

    SDRAM synchronous dynamic random access memory serial peripheral interface SRAM static random access memory TQFP thin quad flat pack UART universal asynchronous receiver/transmitter universal serial bus XTAL crystal MC9328MX1 Reference Manual MOTOROLA...

  • Page 57: Block Diagram

    Chapter 1 Introduction Motorola’s DragonBall family of microprocessors has demonstrated leadership in the portable handheld market. Continuing this legacy, the DragonBall MX (Media Extensions) series provides a leap in performance with an ARM9™ microprocessor core and highly integrated system functions. DragonBall MX products specifically address the requirements of the personal, portable product market by providing intelligent integrated peripherals, an advanced processor core, and power management capabilities.

  • Page 58: Features, Figure 1-1 Mc9328mx1 Functional Block Diagram

    Two General-Purpose 32-bit Counters/Timers • Watchdog Timer • Real-Time Clock/Sampling Timer (RTC) • LCD Controller (LCDC) • Pulse-Width Modulation (PWM) Module • Universal Serial Bus (USB) Device • Multimedia Card and Secure Digital (MMC/SD) Host Controller MC9328MX1 Reference Manual MOTOROLA...

  • Page 59: Arm920t Microprocessor Core, Ahb To Ip Bus Interfaces (aipis)

    Cache locking to support mixed loads of real-time and user applications • Virtual Memory Management Unit (VMMU) 1.4 AHB to IP Bus Interfaces (AIPIs) The MC9328MX1 AIPIs provide a communication interface between the high-speed AHB bus and a lower-speed IP bus for slow slave peripherals. MOTOROLA Introduction...

  • Page 60: External Interface Module (eim), Sdram Controller (sdramc), Clock Generation Module (cgm) And Power Control Module

    • Auto-powerdown (clock suspend) timer 1.7 Clock Generation Module (CGM) and Power Control Module The MC9328MX1 CGM and Power Control Module features: • Digital phase-locked loops (PLLs) and clock controller for all internal clocks generation MC9328MX1 Reference Manual MOTOROLA...

  • Page 61: Two Serial Peripheral Interfaces (spi), Two General-purpose 32-bit Counters/timers, Watchdog Timer

    Programmable timer input/output pins • Input capture capability with programmable trigger edge • Output compare with programmable mode 1.11 Watchdog Timer The MC9328MX1 Watchdog Timer features: • Programmable time out of 0.5 s to 64 s • Resolution of 0.5 s MOTOROLA Introduction...

  • Page 62: Real-time Clock/sampling Timer (rtc), Lcd Controller (lcdc), Pulse-width Modulation (pwm) Module

    In BW mode, the maximum bit depth is 4 bpp • Up to 16 grey levels out of 16 palettes • Capable of directly driving popular LCD drivers from manufacturers including Motorola, Sharp, Hitachi, and Toshiba • Support for data bus width for 12- or 16-bit TFT panels •...

  • Page 63: Universal Serial Bus (usb) Device, Multimedia Card And Secure Digital (mmc/sd) Host Controller

    Up to ten MMC cards and one SD are supported by standard (maximum data rate with a maximum of ten cards) • Support for hot swappable operation • Support for data rates from 20 Mbps to 80 Mbps MOTOROLA Introduction...

  • Page 64: Memory Stick® Host Controller (mshc), Smartcard Interface Module (sim), Direct Memory Access Controller (dmac)

    Bulk data transfer complete or transfer error interrupts provided to interrupt handler (and then to the core) • DMA burst time-out error terminates the DMA cycle when the burst cannot be completed within a programmed timing period • Acknowledge signal provided to peripheral after DMA burst is complete MC9328MX1 Reference Manual MOTOROLA...

  • Page 65: Synchronous Serial Interface And Inter-ic Sound (ssi/i 2 S) Module, Video Port

    Allows user to initialize system and download program or data to system memory through UART • Accepts execution command to run program stored in system memory • Supports memory/register read/write operation of selectable data size of byte, half-word, or word MOTOROLA Introduction...

  • Page 66: Analog Signal Processing (asp) Module, Bluetooth Accelerator (bta), Multimedia Accelerator (mma), Power Management Features

    • 32-word (16-bit) Rx and Tx buffer Programmable RF controller supports three front ends (including SPI / µWire controller) • • Support for external transceiver ICs from manufacturers such as Motorola (MC13180) and Silicon Wave™ • Bluetooth application timer •...

  • Page 67: Operating Voltage Range, Packaging

    1.30 Packaging The MC9328MX1 features two packages: • 256-pin MAPBGA package with 14 mm × 14 mm × 1.3 mm, 0.8 mm ball pitch • 225-pin PBGA package with 13 mm × 13 mm, 0.8 mm ball pitch MOTOROLA Introduction 1-11...

  • Page 68

    Introduction 1-12 MC9328MX1 Reference Manual MOTOROLA...

  • Page 69: Signal Descriptions, Table 2-1 Mc9328mx1 Signal Descriptions

    Clock signal sent to external synchronous memories (such as burst flash) during burst mode. RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input signal by external DRAM. MOTOROLA Signal Descriptions and Pin Assignments...

  • Page 70

    Clocks and Resets EXTAL16M Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when internal oscillator circuit is shut down. XTAL16M Crystal output EXTAL32K 32 kHz crystal input XTAL32K 32 kHz crystal output MC9328MX1 Reference Manual MOTOROLA...

  • Page 71

    ETM packet signals which are multiplex with ECB, LBA, BCLK, PA17, A [19:16]. ETMTRACEPKT [7:0] are selected in ETM mode. CMOS Sensor Interface CSI_D [7:0] Sensor port data CSI_MCLK Sensor port master clock CSI_VSYNC Sensor port vertical sync MOTOROLA Signal Descriptions and Pin Assignments...

  • Page 72

    SIM_RX Receive Data SIM_TX Transmit Data SIM_PD Presence Detect Schmitt trigger input SIM_SVEN SIM Vdd Enable SPI1_MOSI Master Out/Slave In SPI1_MISO Slave In/Master Out SPI1_SS Slave Select (Selectable polarity) SPI1_SCLK Serial Clock SPI1_SPI_RDY Serial Data Ready MC9328MX1 Reference Manual MOTOROLA...

  • Page 73

    SD_CMD SD Command—If the system designer does not want to make use of the internal pull-up, via the Pull-up enable register, a 4.7K–69K external pull up resistor must be added. SD_CLK MMC Output Clock MOTOROLA Signal Descriptions and Pin Assignments...

  • Page 74

    Ring Indicator UART2_DCD Data Carrier Detect UART2_DTR Data Terminal Ready Serial Audio Port – SSI (configurable to I2S protocol) SSI_TXDAT SSI_RXDAT SSI_TXCLK Transmit Serial Clock SSI_RXCLK Receive Serial Clock SSI_TXFS Transmit Frame Sync SSI_RXFS Receive Frame Sync MC9328MX1 Reference Manual MOTOROLA...

  • Page 75

    Negative resistance input (a) Negative resistance input (b) Positive reference for pen ADC Negative reference for pen ADC AVDD Analog power supply AGND Analog ground BlueTooth I/O clock signal Output Input Input Output Output Output MOTOROLA Signal Descriptions and Pin Assignments...

  • Page 76: I/o Pads Power Supply And Signal Multiplexing Scheme

    (memory and external peripherals). The function multiplexing information also shown in Table 2-2 allows the user to select the function of each pin by configuring the appropriate GPIO registers when those pins are multiplexed to provide different functions. MC9328MX1 Reference Manual MOTOROLA...

  • Page 77: Table 2-2 Mc9328mx1 Signal Multiplexing Scheme

    ETMPIPESTAT0 PA28 NVDD1 NVDD1 ETMTRACEPKT3 PA27 NVDD1 Static NVDD1 NVDD1 Static NVDD1 ETMTRACEPKT2 PA26 NVDD1 NVDD1 ETMTRACEPKT1 PA25 NVDD1 NVDD1 ETMTRACEPKT0 PA24 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 Static QVDD1 QVDD1 Static Static MOTOROLA Signal Descriptions and Pin Assignments...

  • Page 78

    NVDD1 Static NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 Static NVDD1 NVDD1 Static NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 Static NVDD1 NVDD1 Static NVDD1 2-10 MC9328MX1 Reference Manual MOTOROLA...

  • Page 79

    SDCLK NVDD1 NVDD1 NVDD1 NVDD1 ETMTRACEPKT7 PA20 NVDD1 NVDD1 ETMTRACEPKT6 PA19 NVDD1 NVDD1 BCLK ETMTRACEPKT5 PA18 BCLK NVDD1 Static NVDD1 NVDD1 Static NVDD1 PA17 ETMTRACEPKT4 PA17 PA17 NVDD1 NVDD1 NVDD1 MA11 NVDD1 MA10 MOTOROLA Signal Descriptions and Pin Assignments 2-11...

  • Page 80

    NVDD1 RESET_SF NVDD1 CLKO Static AVDD1 AVDD1 Static AVDD1 RESET_IN AVDD1 RESET_OUT AVDD1 AVDD1 BIG_ENDIAN AVDD1 BOOT3 AVDD1 BOOT2 AVDD1 BOOT1 AVDD1 BOOT0 AVDD1 TRISTATE AVDD1 TRST QVDD2 QVDD2 Static Static AVDD1 EXTAL16M AVDD1 XTAL16M 2-12 MC9328MX1 Reference Manual MOTOROLA...

  • Page 81

    CSI_D2 NVDD2 CSI_D1 NVDD2 CSI_D0 NVDD2 CSI_MCLK NVDD2 PWMO NVDD2 NVDD2 TMR2OUT PD31 PD31 NVDD2 LD15 PD30 PD30 NVDD2 LD14 PD29 PD29 NVDD2 LD13 PD28 PD28 NVDD2 LD12 PD27 PD27 QVDD3 QVDD3 Static MOTOROLA Signal Descriptions and Pin Assignments 2-13...

  • Page 82

    FLM/VSYNC PD14 PD14 NVDD2 LP/HSYNC PD13 PD13 NVDD2 ACD/OE PD12 PD12 NVDD2 CONTRAST PD11 PD11 NVDD2 SPL_SPR UART2_DSR PD10 PD10 NVDD2 UART2_RI NVDD2 UART2_DCD NVDD2 UART2_DTR NVDD2 LSCLK Static AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 2-14 MC9328MX1 Reference Manual MOTOROLA...

  • Page 83

    PC31 BTRFVDD PC30 PC30 BTRFVDD PC29 PC29 BTRFVDD PC28 PC28 BTRFVDD PC27 PC27 BTRFVDD PC26 PC26 BTRFVDD PC25 PC25 BTRFVDD PC24 PC24 BTRFVDD PC23 PC23 BTRFVDD BT10 PC22 PC22 BTRFVDD BT11 PC21 PC21 MOTOROLA Signal Descriptions and Pin Assignments 2-15...

  • Page 84

    UART2_TXD PB30 PB30 NVDD4 UART2_RTS PB29 PB29 NVDD4 UART2_CTS PB28 PB28 NVDD4 USBD_VMO PB27 PB27 NVDD4 USBD_VPO PB26 PB26 NVDD4 USBD_VM PB25 PB25 NVDD4 USBD_VP PB24 PB24 NVDD4 USBD_SUSPND PB23 PB23 NVDD4 USBD_RCV PB22 PB22 2-16 MC9328MX1 Reference Manual MOTOROLA...

  • Page 85

    NVDD4 SIM_SVEN SSI_RXFS PB14 PB14 NVDD4 SD_CMD MS_BS PB13 PB13 NVDD4 SD_SCLK MS_SCLKO PB12 PB12 NVDD4 SD_DAT3 MS_SDIO PB11 PB11 (pull down) NVDD4 SD_DAT2 MS_SCLKI PB10 PB10 NVDD4 SD_DAT1 MS_PI1 NVDD4 SD_DAT0 MP_PI0 MOTOROLA Signal Descriptions and Pin Assignments 2-17...

  • Page 86

    Signal Descriptions and Pin Assignments 2-18 MC9328MX1 Reference Manual MOTOROLA...

  • Page 87: Memory Space, Memory Map

    Figure 3-1 on page 3-2. 3.1.1 Memory Map The base address referred to in each peripheral register address is the address from this table. The exact address description of each of the peripherals is described in each peripheral section. MOTOROLA Memory Map...

  • Page 88: Figure 3-1 Mc9328mx1 Mcu Physical Memory Map (4 Gbyte)

    16 MB $0021 E000 $5000 1000 $1600 0000 1020 KB 4 KB Reserved $0021 EFFF Reserved (Spare) $0021 F000 Reserved active low $0021 FFFF $FFFF FFFF $16FF FFFF Figure 3-1. MC9328MX1 MCU Physical Memory Map (4 Gbyte) MC9328MX1 Reference Manual MOTOROLA...

  • Page 89: Table 3-1 Mcu Memory Space (physical Addresses)

    $0021 6000 - $0021 6FFF 4 kbyte $0021 7000 - $0021 7FFF 4 kbyte $0021 8000 - $0021 8FFF 4 kbyte $0021 9000 - $0021 9FFF SPI 2 4 kbyte $0021 A000 - $0021 AFFF MSHC 4 kbyte MOTOROLA Memory Map...

  • Page 90

    $1600 0000 - $16FF FFFF External Memory (CS5) 16 Mbyte $1700 0000 - $4FFF FFFF Reserved 912 Mbyte $5000 0000 - $5000 0FFF ARM920T Test Registers 4 kbyte $5000 1000 - $FFFF FFFF Reserved 2815 Mbyte + 1020 kbyte MC9328MX1 Reference Manual MOTOROLA...

  • Page 91: On-chip Mcu Memory, Internal Register Space, External Memory, Double Map Image

    SyncFlash, CS0, or Bootstrap ROM. After system power up, reading or writing to the double map space ($0000,0000 to $000F,FFFF) is the same as reading or writing to the first 1 Mbyte of the selected boot ROM which is controlled by the configuration of BOOT [3:0] input pins. MOTOROLA Memory Map...

  • Page 92: Internal Registers, Table 3-2 Mc9328mx1 Internal Registers Sorted By Address

    SECONDS RTC Seconds Counter Register 0x00204008 ALRM_HM RTC Hours and Minutes Alarm Register 0x0020400C ALRM_SEC RTC Seconds Alarm Register 0x00204010 RCCTL RTC Control Register 0x00204014 RTCISR RTC Interrupt Status Register 0x00204018 RTCIENR RTC Interrupt Enable Register MC9328MX1 Reference Manual MOTOROLA...

  • Page 93

    URX5D_1 UART1 Receiver Register 5 UART 1 0x00206018 URX6D_1 UART1 Receiver Register 6 UART 1 0x0020601C URX7D_1 UART1 Receiver Register 7 UART 1 0x00206020 URX8D_1 UART1 Receiver Register 8 UART 1 0x00206024 URX9D_1 UART1 Receiver Register 9 MOTOROLA Memory Map...

  • Page 94

    UART1 Control Register 3 UART 1 0x0020608C UCR4_1 UART1 Control Register 4 UART 1 0x00206090 UFCR_1 UART1 FIFO Control Register UART 1 0x00206094 USR1_1 UART1 Status Register 1 UART 1 0x00206098 USR2_1 UART1 Status Register 2 MC9328MX1 Reference Manual MOTOROLA...

  • Page 95

    URX10D_2 UART2 Receiver Register 10 UART 2 0x0020702C URX11D_2 UART2 Receiver Register 11 UART 2 0x00207030 URX12D_2 UART2 Receiver Register 12 UART 2 0x00207034 URX13D_2 UART2 Receiver Register 13 UART 2 0x00207038 URX14D_2 UART2 Receiver Register 14 MOTOROLA Memory Map...

  • Page 96

    UART2 Escape Character Register UART 2 0x002070A0 UTIM_2 UART2 Escape Timer Register UART 2 0x002070A4 UBIR_2 UART2 BRM Incremental Register UART 2 0x002070A8 UBMR_2 UART2 BRM Modulator Register UART 2 0x002070AC UBRC_2 UART2 Baud Rate Count Register 3-10 MC9328MX1 Reference Manual MOTOROLA...

  • Page 97

    Y-Size Register A DMAC 0x0020904C WSRB W-Size Register B DMAC 0x00209050 XSRB X-Size Register B DMAC 0x00209054 YSRB Y-Size Register B DMAC 0x00209080 SAR0 Channel 0 Source Address Register DMAC 0x00209084 DAR0 Channel 0 Destination Address Register MOTOROLA Memory Map 3-11...

  • Page 98

    Channel 3 Request Source Select Register DMAC 0x00209154 BLR3 Channel 3 Burst Length Register DMAC 0x00209158 RTOR3 Channel 3 Request Time-Out Register BUCR3 Channel 3 Bus Utilization Control Register DMAC 0x00209180 SAR4 Channel 4 Source Address Register 3-12 MC9328MX1 Reference Manual MOTOROLA...

  • Page 99

    Channel 7 Control Register DMAC 0x00209250 RSSR7 Channel 7 Request Source Select Register DMAC 0x00209254 BLR7 Channel 7 Burst Length Register DMAC 0x00209258 RTOR7 Channel 7 Request Time-Out Register BUCR7 Channel 7 Bus Utilization Control Register MOTOROLA Memory Map 3-13...

  • Page 100

    PSR1_2 AIPI2 Peripheral Size Register 1 AIPI2 0x00210008 PAR_2 AIPI2 Peripheral Access Register AIPI2 0x0021000C PCR_2 AIPI2 Peripheral Control Register AIPI2 0x00210010 TSR_2 AIPI2Time-Out Status Register 0x00211000 PORT_CNTL Port Control Register 0x00211004 CNTL Control Register 3-14 MC9328MX1 Reference Manual MOTOROLA...

  • Page 101

    0x00212024 USB_ENAB USB Enable Register USBD 0x00212030 USB_EP0_STAT Endpoint 0 Status/Control Register USBD 0x00212034 USB_EP0_INTR Endpoint 0 Interrupt Status Register USBD 0x00212038 USB_EP0_MASK Endpoint 0 Interrupt Mask Register USBD 0x0021203C USB_EP0_FDAT Endpoint 0 FIFO Data Register MOTOROLA Memory Map 3-15...

  • Page 102

    0x002120AC USB_EP2_LWFP Endpoint 2 Last Write Frame Pointer Register USBD 0x002120B0 USB_EP2_FALRM Endpoint 2 FIFO Alarm Register USBD 0x002120B4 USB_EP2_FRDP Endpoint 2 FIFO Read Pointer Register USBD 0x002120B8 USB_EP2_FWRP Endpoint 2 FIFO Write Pointer Register 3-16 MC9328MX1 Reference Manual MOTOROLA...

  • Page 103

    Endpoint 5 Interrupt Mask Register USBD 0x0021212C USB_EP5_FDAT Endpoint 5 FIFO Data Register USBD 0x00212130 USB_EP5_FSTAT Endpoint 5 FIFO Status Register USBD 0x00212134 USB_EP5_FCTRL Endpoint 5 FIFO Control Register USBD 0x00212138 USB_EP5_LRFP Endpoint 5 Last Read Frame Pointer Register MOTOROLA Memory Map 3-17...

  • Page 104

    MMC/SD Higher Argument Register MMC/SDHC 0x00214030 ARGL MMC/SD Lower Argument Register MMC/SDHC 0x00214034 RES_FIFO MMC/SD Response FIFO Register MMC/SDHC 0x00214038 BUFFER_ACCESS MMC/SD Buffer Access Register 0x00215000 ASP_PADFIFO Pen Sample FIFO 0x00215004 ASP_VADFIFO Voice ADC Register 3-18 MC9328MX1 Reference Manual MOTOROLA...

  • Page 105

    Offset Clock High Register 0x00216030 HECCRC_CONTROL HECCRC Control Register 0x00216034 WHITE_CONTROL White Control Register 0x00216038 ENCRYPTION_CONTROL_X13 Encryption Control X13 Register 0x00216040 CORRELATION_TIME_SETUP Correlation Time Setup Register CORRELATION_TIME_STAMP Correlation Time Stamp Register 0x00216048 RF_GPO RF GPO Register MOTOROLA Memory Map 3-19...

  • Page 106

    Buf Word 10 (LW0) Register 0x002160AC BUF_WORD_11 (LW0) Buf Word 11 (LW0) Register 0x002160B0 BUF_WORD_12 (LW0) Buf Word 12 (LW0) Register 0x002160B4 BUF_WORD_13 (LW0) Buf Word 13 (LW0) Register 0x002160B8 BUF_WORD_14 (LW0) Buf Word 14 (LW0) Register 3-20 MC9328MX1 Reference Manual MOTOROLA...

  • Page 107

    0x00216114 WU_COUNT WakeUp Count Register 0x00216118 CLK_CONTROL Clock Control Register 0x00216120 SPI_WORD0 SPI Word0 Register 0x00216124 SPI_WORD1 SPI Word1 Register 0x00216128 SPI_WORD2 SPI Word2 Register 0x0021612C SPI_WORD3 SPI Word3 Register 0x00216130 SPI_WRITE_ADDR SPI Write Address Register MOTOROLA Memory Map 3-21...

  • Page 108

    SSI Transmit Clock Control Register 0x00218018 SRCCR SSI Receive Clock Control Register 0x0021801C STSR SSI Time Slot Register 0x00218020 SFCSR SSI FIFO Control/Status Register 0x00218028 SSI Option Register SPI 2 0x00219000 RXDATAREG2 SPI 2 Rx Data Register 3-22 MC9328MX1 Reference Manual MOTOROLA...

  • Page 109

    System PLL Control Register 1 PLLCLK 0x0021B020 PCDR Peripheral Clock Divider Register RESET 0x0021B800 Reset Source Register SYS CTRL 0x0021B804 SIDR Silicon ID Register SYS CTRL 0x0021B808 FMCR Function Multiplexing Control Register SYS CTRL 0x0021B80C GPCR Global Peripheral Control Register MOTOROLA Memory Map 3-23...

  • Page 110

    Port B GPIO In Use Register GPIO B 0x0021C124 SSR_B Port B Sample Status Register GPIO B 0x0021C128 ICR1_B Port B Interrupt Configuration Register 1 GPIO B 0x0021C12C ICR2_B Port B Interrupt Configuration Register 2 3-24 MC9328MX1 Reference Manual MOTOROLA...

  • Page 111

    Port D Input Configuration Register A1 GPIO D 0x0021C310 ICONFA2_D Port D Input Configuration Register A2 GPIO D 0x0021C314 ICONFB1_D Port D Input Configuration Register B1 GPIO D 0x0021C318 ICONFB2_D Port D Input Configuration Register B2 MOTOROLA Memory Map 3-25...

  • Page 112

    SDCTL0 SDRAM 0 Control Register SDRAMC 0x00221004 SDCTL1 SDRAM 1 Control Register SDRAMC 0x00221014 MISCELLANEOUS Miscellaneous Register SDRAMC 0x00221018 SDRST SDRAM Reset Register 0x00222000 MMA_MAC_MOD MMA MAC Module Register 0x00222004 MMA_MAC_CTRL MMA MAC Control Register 3-26 MC9328MX1 Reference Manual MOTOROLA...

  • Page 113

    DCT/iDCT IRQ Enable Register 0x0022240C MMA_DCTIRQSTAT DCT/iDCT IRQ Status Register 0x00222410 DSA_DCTSRCDATA DCT/iDCT Source Data Address 0x00222414 MMA_DCTDESDATA DCT/iDCT Destination Data Address 0x00222418 MMA_DCTXOFF DCT/iDCT X-Offset Address 0x0022241C MMA_DCTYOFF DCT/iDCT Y-Offset Address 0x00222420 MMA_DCTXYCNT DCT/iDCT XY Count MOTOROLA Memory Map 3-27...

  • Page 114

    Interrupt Force Register Low AITC 0x00223058 NIPNDH Normal Interrupt Pending Register High AITC 0x0022305C NIPNDL Normal Interrupt Pending Register Low AITC 0x00223060 FIPNDH Fast Interrupt Pending Register High AITC 0x00223064 FIPNDL Fast Interrupt Pending Register Low 3-28 MC9328MX1 Reference Manual MOTOROLA...

  • Page 115

    Module Name Address Name Description 0x00224000 CSICR1 CSI Control Register 1 0x00224004 CSICR2 CSI Control Register 2 0x00224008 CSISR CSI Status Register 1 0x0022400C CSISTATR CSI Statistic FIFO Register 1 0x00224010 CSIRXR CSI RxFIFO Register 1 MOTOROLA Memory Map 3-29...

  • Page 116

    Memory Map 3-30 MC9328MX1 Reference Manual MOTOROLA...

  • Page 117: Introduction

    ARM920T processor is 100% user code binary compatible with ARM7TDMI , and backwards ® compatible with the ARM7™ Thumb® Family and the StrongARM processor families, giving designers software-compatible processors with a range of price/performance points from 60 MIPS to 200+ MIPS. MOTOROLA ARM920T Processor...

  • Page 118: Arm920t Macrocell, Caches, Figure 4-1 Arm920t Core Functional Block Diagram

    A 32-bit data bus connects each cache to the ARM9TDMI core allowing a 32-bit instruction to be fetched and fed into the instruction Decode stage of the pipeline at the same time as a 32-bit data access for the Memory stage of the pipeline. MC9328MX1 Reference Manual MOTOROLA...

  • Page 119: Cache Lock-down, Write Buffer, Patag Ram, Mmus, System Controller

    The physical address of all the lines held in the data cache is stored by the PATAG memory, removing the need for address translation when evicting a line from the cache. MOTOROLA ARM920T Processor...

  • Page 120: Control Coprocessor (cp15), Armv4t Architecture, Registers, Modes And Exception Handling, Status Registers

    All other processor states are held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds: • Four ALU flags (Negative, Zero, Carry, and Overflow) • Two interrupt disable bits (one for each type of interrupt) MC9328MX1 Reference Manual MOTOROLA...

  • Page 121: Exception Types, Conditional Execution, Four Classes Of Instructions, Data Processing Instructions

    Four types of shift can be specified. Most data processing instructions can perform a shift followed by a logical or arithmetic operation. Multiply instructions come in two classes: • Normal, 32-bit result • Long, 32-bit result variants. Both types of multiply instruction can optionally perform an accumulate operation. MOTOROLA ARM920T Processor...

  • Page 122: Load And Store Instructions, Addressing Modes, Block Transfers, Branch Instructions, Branch With Link

    There is a Branch with Link (BL) that allows efficient subroutine calls. BL preserves the address of the instruction after the branch in R14 (the Link Register, or LR). This allows a move instruction to put the LR in to the PC and return to the instruction after the branch. MC9328MX1 Reference Manual MOTOROLA...

  • Page 123: Coprocessor Instructions, The Arm9 Instruction Set, Table 4-1 Arm920t Instruction Set

    Accumulate UMULL Unsigned Long Multiply UMLAL Unsigned Long Multiply Accumulate Count Leading Zeroes BKPT Breakpoint Move From Status Register Move to Status Register Branch Branch and Link Branch and Link and Exchange Branch and Exchange Software Interrupt MOTOROLA ARM920T Processor...

  • Page 124: The Arm Thumb Instruction Set, Table 4-2 Arm Thumb Instruction Set

    Logical Exclusive OR Logical (inclusive) OR Logical Shift Left Logical Shift Right Arithmetic Shift Right Rotate Right Multiply BKPT Breakpoint Unconditional Branch Conditional Branch Branch and Link Branch and Link and Exchange Branch and Exchange Software Interrupt MC9328MX1 Reference Manual MOTOROLA...

  • Page 125: Arm920t Modes And Registers, Table 4-3 Register Availability By Mode

    Interrupt Mode System Modes Mode Mode Mode R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ CPSR CPSR CPSR CPSR CPSR CPSR SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ = Mode-specific banked registers MOTOROLA ARM920T Processor...

  • Page 126

    ARM920T Processor 4-10 MC9328MX1 Reference Manual MOTOROLA...

  • Page 127: Introduction To The Etm, Figure 5-1 Etm Block Diagram

    ARM7™ processor and ETM7, refer to the ETM7 Technical Reference Manual Rev.1 (ARM Limited: 2001, order number DDI0158D). The block diagram of the ETM is shown in Figure 5-1. Figure 5-1. ETM Block Diagram MOTOROLA Embedded Trace Macrocell (ETM)

  • Page 128: Programming And Reading Etm Registers, Pin Configuration For Etm, Table 5-1 Etm Pin Configuration

    2. Set bits [20:17] of Port A General Purpose Register (GPR_A) ETMTRACEPKT Alternate function of 1. Clear bits [27:24] of Port A GPIO In Use Register (GIUS_A) [3:0] GPIO Port A [27:24] 2. Set bits [27:24] of Port A General Purpose Register (GPR_A) MC9328MX1 Reference Manual MOTOROLA...

  • Page 129: Functional Description Of The Reset Module, Global Reset, Figure 6-1 Reset Module Block Diagram

    See Table 6-1 for reset module signal and pin definitions. There is one source capable of generating a global reset: A high condition on the POR pin for at least × 32 kHz clocks when the 32 kHz crystal oscillator is running. MOTOROLA Reset Module...

  • Page 130: Arm920t Processor Reset, Figure 6-2 Dram And Internal Reset Timing Diagram

    ROM, sync flash, or CS0 space. The memory location of the fetch depends on the configuration of the BOOT pins and the value of the TEST pin on the rising edge of HRESET (see Section 8.2, “System Boot Mode Selection,” on page 8-7). MC9328MX1 Reference Manual MOTOROLA...

  • Page 131: Programming Model, Reset Source Register (rsr), Table 6-1 Reset Module Pin And Signal Descriptions

    RESET_OUT signal), only the highest-priority event is registered by the RSR using the following priority order: 1. POR signal 2. Qualified external reset signal 3. Watchdog signal Otherwise, the last signal that is released is honored. MOTOROLA Reset Module...

  • Page 132: Table 6-2 Rsr Register Description, Table 6-3 Hardware Reset Source Matrix

    0 = Reset was NOT a RESET_IN pin assertion Bit 0 reset was caused by a RESET_IN pin 1 = Reset WAS a RESET_IN pin assertion assertion. Table 6-3. Hardware Reset Source Matrix Source Qualified external reset Watchdog time-out MC9328MX1 Reference Manual MOTOROLA...

  • Page 133: Overview, Features, General Information

    IP bus peripherals. The AIPI captures read data (qualified by IPS_XFR_WAIT) from the IP bus interface and drives it on the R-AHB. The AIPI module terminates the transfer by asserting AIPI_HREADY_OUT. MOTOROLA AHB to IP Bus Interface (AIPI)

  • Page 134: Figure 7-1 Aipi Interface

    AHB for the write operation. haddr[16:0] HWDATA[31:0] IPS_WDATA[31:0] HWDATA[31:0] IPS_RDATA[15:1][31: AIPI_HRDATA[31:0] IPS_MODULE_EN[15: HPROTL IPS_ADDR1[11:1] HTRANSL IPS_BYTE_7_0 HWRITE IPS_BYTE_15_8 HSIZE[1:0] AIPI IPS_BYTE_23_16 HREADY_IN IPS_BYTE_31_24 AIPI_HRESP[1:0] IPS_RWB AIPI_HREADY_OUT IPS_XFR_WAIT[15:1] HCLK IPS_XFR_ERR[15:1] HCLK IPS_SUPERVISOR_A HSEL_AIPI IPS_GATED_CLK_EN[1 HRESET BIGEND_IN Figure 7-1. AIPI Interface MC9328MX1 Reference Manual MOTOROLA...

  • Page 135: Figure 7-2 Block Diagram Of The Aipi Module

    IP bus_peripheral_size aipi_timeout ips_xfr_wait ips_xfr_err ips_rdata[31:0] aipi_start_transfer aipi_watchdog ips_rdata[15:1][31:0] aipi_data_mux aipi_xfr_mux aipi_ip_decode mux_select [3:0] ips_xfr_wait[15:1] ips_xfr_err[15:1] Figure 7-2. Block Diagram of the AIPI Module MOTOROLA AHB to IP Bus Interface (AIPI)

  • Page 136: Table 7-1 R-ahb To Ip Bus Interface Operation (big Endian—read Operation)

    16-bit ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0] 32-bit ips_rdata ips_rdata – – [31:24] [23:16] – – ips_rdata[15:8] ips_rdata[7:0] MC9328MX1 Reference Manual MOTOROLA...

  • Page 137: Table 7-2 R-ahb To Ip Bus Interface Operation (big Endian—write Operation)

    – ips_wdata[7:0] – – – – ips_wdata – [15:8] – – – ips_wdata[7:0] 32-bit ips_wdata – – – [31:24] – ips_wdata – – [23:16] – – ips_wdata – [15:8] – – – ips_wdata[7:0] MOTOROLA AHB to IP Bus Interface (AIPI)

  • Page 138

    8-bit ips_wdata[7:0] – – – – ips_wdata[7:0] – – – – ips_wdata[7:0] – – – – ips_wdata[7:0] 16-bit ips_wdata ips_wdata[7:0] – – [15:8] – – ips_wdata ips_wdata[7:0] [15:8] 32-bit ips_wdata ips_wdata ips_wdata ips_wdata[7:0] [31:24] [23:16] [15:8] MC9328MX1 Reference Manual MOTOROLA...

  • Page 139: Table 7-3 R-ahb To Ip Bus Interface Operation (little Endian—read Operation)

    Word ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] 16-bit ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0] 32-bit – – ips_rdata[15:8] ips_rdata[7:0] ips_rdata ips_rdata – – [31:24] [23:16] MOTOROLA AHB to IP Bus Interface (AIPI)

  • Page 140: Table 7-4 R-ahb To Ip Bus Interface Operation (little Endian—write Operation)

    – ips_wdata[7:0] – – ips_wdata – [15:8] – ips_wdata[7:0] – – ips_wdata – – – [15:8] 32-bit – – – ips_wdata[7:0] – – ips_wdata – [15:8] – ips_wdata – – [23:16] ips_wdata – – – [31:24] MC9328MX1 Reference Manual MOTOROLA...

  • Page 141

    – ips_wdata[7:0] – – ips_wdata[7:0] – – ips_wdata[7:0] – – ips_wdata[7:0] – – – 16-bit – – ips_wdata ips_wdata[7:0] [15:8] ips_wdata ips_wdata[7:0] – – [15:8] 32-bit ips_wdata ips_wdata ips_wdata ips_wdata[7:0] [31:24] [23:16] [15:8] MOTOROLA AHB to IP Bus Interface (AIPI)

  • Page 142: Table 7-5 Aipi Module Register Memory Map, Programming Model, Table 7-6 Peripheral Address Module_en Numbers

    0x0021 5000 – 0x0021 5FFF 0x0020 6000 – 0x0020 6FFF 0x0021 6000 – 0x0021 6FFF 0x0020 7000 – 0x0020 7FFF 0x0021 7000 – 0x0021 7FFF 0x0020 8000 – 0x0020 8FFF 0x0021 8000 – 0x0021 8FFF 7-10 MC9328MX1 Reference Manual MOTOROLA...

  • Page 143

    0x0021 C000 – 0x0021 CFFF 0x0020 D000 – 0x0020 DFFF 0x0021 D000 – 0x0021 DFFF 0x0020 E000 – 0x0020 EFFF 0x0021 E000 – 0x0021 EFFF 0x0020 F000 – 0x0020 FFFF 0x0021 F000 – 0x0021 FFFF MOTOROLA AHB to IP Bus Interface (AIPI) 7-11...

  • Page 144: Peripheral Size Registers[1:0], Aipi1 Peripheral Size Register 0 And Aipi2 Peripheral Size Register 0

    Module_En (Lower)—Each bit represents the lower bit of See Table 7-9 for bit settings Bits 15–1 the 2-bit field (PSR1 + PSR0) that represents the Module_En number. Reserved Reserved—This bit is reserved and should read 0. Bit 0 7-12 MC9328MX1 Reference Manual MOTOROLA...

  • Page 145: Aipi1 Peripheral Size Register 1 And Aipi2 Peripheral Size Register 1

    AIPI registers, {PSR1[bit0], PSR0[bit0]} returns a value of 10, indicating that the AIPI registers are word width registers. Table 7-9 shows how to program the PSR registers based on the size or availability of an IP bus peripheral. MOTOROLA AHB to IP Bus Interface (AIPI) 7-13...

  • Page 146: Peripheral Access Registers, Table 7-9 Psr Data Bus Size Encoding

    Bits 31 through 16 in both registers are preset to 1 and the fields are reserved and can only be read. Addr PAR_1 AIPI1 Peripheral Access Register 0x00200008 PAR_2 AIPI2 Peripheral Access Register 0x00210008 TYPE PAR_1 RESET 0xFFFF PAR_2 RESET 0xFFFF ACCESS TYPE PAR_1 RESET 0xFFFF PAR_2 RESET 0xFFFF 7-14 MC9328MX1 Reference Manual MOTOROLA...

  • Page 147: Peripheral Control Register, Table 7-10 Peripheral Access Register Description

    Bits 31 through 16 in both registers are preset to 0 and the fields are reserved and can only be read. Addr PCR_1 AIPI1 Peripheral Control Register 0x0020000C PCR_2 AIPI2 Peripheral Control Register 0x0021000C TYPE PCR_1 RESET 0x0000 PCR_2 RESET 0x0000 ACCESS_MODE TYPE PCR_1 RESET 0x0000 PCR_2 RESET 0x0000 MOTOROLA AHB to IP Bus Interface (AIPI) 7-15...

  • Page 148: Time-out Status Register, Table 7-11 Peripheral Control Register Description

    The register is clear during initial reset. Addr TSR_1 AIPI1 Time-Out Status Register 0x00200010 TSR_2 AIPI2 Time-Out Status Register 0x00210010 ADDR TYPE TSR_1 RESET 0x0000 TSR_2 RESET 0x0000 MODULE_EN TYPE TSR_1 RESET 0x0000 TSR_2 RESET 0x0000 7-16 MC9328MX1 Reference Manual MOTOROLA...

  • Page 149: Programming Example, Data Access To 8-bit Peripherals, Table 7-12 Time-out Status Register Description

    [r2, #0x1] STRH [r2, #0x2] [r2, #0x4] LDRB [r2, #0x0] LDRB [r2, #0x1] LDRH [r2, #0x2] [r2, #0x4] The Table 7-13 on page 7-18 illustrates the difference in the 8-bit peripheral register content. MOTOROLA AHB to IP Bus Interface (AIPI) 7-17...

  • Page 150: Data Access To 16-bit Peripherals

    [r2, #0x2] [r2, #0x4] The Table 7-14 and Table 7-15 illustrate the difference in the 16-bit peripheral register content. Table 7-14. Core and 16-Bit Peripheral Register Content (Little Endian) Address Peripheral Registers – – – – 7-18 MC9328MX1 Reference Manual MOTOROLA...

  • Page 151: Data Access To 32-bit Peripherals, Table 7-15 Core And 16-bit Peripheral Register Content (big Endian)

    [r2, #0x2] [r2, #0x4] LDRB [r2, #0x0] LDRB [r2, #0x1] LDRH [r2, #0x2] [r2, #0x4] The Table 7-16 and Table 7-17 on page 7-20 illustrate the difference in the 32-bit peripheral register content. MOTOROLA AHB to IP Bus Interface (AIPI) 7-19...

  • Page 152: Special Consideration For Non-natural Size Access

    Therefore, if a programmer is using byte access to set up control information in 32-bit register, extreme care must be taken to ensure the desired byte is written during the desired endian mode. 7-20 MC9328MX1 Reference Manual MOTOROLA...

  • Page 153: Table 8-1 System Control Module Register Memory Map, Programming Model

    Table 8-1. System Control Module Register Memory Map Description Name Address Silicon ID Register SIDR 0x0021B804 Function Multiplexing Control Register FMCR 0x0021B808 Global Peripheral Control Register GPCR 0x0021B80C Global Clock Control Register GCCR 0x0021B810 MOTOROLA System Control...

  • Page 154: Silicon Id Register, Table 8-2 Silicon Id Register Description

    The settings for the bits in the register are listed in Table 8-2. Addr SIDR Silicon ID Register 0x0021B804 TYPE RESET 0x0005 TYPE RESET 0x901D Table 8-2. Silicon ID Register Description Name Description Silicon ID—Contains the chip identification number of the MC9328MX1. Bits 31–0 MC9328MX1 Reference Manual MOTOROLA...

  • Page 155: Function Multiplexing Control Register, Table 8-3 Function Multiplexing Control Register Description

    Transmit Frame Sync input source. 1 = Input from Port B[18] SIM_RST pin SSI_TXCLK_SEL SSI Transmit Clock Select—Selects the 0 = Input from Port C[8] SSI_TXCLK pin Bit 3 Transmit Clock input source. 1 = Input from Port B[19] SIM_CLK pin MOTOROLA System Control...

  • Page 156: Global Peripheral Control Register

    The Global Peripheral Control Register (GPCR) controls the driving force parameters of the bus and several other functions in the MC9328MX1. Descriptions of the register settings appear in Table 8-4. Addr GPCR Global Peripheral Control Register 0x0021B80C TYPE RESET 0x0000 TYPE RESET 0x03FB MC9328MX1 Reference Manual MOTOROLA...

  • Page 157: Table 8-4 Global Peripheral Control Register Description

    CMOS Sensor Interface Privileged Mode 0 = All access modes available Bit 0 Access—Selects whether the CSI can only be 1 = Privileged mode access only accessed in privileged mode or if it can be accessed in all modes. MOTOROLA System Control...

  • Page 158: Global Clock Control Register, Table 8-5 Global Clock Control Register Description

    1 = CSI clock input is enabled (default). Bit 2 USBD_ USBD Clock Enable—Enables/Disables clock input 0 = USB clock input is disabled. CLK_EN to the USB module. 1 = USB clock input is enabled (default). Bit 2 MC9328MX1 Reference Manual MOTOROLA...

  • Page 159: System Boot Mode Selection, Table 8-6 System Boot Mode Selection

    Output Signals BOOT[3:0] Active Device 0000 Bootstrap ROM 0001 16-bit SyncFlash D[15:0] 0010 32-bit SyncFlash 0011 8-bit CS0 at D[7:0] 0100 16-bit CS0 at D[31:16] 0101 16-bit CS0 at D[15:0] 0110 32-bit CS0 at D[31:0] 0111 Reserved MOTOROLA System Control...

  • Page 160

    System Control MC9328MX1 Reference Manual MOTOROLA...

  • Page 161: Operation

    The instruction buffer allows the user to download the vector table to the buffer without the use of external ROM or Flash. The feature provides the user a fast and easy environment to use IRQ during program debugging. MOTOROLA Bootstrap Mode Operation...

  • Page 162: Entering Bootstrap Mode, Bootstrap Record Format, Table 9-1 Bootstrap Record Format

    Comments can be added to files of b-records. As described above, the shortest b-record consists of 10 ASCII characters (when the data count is 0) of 0 to 9 or A to F (hexadecimal digits). Comments included must not contain patterns to prevent the comments from being considered a b-record. MC9328MX1 Reference Manual MOTOROLA...

  • Page 163: Registers Used In Bootloader Program, Setting Up The Rs-232 Terminal, Changing The Speed Of Communication

    The buffer starts at 0x00000004. Up to eight instructions can be loaded to the instruction buffer for execution.Usually, the last instruction is an unconditional jump instruction (jmp) that jumps to the start of the bootloader program (0x00000100). MOTOROLA Bootstrap Mode Operation...

  • Page 164: Table 9-3 Program Breakdown, Table 9-4 Resulting B-records

    Breaking down the register initialization into three parts is not mandatory, however it produces similar b-records and therefore is easier to manage. The resulting b-records appear in Table 9-4. Table 9-4. Resulting B-Records B-Record Number B-Record 00000004 08E3A04F40E1A0F004 0000000400 00000004 08E3A019C4E1A0F004 0000000400 00000004 08E3A02F40E1A0F004 0000000400 00000004 0CE59F3000E1A0F00412345678 0000000400 MC9328MX1 Reference Manual MOTOROLA...

  • Page 165: Simple Read/write Examples, Table 9-5 Read/write Examples

    0031000003XXYYZZ/ from location (where XX, YY, and ZZ are data in byte) 0x00310000 Read 3 half-words 0031000066 0031000066XXXXYYYYZZZZ/ starting from location (6 bytes = 3 half-words) (where XXXX, YYYY, and ZZZZ are data in 0x00310000 half-word) MOTOROLA Bootstrap Mode Operation...

  • Page 166

    Write 3 bytes starting 0031000003112233 0031000003112233/ from location 0x00310000 Write 3 half-words 0031000046111122223333 0031000046111122223333/ starting from location (6 bytes = 3 half-words) 0x00310000 Write 3 words starting 00310000CC111111112222 00310000CC111111112222222233333333/ from location 222233333333 0x00310000 (12 bytes = 3 words) MC9328MX1 Reference Manual MOTOROLA...

  • Page 167: Bootloader Flowchart, Special Notes, Figure 9-1 Bootloader Program Operation

    Comments in a b-record or b-record file must not contain any word or symbol that is longer than nine characters. However, the following characters can be used in a string of any length (all of these have an ASCII code value that is less than 0x30): — space MOTOROLA Bootstrap Mode Operation...

  • Page 168

    (ASCII code value less than 0x30) will force the bootloader to start a new b-record. • General-purpose registers r7–r14 and supervisor scratch registerss3 are used by the bootloader program. Writing to these registers may corrupt the bootloader program. • Please visit the DragonBall Web site for bootstrap utility programs. MC9328MX1 Reference Manual MOTOROLA...

  • Page 169: Figure 10-1 Aitc Block Diagram, Introduction

    Supports a maximum of 64 interrupt sources • Supports fast and normal interrupts • Selects normal or fast interrupt request for any interrupt source • Indicates pending interrupt sources via a register for normal and fast interrupts MOTOROLA Interrupt Controller (AITC) 10-1...

  • Page 170

    The interrupt requests are prioritized in the following order: 1. Fast interrupt requests, in order of highest number 2. Normal interrupt requests, in order of highest priority level, then highest source number with the same priority 10-2 MC9328MX1 Reference Manual MOTOROLA...

  • Page 171: Aitc Interrupt Controller Signals, Table 10-1 Interrupt Assignment

    Unused PWM_INT Unused MMC_IRQ Unused Unused PEN_UP_INT Unused CSI_INT Unused MMA_MAC_INT I2C_INT MMA_INT SPI2_INT COMP_INT SPI1_INT MSIRQ SSI_TX_INT GPIO_INT_PORTA SSI_TX_ERR_INT GPIO_INT_PORTB SSI_RX_INT GPIO_INT_PORTC SSI_RX_ERR_INT LCDC_INT TOUCH_INT SIM_IRQ USBD_INT [0] SIM_DATA USBD_INT [1] RTC_INT USBD_INT [2] MOTOROLA Interrupt Controller (AITC) 10-3...

  • Page 172: Table 10-2 Aitc Module Register Memory Map, Programming Model

    Interrupt Disable Number Register INTDISNUM 0x0022300C Interrupt Enable Register High INTENABLEH 0x00223010 Interrupt Enable Register Low INTENABLEL 0x00223014 Interrupt Type Register High INTTYPEH 0x00223018 Interrupt Type Register Low INTTYPEL 0x0022301C Normal Interrupt Priority Level Register 7 NIPRIORITY7 0x00223020 10-4 MC9328MX1 Reference Manual MOTOROLA...

  • Page 173

    0x00223050 Interrupt Force Register Low INTFRCL 0x00223054 Normal Interrupt Pending Register High NIPNDH 0x00223058 Normal Interrupt Pending Register Low NIPNDL 0x0022305C Fast Interrupt Pending Register High FIPNDH 0x00223060 Fast Interrupt Pending Register Low FIPNDL 0x00223064 MOTOROLA Interrupt Controller (AITC) 10-5...

  • Page 174: Table 10-3 Register Field Summary

    NIPRIORITY2 NIPR23 NIPR22 NIPR21 NIPR20 NIPR19 NIPR18 NIPR17 NIPR16 NIPRIORITY1 NIPR15 NIPR14 NIPR13 NIPR12 NIPR11 NIPR10 NIPR9 NIPR8 NIPRIORITY0 NIPR7 NIPR6 NIPR5 NIPR4 NIPR3 NIPR2 NIPR1 NIPR0 NIVECTOR NIPRILVL NIVECSR FIVECTOR FIVECSR INTIN [63:32] INTSRCH 10-6 MC9328MX1 Reference Manual MOTOROLA...

  • Page 175: Interrupt Control Register, Table 10-4 Interrupt Control Register Description

    (32-bit) boundaries. Addr INTCNTL Interrupt Control Register 0x00223000 NIAD FIAD TYPE RESET 0x0000 TYPE RESET 0x0000 Table 10-4. Interrupt Control Register Description Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–21 MOTOROLA Interrupt Controller (AITC) 10-7...

  • Page 176

    Note: To prevent an alternate master from accessing the bus during an interrupt service routine, do not clear the interrupt flag until the end of the service routine. Reserved Reserved—These bits are reserved and should read 0. Bits 18–0 10-8 MC9328MX1 Reference Manual MOTOROLA...

  • Page 177: Normal Interrupt Mask Register, Table 10-5 Normal Interrupt Mask Register Description

    1 = Disable priority level 1 and lower normal interrupts of priority level less than or equal to the NIMASK are disabled. Settings are shown 16+ = Disable all normal interrupts. in decimal. Setting bit 4 disables all normal interrupts. MOTOROLA Interrupt Controller (AITC) 10-9...

  • Page 178: Interrupt Enable Number Register, Table 10-6 Interrupt Enable Number Register Description

    Reserved—These bits are reserved and should read 0. Bits 31–6 ENNUM Interrupt Enable Number—Enables/Disables the 0x00 = Enable interrupt source 0 Bits 5–0 interrupt source associated with this value. 0x01 = Enable interrupt source 1 0x3F = Enable interrupt source 63 10-10 MC9328MX1 Reference Manual MOTOROLA...

  • Page 179: Interrupt Disable Number Register, Table 10-7 Interrupt Disable Number Register Description

    Reserved—These bits are reserved and should read 0. Bits 31–6 DISNUM Interrupt Disable Number—Enables/Disables the 0x00 = Disable interrupt source 0 Bits 5–0 interrupt source associated with this value. 0x01 = Disable interrupt source 1 0x3F = Disable interrupt source 63 MOTOROLA Interrupt Controller (AITC) 10-11...

  • Page 180: Interrupt Enable Register High And Interrupt Enable Register Low, Interrupt Enable Register High

    INTTYPEH and INTTYPEL setting. interrupt upon assertion 10-12 MC9328MX1 Reference Manual MOTOROLA...

  • Page 181: Interrupt Enable Register Low, Table 10-9 Interrupt Enable Register Low Description

    INTTYPEH and INTTYPEL setting. interrupt upon assertion MOTOROLA Interrupt Controller (AITC) 10-13...

  • Page 182: Interrupt Type Register High And Interrupt Type Register Low, Interrupt Type Register High

    (nIRQ) When a INTTYPE bit is set and the corresponding interrupt 1 = Interrupt source generates a source is asserted, the interrupt controller asserts a fast interrupt fast interrupt (nFIQ) request. 10-14 MC9328MX1 Reference Manual MOTOROLA...

  • Page 183: Interrupt Type Register Low, Normal Interrupt Priority Level Registers

    NIMASK has not disabled level 1 normal interrupts. These registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be accessed only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries. MOTOROLA Interrupt Controller (AITC) 10-15...

  • Page 184: Normal Interrupt Priority Level Register 7, Table 10-12 Normal Interrupt Priority Level Register 7 Description

    1111 = Highest priority normal Bits 27–24 These registers do not affect the prioritization of fast interrupt interrupt priorities. NIPR61 Bits 23–20 NIPR60 Bits 19–16 NIPR59 Bits 15–12 NIPR58 Bits 11–8 NIPR57 Bits 7–4 NIPR56 Bits 3–0 10-16 MC9328MX1 Reference Manual MOTOROLA...

  • Page 185: Normal Interrupt Priority Level Register 6, Table 10-13 Normal Interrupt Priority Level Register 6 Description

    1111 = Highest priority normal Bits 27–24 These registers do not affect the prioritization of fast interrupt interrupt priorities. NIPR53 Bits 23–20 NIPR52 Bits 19–16 NIPR51 Bits 15–12 NIPR50 Bits 11–8 NIPR49 Bits 7–4 NIPR48 Bits 3–0 MOTOROLA Interrupt Controller (AITC) 10-17...

  • Page 186: Normal Interrupt Priority Level Register 5, Table 10-14 Normal Interrupt Priority Level Register 5 Description

    1111 = Highest priority normal Bits 27–24 These registers do not affect the prioritization of fast interrupt interrupt priorities. NIPR45 Bits 23–20 NIPR44 Bits 19–16 NIPR43 Bits 15–12 NIPR42 Bits 11–8 NIPR41 Bits 7–4 NIPR40 Bits 3–0 10-18 MC9328MX1 Reference Manual MOTOROLA...

  • Page 187: Normal Interrupt Priority Level Register 4, Table 10-15 Normal Interrupt Priority Level Register 4 Description

    1111 = Highest priority normal Bits 27–24 These registers do not affect the prioritization of fast interrupt interrupt priorities. NIPR37 Bits 23–20 NIPR36 Bits 19–16 NIPR35 Bits 15–12 NIPR34 Bits 11–8 NIPR33 Bits 7–4 NIPR32 Bits 3–0 MOTOROLA Interrupt Controller (AITC) 10-19...

  • Page 188: Normal Interrupt Priority Level Register 3, Table 10-16 Normal Interrupt Priority Level Register 3 Description

    1111 = Highest priority normal Bits 27–24 These registers do not affect the prioritization of fast interrupt interrupt priorities. NIPR29 Bits 23–20 NIPR28 Bits 19–16 NIPR27 Bits 15–12 NIPR26 Bits 11–8 NIPR25 Bits 7–4 NIPR24 Bits 3–0 10-20 MC9328MX1 Reference Manual MOTOROLA...

  • Page 189: Normal Interrupt Priority Level Register 2, Table 10-17 Normal Interrupt Priority Level Register 2 Description

    1111 = Highest priority normal Bits 27–24 These registers do not affect the prioritization of fast interrupt interrupt priorities. NIPR21 Bits 23–20 NIPR20 Bits 19–16 NIPR19 Bits 15–12 NIPR18 Bits 11–8 NIPR17 Bits 7–4 NIPR16 Bits 3–0 MOTOROLA Interrupt Controller (AITC) 10-21...

  • Page 190: Normal Interrupt Priority Level Register 1, Table 10-18 Normal Interrupt Priority Level Register 1 Description

    1111 = Highest priority normal Bits 27–24 These registers do not affect the prioritization of fast interrupt interrupt priorities. NIPR13 Bits 23–20 NIPR12 Bits 19–16 NIPR11 Bits 15–12 NIPR10 Bits 11–8 NIPR9 Bits 7–4 NIPR8 Bits 3–0 10-22 MC9328MX1 Reference Manual MOTOROLA...

  • Page 191: Normal Interrupt Priority Level Register 0, Table 10-19 Normal Interrupt Priority Level Register 0 Description

    1111 = Highest priority normal Bits 27–24 These registers do not affect the prioritization of fast interrupt interrupt priorities. NIPR5 Bits 23–20 NIPR4 Bits 19–16 NIPR3 Bits 15–12 NIPR2 Bits 11–8 NIPR1 Bits 7–4 NIPR0 Bits 3–0 MOTOROLA Interrupt Controller (AITC) 10-23...

  • Page 192: Normal Interrupt Vector And Status Register, Table 10-20 Normal Interrupt Vector And Status Register Description

    This number can be written to the NIMASK to disable the current priority normal interrupts to build 15 = Highest priority normal interrupt is level a reentrant normal interrupt system. Settings are shown in decimal. 16+ = No normal interrupt request pending 10-24 MC9328MX1 Reference Manual MOTOROLA...

  • Page 193: Fast Interrupt Vector And Status Register, Table 10-21 Fast Interrupt Vector And Status Register Description

    0 = Interrupt 0 is highest pending fast interrupt 1 = Interrupt 1 is highest pending fast interrupt 63 = Interrupt 63 is highest pending fast interrupt 64+ = not used, does not occur MOTOROLA Interrupt Controller (AITC) 10-25...

  • Page 194: Interrupt Source Register High And Interrupt Source Register Low, Interrupt Source Register High

    1 = Interrupt source asserted NOTE: The peripheral circuits generating the requests determine the state of this register out of reset; normally, the requests are inactive. This read-only register must be accessed only on word (32-bit) boundaries. 10-26 MC9328MX1 Reference Manual MOTOROLA...

  • Page 195: Interrupt Source Register Low, Table 10-23 Interrupt Source Register Low Description

    1 = Interrupt source asserted NOTE: The state of this register out of reset is determined by the peripheral circuits generating the requests; normally, the requests are inactive. This read-only register must be accessed only on word (32-bit) boundaries. MOTOROLA Interrupt Controller (AITC) 10-27...

  • Page 196: Interrupt Force Register High And Interrupt Force Register Low, Interrupt Force Register High

    0x0000 Table 10-24. Interrupt Force Register High Description Name Description Settings FORCE Interrupt Source Force Request—Forces a request for the 0 = Standard interrupt operation Bits 31–0 corresponding interrupt source. 1 = Interrupt forced asserted 10-28 MC9328MX1 Reference Manual MOTOROLA...

  • Page 197: Interrupt Force Register Low, Table 10-25 Interrupt Force Register Low Description

    0x0000 Table 10-25. Interrupt Force Register Low Description Name Description Settings FORCE Interrupt Source Force Request—Forces a request for the 0 = Standard interrupt operation Bits 31–0 corresponding interrupt source. 1 = Interrupt forced asserted MOTOROLA Interrupt Controller (AITC) 10-29...

  • Page 198: And Normal Interrupt Pending Register Low, Normal Interrupt Pending Register High

    The normal interrupt pending bits reflect the interrupt input lines that are asserted and are currently enabled to generate a normal interrupt. 10-30 MC9328MX1 Reference Manual MOTOROLA...

  • Page 199: Normal Interrupt Pending Register Low, Table 10-27 Normal Interrupt Pending Register Low Description

    The normal interrupt pending bits reflect the interrupt input lines that are asserted and are currently enabled to generate a normal interrupt. MOTOROLA Interrupt Controller (AITC) 10-31...

  • Page 200: Fast Interrupt Pending Register High And Fast Interrupt Pending Register Low

    1 = Fast interrupt request pending controller asserts a fast interrupt request. The fast interrupt pending bits reflect the interrupt input lines that are asserted and are currently enabled to generate a fast interrupt. 10-32 MC9328MX1 Reference Manual MOTOROLA...

  • Page 201: Fast Interrupt Pending Register Low, Table 10-29 Fast Interrupt Pending Register Low Description

    1 = Fast interrupt request pending controller asserts a fast interrupt request. The fast interrupt pending bits reflect the interrupt input lines that are asserted and are currently enabled to generate a fast interrupt. MOTOROLA Interrupt Controller (AITC) 10-33...

  • Page 202: Arm920t Processor Interrupt Controller Operation, Arm920t Processor Prioritization Of Exception Sources

    ORs this mask to the correct INTENABLEH and INTENABLEL register. To disable interrupts, the procedure is exactly the same except the source number is written to the INTDISNUM register. 10-34 MC9328MX1 Reference Manual MOTOROLA...

  • Page 203: Typical Interrupt Entry Sequences, Table 10-30 Typical Hardware Accelerated Normal Interrupt Entry Sequence

    FIQ service routine begins at 0x0000001C and single cycle memories. Table 10-31. Typical Fast Interrupt Entry Sequence Time Address –2 –1 nFIQ nFIQ Assert Last ADDR before nFIQ Fetch Exec Link Adjust +4 / +2 Fetch +8 / +4 Fetch 0x0000001C Fetch Exec MOTOROLA Interrupt Controller (AITC) 10-35...

  • Page 204: Writing Reentrant Normal Interrupt Routines

    13. Pop the link register from the stack into the PC. 14. Return from nIRQ. NOTE: These steps are still in development and are subject to change. Steps 1, 2, 13, and 14 are automatically done by most C compilers and are included for completeness. 10-36 MC9328MX1 Reference Manual MOTOROLA...

  • Page 205: Eim I/o Signals, Overview, Address Bus, Data Bus

    The A [24:0] signals are address bus outputs used to address external devices. 11.2.2 Data Bus The D [31:0] signals are bidirectional data bus pins used to transfer data between the MC9328MX1 and an external device. MOTOROLA External Interface Module (EIM) 11-1...

  • Page 206: Read/write, Control Signals, Oe—output Enable, Eb [3:0]—enable Bytes, Dtack—data Transfer Acknowledge, Chip Select Outputs

    The CS1 through CS5 output signals are active-low and are asserted based on a decode of the internal address bus bits A [31:24] of the accessed address. When disabled, these pins can be used as programmable general-purpose outputs. Table 11-1 specifies the address range for each Chip Select output. 11-2 MC9328MX1 Reference Manual MOTOROLA...

  • Page 207: Burst Mode Signals, Bclk—burst Clock, Lba—load Burst Address, Ecb—end Current Burst, Pin Configuration For Eim

    11.3 Pin Configuration for EIM Table 11-2 lists the pins used for the EIM module. Many of these pins are multiplexed with other functions on the device, and must be configured for EIM operation. MOTOROLA External Interface Module (EIM) 11-3...

  • Page 208: Table 11-2 Eim Pin List, Table 11-3 Pin Configuration

    1. Clear bits [23:22] of Port A GPIO In Use Register (GIUS_A) A [23:22] 2. Clear bits [23:22] of Port A General Purpose Register (GPR_A) CS [3] Primary function of pin shared 1. Clear bit 1 (SDCS1_SEL) of Function Muxing Control Register (FMCR) with SDRAM’s CSD1 11-4 MC9328MX1 Reference Manual MOTOROLA...

  • Page 209

    2. Clear bit 19 of Port A General Purpose Register (GPR_A) Not Multiplexed Primary function of GPIO Port 1. Clear bit 20 of Port A GPIO In Use Register (GIUS_A) A [20] 2. Clear bit 20 of Port A General Purpose Register (GPR_A) MOTOROLA External Interface Module (EIM) 11-5...

  • Page 210: Typical Eim System Connections, Figure 11-1 Example Of Eim Interface To Memory And Peripherals

    Intel EB [2] Flash EB [2] 512Kx16 D [15:0] Data [15:0] ACIA R’W D [7:0] Data [7:0] BCLK Control D [7:0] Data [7:0] EB [3] Figure 11-1. Example of EIM Interface to Memory and Peripherals 11-6 MC9328MX1 Reference Manual MOTOROLA...

  • Page 211: Figure 11-2 Example Of Eim Interface To Burst Memory

    BCLK FLASH WAIT# D [31:16] DQ [15:0] 1Mx16 A [16:1] Address [15:0] EB [2] EB [2] EB [3] EB [3] 64Kx16 D [15:1] Data [15:0] Figure 11-2. Example of EIM Interface to Burst Memory MOTOROLA External Interface Module (EIM) 11-7...

  • Page 212: Eim Functionality, Configurable Bus Sizing, Programmable Output Generation, Burst Mode Operation, Burst Clock Divisor

    AHB bus. The internal bus frequency can be divided by 2, 3, or 4 for presentation on the external bus in burst mode operation. 11-8 MC9328MX1 Reference Manual MOTOROLA...

  • Page 213: Burst Clock Start, Page Mode Emulation, Error Conditions

    • User read or write access to a chip select control register or the EIM configuration register • Byte or halfword access to a chip select control register or the EIM configuration register MOTOROLA External Interface Module (EIM) 11-9...

  • Page 214: Table 11-4 Eim Module Register Memory Map, Programming Model

    Chip Select 4 Upper Control Register CS4U 0x00220020 Chip Select 4 Lower Control Register CS4L 0x00220024 Chip Select 5 Upper Control Register CS5U 0x00220028 Chip Select 5 Lower Control Register CS5L 0x0022002C EIM Configuration Register 0x00220030 11-10 MC9328MX1 Reference Manual MOTOROLA...

  • Page 215: Chip Select 0 Control Registers, Chip Select 0 Upper Control Register

    11.6.1.2 Chip Select 0 Lower Control Register Addr CS0L Chip Select 0 Lower Control Register 0x00220004 TYPE RESET 0x0000 CSEN TYPE RESET 0x0801 For bit descriptions, see Table 11-5 on page 11-13. *Configurable on reset. MOTOROLA External Interface Module (EIM) 11-11...

  • Page 216: Chip Select 1–chip Select 5 Control Registers

    Chip Select 3 Upper Control Register 0x00220018 CS4U Chip Select 4 Upper Control Register 0x00220020 CS5U Chip Select 5 Upper Control Register 0x00220028 62 61 DTACK_SEL SYNC TYPE RESET 0x0000 46 45 TYPE rw rw RESET 0x0000 11-12 MC9328MX1 Reference Manual MOTOROLA...

  • Page 217: Table 11-5 Chip Select Control Registers Description

    When the 11 = Divisor is 4 BCM bit is set (BCM = 1) in the EIM configuration register, BCD is ignored. BCD is cleared by a hardware reset. MOTOROLA External Interface Module (EIM) 11-13...

  • Page 218

    EIM data setup time requirements. DOL has no effect on EIM data latching when SYNC = 0. DOL is cleared by a hardware reset. 11-14 MC9328MX1 Reference Manual MOTOROLA...

  • Page 219

    See Table 11-6, "Chip Select Wait State and Bits 38–36 additional wait-states are required for write Burst Delay Encoding" cycles. This is useful for writing to memories that require additional data setup time. WWS is cleared by a hardware reset. MOTOROLA External Interface Module (EIM) 11-15...

  • Page 220

    0001 = 1 half clock before assertion meet data setup time requirements for slow memories. 1111 = 15 half clocks before assertion WEA does not affect the cycle length. WEA is cleared by a hardware reset. 11-16 MC9328MX1 Reference Manual MOTOROLA...

  • Page 221

    User mode results in a TEA to the ARM9 core and no assertion of the chip select output Reserved Reserved—This bit is reserved and should read 0. Bit 5 MOTOROLA External Interface Module (EIM) 11-17...

  • Page 222: Table 11-6 Chip Select Wait State And Burst Delay Encoding

    Table 11-6. Chip Select Wait State and Burst Delay Encoding Number of Wait-States WWS = 0 WWS = 1 WWS = 7 WSC [5:0] Read Write Read Write Read Write Access Access Access Access Access Access 000000 000001 000010 000011 000100 000101 000110 11-18 MC9328MX1 Reference Manual MOTOROLA...

  • Page 223

    Read Write Access Access Access Access Access Access 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 MOTOROLA External Interface Module (EIM) 11-19...

  • Page 224

    Write Read Write Access Access Access Access Access Access 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 11-20 MC9328MX1 Reference Manual MOTOROLA...

  • Page 225: Eim Configuration Register, Table 11-7 Eim Configuration Register Description

    The EIM Configuration Register contains the bit that controls the operation of the burst clock. Addr EIM Configuration Register 0x00220030 TYPE RESET 0x0000 TYPE RESET 0x0000 Table 11-7. EIM Configuration Register Description Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31– 3 MOTOROLA External Interface Module (EIM) 11-21...

  • Page 226

    BCD and BCS bits in the chip select control register. 1 = The burst clock runs all the time (independent of chip select accesses). Reserved Reserved—These bits are reserved and should read 0. Bits 1–0 11-22 MC9328MX1 Reference Manual MOTOROLA...

  • Page 227: Clock Sources, Introduction, Low Frequency Clock Source

    System_SEL bit in the Clock Source Control Register to produce all of the system clocks from a single 32 kHz crystal oscillator. See Section 12.3.1, “DPLL Phase and Frequency Jitter,” for more detailed information on phase and frequency jitter specifications using this configuration. MOTOROLA Phase-Locked Loop and Clock Controller 12-1...

  • Page 228: High Frequency Clock Source, Figure 12-1 Clock Controller Module

    16 MHz clock input from an external Bluetooth RF module through the Stop internal BTA module. CLK48M Continuous 48 MHz clock output when System PLL is enabled or when external 48 MHz clock is selected. FCLK Fast clock (FCLK) output to the CPU. 12-2 MC9328MX1 Reference Manual MOTOROLA...

  • Page 229: Dpll Output Frequency Calculation, Dpll Phase And Frequency Jitter

    Frequency and Phase Lock (FPL) mode. The DPLL mode is user selectable. The DPLL communicates with the clock module. This block contains a control register and provides an interface between the DPLL and the ARMTDMI core. MOTOROLA Phase-Locked Loop and Clock Controller 12-3...

  • Page 230: Mc9328mx1 Power Management, Pll Operation At Power-up, Pll Operation At Wake-up, Arm920t Processor Low-power Modes

    Deep power-down mode 12.4.5 Power Management in the Clock Controller Power management in the MC9328MX1 is achieved by controlling the duty cycles of the clock system efficiently. The clocking control scheme is shown in Table 12-3. 12-4 MC9328MX1 Reference Manual MOTOROLA...

  • Page 231: Clock Source Control Register, Programming Model, Table 12-3 Power Management In The Clock Controller

    32 kHz derived clock source to the System PLL when the design requires clock signals with greater frequency and phase jitter performance than the internal PLL using the 32 kHz clock source provides. MOTOROLA Phase-Locked Loop and Clock Controller 12-5...

  • Page 232: Table 12-5 Clock Source Control Register Description

    11 = System PLL shuts down after forth rising edge of CLK32 is detected and the current bus cycle is completed. Reserved Reserved—This bit is reserved and should read 0. Bit 23 12-6 MC9328MX1 Reference Manual MOTOROLA...

  • Page 233

    PLL. When cleared, the MCU PLL is disabled. 1 = MCU PLL enabled When software writes 0 to MPEN, the PLL shuts down immediately. MPEN sets automatically when MPLLEN asserts, and on system reset. MOTOROLA Phase-Locked Loop and Clock Controller 12-7...

  • Page 234: Peripheral Clock Divider Register, Table 12-6 Clock Sources For Peripherals

    0000 = Divide by 1 Bits 7–4 produces the PERCLK2 clock signal for the peripherals. The input to 0001 = Divide by 2 the PCLK_DIV2 divider circuit is System PLLCLK. … 1111 = Divide by 16 12-8 MC9328MX1 Reference Manual MOTOROLA...

  • Page 235: Programming Digital Phase Locked Loops, Mcu Pll Control Register 0, Table 12-8 Sample Frequency Table

    MCU PLL settings: 1. Program the desired values of PD, MFD, MFI, and MFN into the MPCTL0. 2. Set the MPLL_RESTART bit in the CSCR (it will self-clear). 3. New PLL settings will take place. MOTOROLA Phase-Locked Loop and Clock Controller 12-9...

  • Page 236: Table 12-9 Mcu Pll Control Register 0 Description

    BRM value for the MF. When a new value is written into the MFN bits, 0x001 = 1 the PLL loses its lock; after a time delay, the PLL re-locks. 0x3FE = 1022 0x3FF = Reserved 12-10 MC9328MX1 Reference Manual MOTOROLA...

  • Page 237: Mcu Pll And System Clock Control Register 1, Generation Of 48 Mhz Clocks

    Table 12-11. System PLL Multiplier Factor Input Premultiplier Output USBDIV Clock Frequency Frequency Frequency 32 kHz 16.384 MHz 96 MHz 48 MHz The default setting exception is USB_DIV. The user must program this to 010. MOTOROLA Phase-Locked Loop and Clock Controller 12-11...

  • Page 238: System Pll Control Register 0, Table 12-12 System Pll Control Register 0 Description

    BRM value for the MF. When a new value is written into the MFD9–MFD0 0x001 = 1 bits, the PLL loses its lock: after a time delay, the PLL re-locks. … 0x3FF = 1023 Reserved Reserved—These bits are reserved and should read 0. Bits 15–14 12-12 MC9328MX1 Reference Manual MOTOROLA...

  • Page 239: System Pll Control Register 1, Table 12-13 System Pll Control Register 1 Description

    System PLL clock output is valid. When cleared, the 1 = System PLL is locked System PLL clock output remains at logic high. Reserved Reserved—These bits are reserved and should read 0. Bits 14–7 MOTOROLA Phase-Locked Loop and Clock Controller 12-13...

  • Page 240

    1 = BRM has second order 9/10. In other cases, the second order BRM is used. The BRMO bit is cleared by a hardware reset. Reserved Reserved—These bits are reserved and should read 0. Bits 5–0 12-14 MC9328MX1 Reference Manual MOTOROLA...

  • Page 241

    The DMA controller provides an acknowledge signal to the peripheral after a DMA burst is complete. This signal is sometimes used by the peripheral to clear some status bits. • Repeat data transfer function supports automatic USB host–USB device bulk/iso data stream transfer. MOTOROLA DMA Controller 13-1...

  • Page 242: Figure 13-1 Dmac In Mc9328mx1, Block Diagram, Figure 13-2 Dmac Block Diagram

    Cntl Signal Generation DMA_ACK DMA_ACK, AHB I/F DMA_EOBO, and DMA_EOBO AHB_A [31:0] Address DMA_EOBO_CNT Generation Generation DMA_EOBO_CNT DMA_ERR AHB I/F Interrupt AHB_D [31:0] Data Buffer DMA_INT Generation × 32 Data FIFO Figure 13-2. DMAC Block Diagram 13-2 MC9328MX1 Reference Manual MOTOROLA...

  • Page 243: Signal Description, Figure 13-3 Dma Request And Acknowledge Timing Diagram, Figure 13-4 2d Memory Diagram

    This signal must be negated by the peripheral automatically before the rising edge of DMA_ACK. It is usually negated when the FIFO is read. DMA_ACK DMA request acknowledge generated by the DMA controller to signal the end of a DMA burst. MOTOROLA DMA Controller 13-3...

  • Page 244: Big Endian And Little Endian, Programming Model, Table 13-2 Dma Module Register Memory Map

    Table 13-2. DMA Module Register Memory Map Description Name Address General Registers DMA Control Register 0x00209000 DMA Interrupt Status Register DISR 0x00209004 DMA Interrupt Mask Register DIMR 0x00209008 DMA Burst Time-Out Status Register DBTOSR 0x0020900C 13-4 MC9328MX1 Reference Manual MOTOROLA...

  • Page 245

    Channel 2 Control Register CCR2 0x0020910C Channel 2 Request Source Select Register RSSR2 0x00209110 Channel 2 Burst Length Register BLR2 0x00209114 Channel 2 Request Time-Out Register RTOR2 0x00209118 Channel 2 Bus Utilization Control Register BUCR2 0x00209118 MOTOROLA DMA Controller 13-5...

  • Page 246

    Channel 8 Control Register CCR8 0x0020928C Channel 8 Request Source Select Register RSSR8 0x00209290 Channel 8 Burst Length Register BLR8 0x00209294 Channel 8 Request Time-Out Register RTOR8 0x00209298 Channel 8 Bus Utilization Control Register BUCR8 0x00209298 13-6 MC9328MX1 Reference Manual MOTOROLA...

  • Page 247

    Channel 10 Control Register CCR10 0x0020930C Channel 10 Request Source Select Register RSSR10 0x00209310 Channel 10 Burst Length Register BLR10 0x00209314 Channel 10 Request Time-Out Register RTOR10 0x00209318 Channel 10 Bus Utilization Control Register BUCR10 0x00209318 MOTOROLA DMA Controller 13-7...

  • Page 248: General Registers, Dma Control Register, Table 13-3 Dma Control Register Description

    DRST always reads 0. 1 = Generates a 3-cycle reset pulse DMA Enable—Enables/Disables the system clock to the DMA module. 0 = DMA disable Bit 0 1 = DMA enable 13-8 MC9328MX1 Reference Manual MOTOROLA...

  • Page 249: Dma Interrupt Status Register, Table 13-4 Dma Interrupt Status Register Description

    Reserved Reserved—These bits are reserved and should read 0. Bits 31–11 CH10–CH0 Channel 10 to 0 Interrupt Status—Indicates the interrupt status for 0 = No interrupt Bits 10–0 each DMA channel. 1 = Interrupt is pending MOTOROLA DMA Controller 13-9...

  • Page 250: Dma Interrupt Mask Register, Table 13-5 Dma Interrupt Mask Register Description

    Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–11 CH10–CH0 Channel 10 to 0—Controls the interrupts for each DMA channel. 0 = Enables interrupts Bits 10–0 1 = Disables interrupts 13-10 MC9328MX1 Reference Manual MOTOROLA...

  • Page 251: Dma Burst Time-out Status Register, Table 13-6 Dma Burst Time-out Status Register Description

    Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–11 CH10–CH0 Channel 10 to 0—Indicates the burst time-out status of each DMA 0 = No burst time-out Bits 10–0 channel. 1 = Burst time-out MOTOROLA DMA Controller 13-11...

  • Page 252: Dma Request Time-out Status Register, Table 13-7 Dma Request Time-out Status Register Description

    Reserved—These bits are reserved and should read 0. Bits 31–11 CH10–CH0 Channel 10 to 0—Indicates the request time-out status of each 0 = No DMA request time-out Bits 10–0 DMA channel. 1 = DMA request time-out 13-12 MC9328MX1 Reference Manual MOTOROLA...

  • Page 253: Dma Transfer Error Status Register, Table 13-8 Dma Transfer Error Status Register Description

    Reserved Reserved—These bits are reserved and should read 0. Bits 31–11 CH10–CH0 Channel 10 to 0—Indicates the DMA transfer error status of each 0 = No transfer error Bits 10–0 DMA channel. 1 = Transfer error MOTOROLA DMA Controller 13-13...

  • Page 254: Dma Buffer Overflow Status Register, Table 13-9 Dma Buffer Overflow Status Register Description

    Reserved—These bits are reserved and should read 0. Bits 31–11 CH10–CH0 Channel 10 to 0—Indicates the buffer overflow error status 0 = No buffer overflow occurred Bits 10–0 of each DMA channel. 1 = Buffer overflow occurred 13-14 MC9328MX1 Reference Manual MOTOROLA...

  • Page 255: Dma Burst Time-out Control Register, Table 13-10 Dma Burst Time-out Control Register Description

    Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 Enable—Enables/Disables the burst time-out. 0 = Disables burst time-out Bit 15 1 = Enables burst time-out Count—Contains the time-out count down value. Bits 14–0 MOTOROLA DMA Controller 13-15...

  • Page 256: D Memory Registers (a And B), W-size Registers, Table 13-11 W-size Registers Description

    0x0000 TYPE RESET 0x0000 Table 13-11. W-Size Registers Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 W-Size—Contains the number of bytes that make up the display width. Bits 15–0 13-16 MC9328MX1 Reference Manual MOTOROLA...

  • Page 257: X-size Registers, Table 13-12 X-size Registers Description

    Table 13-12. X-Size Registers Description Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 X-Size—Contains the number of bytes per row that define the X-Size of the 2D memory. Bits 15–0 MOTOROLA DMA Controller 13-17...

  • Page 258: Y-size Registers, Channel Registers, Table 13-13 Y-size Registers Description

    A DMA request time-out is true • A DMA burst time-out is true during a burst cycle • The internal buffer overflows during a burst cycle • A transfer error acknowledge is asserted during a burst cycle 13-18 MC9328MX1 Reference Manual MOTOROLA...

  • Page 259: Channel Source Address Register, Table 13-14 Channel Source Address Register Description

    0. These bits will be read/write as any value if and only if running in big endian and source mode set to FIFO. This is to allow FIFO to use offset address during big endian mode. MOTOROLA DMA Controller 13-19...

  • Page 260: Destination Address Registers, Table 13-15 Channel Destination Address Registers Description

    Destination Address—Contains the destination address to which data is written to during a DMA Bits 31–2 transfer. DA [1], DA [0] Destination Address [1] and Destination Address [0]—To ensure that all addresses are Bits 1–0 word-aligned, these bits are set internally to 0. 13-20 MC9328MX1 Reference Manual MOTOROLA...

  • Page 261: Channel Count Registers, Table 13-16 Channel Count Registers Description

    Channel 9 Count Register 0x002092C8 CNTR10 Channel 10 Count Register 0x00209308 TYPE RESET 0x0000 TYPE RESET 0x0000 Table 13-16. Channel Count Registers Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–24 MOTOROLA DMA Controller 13-21...

  • Page 262: Channel Control Registers

    0x0020924C CCR8 Channel 8 Control Register 0x0020928C CCR9 Channel 9 Control Register 0x002092CC CCR10 Channel 10 Control Register 0x0020930C TYPE RESET 0x0000 DMOD SMOD MDIR MSEL DSIZ SSIZ REN RPT FRC CEN TYPE RESET 0x0000 13-22 MC9328MX1 Reference Manual MOTOROLA...

  • Page 263: Table 13-17 Channel Control Registers Description

    Interrupt Mask Register is cleared. The address is reloaded from the source and destination address register for the next DMA burst. Data transfer is carried out continuously until the channel is disabled or it completes the last cycle after RPT is cleared. MOTOROLA DMA Controller 13-23...

  • Page 264: Table 13-18 Dma_eobo_cnt And Dma_eobi_cnt Settings

    FIFO of a USB device. Table 13-18. DMA_EOBO_CNT and DMA_EOBI_CNT Settings DMA_EOBI_CNT [1:0] or Number of Bytes Per Transfer DMA_EOBO_CNT [1:0] 13-24 MC9328MX1 Reference Manual MOTOROLA...

  • Page 265: Channel Request Source Select Registers, Table 13-19 Channel Request Source Select Registers Description

    Bits 31–5 Request Source Select—Selects one of the 32 DMA_REQ 00000 = select DMA_REQ [0] Bits 4–0 signals that initiates a DMA transfer cycle for the channel. 00001 = select DMA_REQ [1] 11111 = select DMA_REQ [31] MOTOROLA DMA Controller 13-25...

  • Page 266: Channel Burst Length Registers, Table 13-20 Channel Burst Length Registers Description

    0x002092D4 BLR10 Channel 10 Burst Length Register 0x00209314 TYPE RESET 0x0000 TYPE RESET 0x0000 Table 13-20. Channel Burst Length Registers Description Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–6 13-26 MC9328MX1 Reference Manual MOTOROLA...

  • Page 267: Channel Request Time-out Registers

    Channel 6 Request Time-Out Register 0x00209218 RTOR7 Channel 7 Request Time-Out Register 0x00209258 RTOR8 Channel 8 Request Time-Out Register 0x00209298 RTOR9 Channel 9 Request Time-Out Register 0x002092D8 RTOR10 Channel 10 Request Time-Out Register 0x00209318 TYPE RESET 0x0000 TYPE RESET 0x0000 MOTOROLA DMA Controller 13-27...

  • Page 268: Channel 0 Bus Utilization Control Register, Table 13-21 Channel Request Time-out Registers Description

    In this case, the user must be careful not to violate the maximum bus request latency of other devices. NOTE: This register shares the same address of request time-out register. 13-28 MC9328MX1 Reference Manual MOTOROLA...

  • Page 269: Table 13-22 Channel 0 Bus Utilization Control Registers Description

    Reserved—These bits are reserved and should read 0. Bits 31–16 CCNT Clock Count—Sets the number of system clocks that must occur before the memory channel Bits 15–0 releases the AHB, before the next DMA request for the channel. MOTOROLA DMA Controller 13-29...

  • Page 270: Dma Request Table, Table 13-23 Dma Request Table

    DMA_REQ [10] DSPA DCT DIN DMA Request DMA_REQ [9] DSPA DCT DOUT DMA Request DMA_REQ [8] MSHC DMA Request DMA_REQ [7] CSI Receive FIFO DMA Request DMA_REQ [6] CSI Statistic FIFO DMA Request DMA_REQ [5] Reserved 13-30 MC9328MX1 Reference Manual MOTOROLA...

  • Page 271

    DMA Request Table Table 13-23. DMA Request Table (Continued) DMA Request Peripheral DMA_REQ [4] Reserved DMA_REQ [3] Reserved DMA_REQ [2] Reserved DMA_REQ [1] Reserved DMA_REQ [0] Reserved MOTOROLA DMA Controller 13-31...

  • Page 272

    DMA Controller 13-32 MC9328MX1 Reference Manual MOTOROLA...

  • Page 273: General Overview, Watchdog Timer Operation, Timing Specifications, Figure 14-1 Watchdog Timer Functional Block Diagram

    7-bit counter to obtain a range of 0.5 to 64 seconds. The user can determine the time-out period by writing to the watchdog time-out field (WT[6:0]) in the Watchdog Control Register (WCR). WHALT (Time-Out) 7-bit Counter CLK2HZ CLK32K Test Mode (TMD bit) Figure 14-1. Watchdog Timer Functional Block Diagram MOTOROLA Watchdog Timer Module 14-1...

  • Page 274: Watchdog During Reset, Power-on Reset, Software Reset, Watchdog After Reset, Initial Load, Countdown, Reload

    If the WSR is not loaded with a $5555 prior to a write of $AAAA to the WSR, the counter will not be reloaded. If any value other than $AAAA is written to the WSR after $5555, the counter will not be reloaded. 14-2 MC9328MX1 Reference Manual MOTOROLA...

  • Page 275: Time-out, Halting The Counter, Watchdog Control, Interrupt Control, Reset Sources

    Reading the TINT bit clears the interrupt and this status bit. 14.4.2 Reset Sources The watchdog timer generates reset signal WDT_RST as a result of a WDOG time-out. This signal is an output to the Reset Module for system reset generation. MOTOROLA Watchdog Timer Module 14-3...

  • Page 276: State Machine, Figure 14-2 Counter State Machine

    Start Counter Decrement Counter Counting Resumed (fiq, irq, reset) Counting Halted (WHALT=1) Counter Suspended Reload Counter Serviced Count Assert Time-out Indication Interrupt Request Assert wdt_rst Assert wdt_int Reset Interrupt Module Handler Figure 14-2. Counter State Machine 14-4 MC9328MX1 Reference Manual MOTOROLA...

  • Page 277: Watchdog Timer I/o Signals, Table 14-1 Watchdog Timer I/o Signals

    Module read/write signal IPS_ADDR[11:2] Module address bus IPS_WDATA[31:0] Module write data bus SCAN_MODE Indicates scan mode selection SCAN_RESET Indicates scan reset IPS_CONT_CLK_EN ips_cont_clk enable IPS_XFR_ERR Transfer error acknowledge IPS_XFR_WAIT Transfer wait acknowledge IPS_RDATA[31:0] Module read data bus MOTOROLA Watchdog Timer Module 14-5...

  • Page 278: Watchdog Control Register, Programming Model, Table 14-2 Watchdog Control Register Description

    1 = Counter is halted The WHALT bit can be cleared by writing 0 to it or it can be automatically cleared by the occurrence of any of three system events, fast interrupt, slow interrupt, or system reset. 14-6 MC9328MX1 Reference Manual MOTOROLA...

  • Page 279: Watchdog Service Register

    The Watchdog Service register contains the watchdog service sequence. When Watchdog is enabled, the Watchdog requires that a service sequence be written to the Watchdog Service Register (WSR) as described in Table 14-3. Addr Watchdog Service Register 0x00201004 TYPE RESET 0x0000 TYPE RESET 0x0000 MOTOROLA Watchdog Timer Module 14-7...

  • Page 280: Watchdog Status Register, Table 14-3 Watchdog Service Register Description, Table 14-4 Watchdog Status Register Description

    1 = Time-out interrupt generated Reserved Reserved—These bits are reserved and should read 0. Bits 7–1 TOUT Time-Out—Indicates whether the watchdog timer times 0 = Watchdog timer does not time-out. Bit 0 out. 1 = Watchdog timer times out. 14-8 MC9328MX1 Reference Manual MOTOROLA...

  • Page 281

    Programming Model MOTOROLA Watchdog Timer Module 14-9...

  • Page 282

    Watchdog Timer Module 14-10 MC9328MX1 Reference Manual MOTOROLA...

  • Page 283: Asp Signal Description, Features, Figure 15-1 Asp System Block Diagram

    SAMPLE RATE CTRL REG Detect LOGIC COMPARE CONTROL REG PADC SWITCH INPUT SELECT From Touch PEN SAMPLE REG (12X16-bit) CIRCUIT Panel comp_int touch_int pen_up_int For Touch Interrupt Generation INTERRUPT GENERATOR pen_data_int Figure 15-1. ASP System Block Diagram MOTOROLA Analog Signal Processor (ASP) 15-1...

  • Page 284: Figure 15-2 Simplified Asp Signal Path Diagram, Table 15-1 Asp Interface Signal Description

    Read Y: SW[8..1] = 0011 1001 Auto zero: SW[8..1] = 0000 0000 Auto Calibration X SW[8..1] = 1100 1100 Auto Calibration Y SW[8..1] = 0011 0011 Default: SW [8:1] = 0010 000 Figure 15-2. Simplified ASP Signal Path Diagram 15-2 MC9328MX1 Reference Manual MOTOROLA...

  • Page 285: Interrupt Generation, Pen Adc (padc) Operation, Table 15-2 Simplified Asp Signal Path Parameters

    FIFO will overflow and old data will be overwritten. When an overflow occurs, the POV status bit is set in the Interrupt/Error Status Register. MOTOROLA Analog Signal Processor (ASP)

  • Page 286: Current-mode Operation, Table 15-3 Pen Adc Operation

    = (Vm - V2b) / R2 Where ip and im are limited to ≤ ≤ • -2.5µA +9.5µA ≤ ≤ • -2.5µA +9.5µA Calculation for ∆ i is as follows: ≤ ≤ ∆ i -12µA +12µA Eqn. 15-1 15-4 MC9328MX1 Reference Manual MOTOROLA...

  • Page 287: Sample Rate Control, Figure 15-3 Pen Input Sampling Timing

    DSCNT (t1)—Data setup count: This controls the time for the MUX and touch panel to settle. The max value is 1.575ms at ACLK = 12MHz. • DMCNT (t2)—Decimation count: This controls the number of samples to be averaged, which effectively performs a simple comb filter as the second-stage decimation filter. MOTOROLA Analog Signal Processor (ASP) 15-5...

  • Page 288: Table 15-5 Output Data Rate Equations

    9.6 kHz when DMCNT = 0 and IDLECNT = 0. DSCNT can be set to 0 as there is no need for the settling time for the touch panel and MUX. To get a 200Hz output data rate, set DSCNT = 0, DMCNT = 0, and IDLECNT = 47. 15-6 MC9328MX1 Reference Manual MOTOROLA...

  • Page 289: Auto-zero Function, Pen-down Detection, Pen-up Detection (method 1 – Compare Value)

    Because a temperature compensation circuit does not exist in the ASP module, software must be used for compensation. Auto calibration mode provides the necessary switch settings to help software provide temperature compensation. MOTOROLA Analog Signal Processor (ASP) 15-7...

  • Page 290: Table 15-6 Asp Module Register Memory Map, Programming Model

    Pen A/D Sample Rate Control Register ASP_PSMPLRG 0x00215014 Compare Control Register ASP_CMPCNTL 0x00215030 Interrupt Control Register ASP_ICNTLR 0x00215018 Interrupt/Error Status Register ASP_ISTATR 0x0021501C Pen Sample FIFO ASP_PADFIFO 0x00215000 Clock Divide Register ASP_CLKDIV 0x0021502C ASP FIFO Pointer Register ASP_FIFO_PTR 0x00215034 15-8 MC9328MX1 Reference Manual MOTOROLA...

  • Page 291: Asp Control Register, Table 15-7 Control Register Description

    Reserved—This bit is reserved and should read 0. Bit 22 U_SEL U-Channel Resistor Selection—Selects which external 0 = Resistor at UIN and UIP pins Bit 21 resistor to use for U-channel measurement. 1 = Resistor at R1a and R2a pins MOTOROLA Analog Signal Processor (ASP) 15-9...

  • Page 292

    X is [11000110]; Y is [00111001]. Bit 8 Exception cases occur when ACAL bit or ASWB bits are set. Bit 7 Bit 6 Bit 5 Bit 4 Reserved Reserved—These bits are reserved and should read 0. Bits 3–2 15-10 MC9328MX1 Reference Manual MOTOROLA...

  • Page 293: Pen A/d Sample Rate Control Register, Table 15-8 Pen A/d Sample Rate Control Register Description

    010 = Decimation ratio is 3 011 = Decimation ratio is 4 100 = Decimation ratio is 5 101 = Decimation ratio is 6 110 = Decimation ratio is 7 111 = Decimation ratio is 8 MOTOROLA Analog Signal Processor (ASP) 15-11...

  • Page 294: Compare Control Register, Table 15-9 Compare Control Register Description

    Reserved—These bits are reserved and should read 0. Bits 31–20 Interrupt Status—Sets when a trigger event is 0 = No trigger event was detected Bit 19 detected. Write 1 to clear. 1 = A trigger event was detected 15-12 MC9328MX1 Reference Manual MOTOROLA...

  • Page 295: Table 15-10 Interrupt Control Register Description, Interrupt Control Register

    Reserved—These bits are reserved and should read 0. Bits 9 - 7 Pen Interrupt Polarity—Selects the polarity of the TOUCH_INT 0 = Active low, or falling edge Bit 6 input signal for interrupt trigger. 1 = Active high, or rising edge MOTOROLA Analog Signal Processor (ASP) 15-13...

  • Page 296: Interrupt/error Status Register, Table 15-11 Interrupt/error Status Register Description

    Pen-up Status—Bit is set when a pen-up event is pending. 0 = No pen-up interrupt is pending Bit 10 Clear by writing ‘1’. 1 = Pen-up interrupt is pending Reserved Reserved—These bits are reserved and should read 0. Bits 9–8 15-14 MC9328MX1 Reference Manual MOTOROLA...

  • Page 297: Pen Sample Fifo

    The 12x16 Pen Sample FIFO holds the sample data after Pen A/D sampling. The data structure is controlled by the MOD bits of control register. Addr ASP_PADFIFO Pen Sample FIFO 0x00215000 TYPE RESET 0X0000 SAMPLE TYPE RESET 0X0000 MOTOROLA Analog Signal Processor (ASP) 15-15...

  • Page 298: Clock Divide Register, Table 15-12 Pen Sample Fifo Register Description

    PADC_CLK PADC Clock Divider—Selects the divide ratio to generate the 0x00 = Clock disabled Bits 4–0 clock for use by the pen ADC. 0x01 = Divider ratio is 2 0x1F = Divider ratio is 32 15-16 MC9328MX1 Reference Manual MOTOROLA...

  • Page 299: Asp Fifo Pointer Register, Table 15-14 Asp Fifo Pointer Register Description

    Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–5 PEN_FIFO_READ_POINTER PEN_FIFO_READ_POINTER—Holds the read pointer of PADC FIFO. Bit 7–4 PEN_FIFO_WRITE_POINTER PEN_FIFO_WRITE_POINTER—Holds the write pointer of PADC FIFO. Bit 3–0 MOTOROLA Analog Signal Processor (ASP) 15-17...

  • Page 300

    Analog Signal Processor (ASP) 15-18 MC9328MX1 Reference Manual MOTOROLA...

  • Page 301: Bluetooth Primer

    A Bluetooth system consists of a radio unit, a link control unit, and a support unit for link management and host terminal interface functions (see Figure 16-1 on page 16-2). The radio, link controller, and link manager are described in the Specification of the Bluetooth System, version 1.1. MOTOROLA Bluetooth Accelerator (BTA) 16-1...

  • Page 302: Bta Overview, Figure 16-1 Functional Blocks In A Bluetooth System

    Sequence Estimation (MLSE/JD) pre-processor for improved RF performance • Bluetooth Application Timer (BAT) • Low-power support IP-bus interface (16-bit Blue-line Standard, version 2.0) • Bluetooth Bluetooth Link Manager Bluetooth Radio Link Controller and I/O Figure 16-1. Functional Blocks in a Bluetooth System 16-2 MC9328MX1 Reference Manual MOTOROLA...

  • Page 303: Module Descriptions, Bluetooth Core, Figure 16-2 Functional Blocks In The Bluetooth Accelerator

    Bluetooth core can be accessed to write to the control words and to retrieve the status of the Bluetooth core. Within the Bluetooth core, the main functional blocks are: • IP bus interface • Sequencer • Bluetooth pipeline processor MOTOROLA Bluetooth Accelerator (BTA) 16-3...

  • Page 304: Ip Bus Interface, Table 16-1 Clk_control Register Settings For Synchronization

    Refer to Section 16.5.9.1, “Clock Control Register.” Table 16-1. CLK_CONTROL Register Settings for Synchronization BT1_CLK_IN_DIV Value ips_clk (MHz) BT1_WSLOT Value BT1_RSLOT Value 2, (6) 2, (6) 2, (3) 2, (3) 16-4 MC9328MX1 Reference Manual MOTOROLA...

  • Page 305: Sequencer, Bluetooth Clocks, Table 16-2 Bluetooth Clocks And Counters

    Difference between NativeCount and EstimatedCount. NativeClk 3.2 kHz Low (power down) Free-running native clock of the unit. High (operation) When the unit is the master of a communication, the remote slave must synchronize to this clock. MOTOROLA Bluetooth Accelerator (BTA) 16-5...

  • Page 306

    This one-shot interrupt is termed “BTsys.” 2. An interrupt triggered by the Bluetooth application timer termed “BTtim.” 3. An interrupt generated during the wake-up sequence termed “BTwui.” The interrupts are summarized and described in Table 16-3 on page 16-7. 16-6 MC9328MX1 Reference Manual MOTOROLA...

  • Page 307: Bluetooth Pipeline Processor, Table 16-3 Bluetooth Core Interrupts

    HEC/CRC generator and checker • Encryption and decryption engine • Whitening and de-whitening logic • FEC coding and decoding The four units process incoming or outgoing Bluetooth packets. Figure 16-3 shows the format of a Bluetooth packet. MOTOROLA Bluetooth Accelerator (BTA) 16-7...

  • Page 308: Hec/crc Generator And Checker, Figure 16-3 Bluetooth Packet Format

    The type information is available from the packet header and length information fields in the payload header field, which is the first one or two bytes of the payload, depending on the packet 16-8 MC9328MX1 Reference Manual MOTOROLA...

  • Page 309: Table 16-4 Packet Types And Fec/crc Processing

    Disabled Disabled 1100 Disabled Disabled Disabled 1101 Disabled Disabled Disabled 1110 Enabled Disabled Enabled 1111 Enabled Disabled Disabled CRC and 2/3 FEC are performed on the data field only. Not defined in the standard yet. MOTOROLA Bluetooth Accelerator (BTA) 16-9...

  • Page 310: Encryption And Decryption Engine, Table 16-5 Writing Sequence For Encryption Engine Initialization

    Table 16-5. Writing Sequence for Encryption Engine Initialization Word Number Bits 15–8 Bits 7–0 Kc’[1] Kc’[0] Kc’[3] Kc’[2] Kc’[5] Kc’[4] Kc’[7] Kc’[6] Kc’[9] Kc’[8] Kc’[11] Kc’[10] Kc’[13] Kc’[12] Kc’[15] Kc’[14] Addr[1] Addr[0] Addr[3] Addr[2] Addr[5] Addr[4] 16-10 MC9328MX1 Reference Manual MOTOROLA...

  • Page 311: Whitening/de-whitening, Fec Coding/decoding, Bit Buffer

    64-bit “long words,” designated LW0 through LW7. Software views each long word as four concatenated 16 bit words that are accessed independently. Figure 16-4 illustrates the arrangement of the long words in the bit buffer. MOTOROLA Bluetooth Accelerator (BTA) 16-11...

  • Page 312: Correlator, Figure 16-4 Bitbuf Memory, Table 16-6 Functions Using The Bit Buffer

    The threshold for the correlator is programmable via the THRESHOLD register. The correlation peak value in the most recent correlation window can be read from the same register. Software access to the bit buffer is prohibited during correlation because of the bit buffer time sharing (see section 16.3.1.4). 16-12 MC9328MX1 Reference Manual MOTOROLA...

  • Page 313: Bluetooth Application Timer, Hop Selection Co-processor, Radio Control, Table 16-7 Hop Selection Co-processor Writing Sequence

    In) Register,” on page 16-84 16.3.1.8 Radio Control The radio interface supports two RF front ends: • Motorola Radio, MC13180, SPI Interface • SiliconWave Radio, SiW1502, SPI Interface The selection of the used interface is determined via software by writing to the RF_CONTROL register.

  • Page 314: Frequency Synthesizer And Timing Control, Pulse Width Modulators, Radio Module Interfaces

    PWM_TX register while the RSSI value is written to the PWM_RSSI register. 16.3.1.8.3 Radio Module Interfaces MC13180 Radio (3 Wire SPI) The MC13180 radio is programmed via a three wire serial programming interface (SPI) comprised of the spi_data, spi_en, and spi_clk lines. 16-14 MC9328MX1 Reference Manual MOTOROLA...

  • Page 315: Figure 16-5 Programming Interfaces For The Mc13180 Radio

    SPI. Writing to the SPI_READ_ADDR or SPI_WRITE_ADDR register overrides any previous SPI address maintained in that register by the Bluetooth core. The timing of the MC13180 radio is shown in Figure 16-6 on page 16-16. MOTOROLA Bluetooth Accelerator (BTA) 16-15...

  • Page 316: Figure 16-6 Timing Of The Rf Module Control Signals For The Mc13180 Radio

    The radio increments the address of the radio register by one after each write. The mapping of the data written to the SPI_WORD0 through SPI_WORD3 registers in the programming sequence illustrated in Figure 16-7. 16-16 MC9328MX1 Reference Manual MOTOROLA...

  • Page 317: Figure 16-7 Programming Interface For The Siwave Radio

    ( 1) Ca n be t ristated depe nding on RF_ Contro l Register BT pa cket dat a Sa me as (1) BT packet data Rx_data SysTick SysTick Idle Idle Figure 16-8. Timing of RF Module Control Signals for the SiWave Radio MOTOROLA Bluetooth Accelerator (BTA) 16-17...

  • Page 318: Wake-up Module, Figure 16-9 Block Diagram Of The Wake-up Module

    3. The WAKEUP_4 register holds the value at which the Bluetooth clock is enabled again (BT1ClkHold goes high). After receiving a WU2 event, WAKEUP_4 is updated with the sum of the WU_COUNT and WAKEUP_DELTA4 registers. The WAKEUP_DELTA4 value 16-18 MC9328MX1 Reference Manual MOTOROLA...

  • Page 319: Pin Configuration For Bta, Figure 16-10 Timing Of The Wake-up Signals

    BTA operation. NOTE: The user must ensure that the data direction bits in the GPIO are set to the correct direction for proper operation. See Section 32.5.1, “Data Direction Registers,” on page 32-9 for details. MOTOROLA Bluetooth Accelerator (BTA) 16-19...

  • Page 320: Table 16-9 Pin Configuration, Programming Model

    For clarification, when the behavior changes significantly, the same address is given two different names. Table 16-10 on page 16-21 summarizes these registers and their addresses. Table 16-11 on page 16-23 provides an alternate view of the memory map 16-20 MC9328MX1 Reference Manual MOTOROLA...

  • Page 321: Table 16-10 Bta Module Register Memory Map

    RF Control Register RF_CONTROL 0x0021605C Write RF Status Register RF_STATUS 0x0021605C Read RX Time Register RX_TIME 0x00216060 Write TX Time Register TX_TIME 0x00216064 Write Bluetooth Application Timer Register 0x00216068 Write Threshold Register THRESHOLD 0x0021606C Write MOTOROLA Bluetooth Accelerator (BTA) 16-21...

  • Page 322

    Write SPI Write Address Register SPI_WRITE_ADDR 0x00216130 Write SPI Read Address Register SPI_READ_ADDR 0x00216134 Write SPI Control Register SPI_CONTROL 0x00216138 Write SPI Status Register SPI_STATUS 0x00216138 Read Hop 0 (Frequency In) Register HOP0 0x00216140 Write 16-22 MC9328MX1 Reference Manual MOTOROLA...

  • Page 323: Table 16-11 Bta Module Register Overview

    NATIVE_COUNT NATIVE_COUNT Clocks 0x00216010 ESTIMATED_COUNT ESTIMATED_COUNT 0x00216014 OFFSET_COUNT OFFSET_COUNT 0x00216018 NATIVECLK_LOW NATIVECLK_LOW 0x0021601C NATIVECLK_HIGH NATIVECLK_HIGH 0x00216020 ESTIMATED_CLK_LOW ESTIMATED_CLK_LOW 0x00216024 ESTIMATED_CLK_HIGH ESTIMATED_CLK_HIGH 0x00216028 OFFSET_CLK_LOW OFFSET_CLK_LOW 0x0021602C OFFSET_CLK_HIGH OFFSET_CLK_HIGH Bluetooth 0x00216030 HECCRC_CONTROL Pipeline 0x00216034 WHITE_CONTROL 0x00216038 ENCRYPTION_CONTROL_X13 MOTOROLA Bluetooth Accelerator (BTA) 16-23...

  • Page 324

    BUF_WORD_2 (LW0) 0x002160F4 BUF_WORD_29 (LW7) BUF_WORD_29 (LW7) 0x002160F8 BUF_WORD_30 (LW7) BUF_WORD_30 (LW7) 0x002160FC BUF_WORD_31 (LW7) BUF_WORD_31 (LW7) Wake-Up 0x00216100 WAKEUP_1 WAKEUP_1 0x00216104 WAKEUP_2 WAKEUP_2 0x0021610C WAKEUP_DELTA4 WAKEUP_4 0x00216110 WU_CONTROL WU_STATUS 0x00216114 WU_COUNT System 0x00216118 CLK_CONTROL CLK_CONTROL 16-24 MC9328MX1 Reference Manual MOTOROLA...

  • Page 325

    0x00216134 SPI_READ_ADDR 0x00216138 SPI_CONTROL SPI_STATUS Frequency 0x00216140 HOP0 HOP_FREQ_OUT Hopping 0x00216144 HOP1 0x00216148 HOP2 0x0021614C HOP3 0x00216150 HOP4 Interrupt 0x00216160 INTERRUPT_VECTOR INTERRUPT_VECTOR Joint 0x00216170 SYNC_METRIC Detection 0x00216174 SYNC_FC Reversing 0x00216178 WORD_REVERSE WORD_REVERSE 0x0021617C BYTE_REVERSE BYTE_REVERSE MOTOROLA Bluetooth Accelerator (BTA) 16-25...

  • Page 326: Sequencer Registers, Command Register, Table 16-12 Command Register Description

    Bit 12 to bypass the Bluetooth pipeline module. When bypass is 1 = Bypass Bluetooth pipeline selected (PIPE is set), data flows directly between the Bit Buffer after the header trailer bits and the RF sub-modules. 16-26 MC9328MX1 Reference Manual MOTOROLA...

  • Page 327: Status Register

    BTA. The Status Register bits and their settings are described in Table 16-13 on page 16-28. Addr STATUS Status Register 0x00216000 TYPE RESET 0x0000 MS2LSB REC1 REC2 NREC CRC16 HEC8 STATE BUF_ADDR TYPE RESET 0x0040 MOTOROLA Bluetooth Accelerator (BTA) 16-27...

  • Page 328: Table 16-13 Status Register Description

    (but not including) the long word currently used by the BTA. (It can read up to BUF_ADDR-1) The software must keep track of the last long word accessed. 16-28 MC9328MX1 Reference Manual MOTOROLA...

  • Page 329: Packet Header Register, Table 16-14 Packet Header Register Description

    ARQN—Defined in the Bluetooth header standard. Bit 8 FLOW FLOW—Defined in the Bluetooth header standard. Bit 7 TYPE TYPE—Defined in the Bluetooth header standard. Bits 6–3 AM_ADDR AM_Addr—Defined in the Bluetooth header standard. Bits 2–0 MOTOROLA Bluetooth Accelerator (BTA) 16-29...

  • Page 330: Payload Header Register, Table 16-15 Payload Header Register Description

    Reserved—These bits are reserved and should read 0. Bits 31–12 LENGTH Payload Length—Contains a 5- or 9-bit payload length determined by packet type. Bits 11–3 FLOW Flow—Defined in the Bluetooth standard. Bit 2 L_CH Logical Channel—Defined in the Bluetooth standard. Bits 1–0 16-30 MC9328MX1 Reference Manual MOTOROLA...

  • Page 331: Bluetooth Clocks Registers, Native Count Register, Table 16-16 Native Count Register Description

    Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–12 NATIVE_COUNT Native Count—Contains the NATIVECOUNT counter, which divides the high precision 8 MHz Bits 11–0 clock to generate the 3.2 kHz SYSTICK. MOTOROLA Bluetooth Accelerator (BTA) 16-31...

  • Page 332: Estimated Count Register, Table 16-17 Estimated Count Register Description

    Reserved Reserved—These bits are reserved and should read 0. Bits 31–12 ESTIMATED_COUNT ESTIMATEDCOUNT—Contains the ESTIMATEDCOUNT counter, which is clocked by Bits 11–0 the high precision 8 MHz clock and preset by the access code triggering. 16-32 MC9328MX1 Reference Manual MOTOROLA...

  • Page 333: Offset Count Register, Table 16-18 Offset Count Register Description

    0x0000 OFFSET_COUNT TYPE RESET 0x0000 Table 16-18. Offset Count Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–12 OFFSET_COUNT Off Set Count—Contains the OFFSETCOUNT, which generates OFFSETCLK. Bits 11–0 MOTOROLA Bluetooth Accelerator (BTA) 16-33...

  • Page 334: Native Clock Low Register, Table 16-19 Native Clock Low Register Description

    Table 16-19. Native Clock Low Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 NATIVECLK_LOW Lower Two Bytes of the NATIVECLK—Contains the LSB (bits 15–0) of the 28-bit Bits 15–0 NATIVECLK. 16-34 MC9328MX1 Reference Manual MOTOROLA...

  • Page 335: Native Clock High Register, Table 16-20 Native Clock High Register Description

    Table 16-20. Native Clock High Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–12 NATIVECLK_HIGH High Bits of the NATIVECLK—Contains the MSBs (bits 27–16) of the 28-bit NATIVECLK. Bits 11–0 MOTOROLA Bluetooth Accelerator (BTA) 16-35...

  • Page 336: Estimated Clock Low Register, Table 16-21 Estimated Clock Low Register Description

    Table 16-21. Estimated Clock Low Register Description Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 ESTIMATED_CLK_LOW Lower 2 Bytes of the ESTIMATEDCLK—Contains the LSB (bits 15–0) of the 28-bit Bits 15–0 ESTIMATEDCLK. 16-36 MC9328MX1 Reference Manual MOTOROLA...

  • Page 337: Estimated Clock High Register, Table 16-22 Estimated Clock High Register Description

    Table 16-22. Estimated Clock High Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–12 ESTIMATED_CLK_HIGH High Bits of the ESTIMATEDCLK—Contains the MSBs (bits 27–16) of the 28-bit Bits 11–0 ESTIMATEDCLK. MOTOROLA Bluetooth Accelerator (BTA) 16-37...

  • Page 338: Offset Clock Low Register, Table 16-23 Offset Clock Low Register Description

    Table 16-23. Offset Clock Low Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 OFFSET_CLK_LOW Lower 2 Bytes of OFFSETCLK—Contains the LSB (bits 15–0) of the 28-bit OFFSETCLK. Bits 15–0 16-38 MC9328MX1 Reference Manual MOTOROLA...

  • Page 339: Offset Clock High Register, Table 16-24 Offset Clock High Register Description

    Table 16-24. Offset Clock High Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–12 OFFSET_CLK_HIGH High Bits of OFFSETCLK—Contains the MSBs (bits 27–16) of the 28-bit OFFSETCLK. Bits 11–0 MOTOROLA Bluetooth Accelerator (BTA) 16-39...

  • Page 340: Bluetooth Pipeline Registers, Heccrc Control Register, Table 16-25 Heccrc Control Register Description

    Field—Initializes the registers for generating registers. The lower byte (bits 7:0) is the same the check bits for HEC and CRC. for both HEC and CRC while the upper byte (bits 15:8) is all 0s. 16-40 MC9328MX1 Reference Manual MOTOROLA...

  • Page 341: White Control Register, Table 16-26 White Control Register Description

    Reserved Reserved—These bits are reserved and should read 0. Bits 31–7 WHITE_INIT Whitening Unit Initialization Field—Initializes the registers Initialization values for the Bits 6–0 that generate the whitening sequence. registers that generate the whitening sequence. MOTOROLA Bluetooth Accelerator (BTA) 16-41...

  • Page 342: Encryption Control X13 Register, Table 16-27 Encryption Control X13 Register Description

    Reserved—These bits are reserved and should read 0. Bits 31–16 ENCRYPT Encryption Words—Receives a sequence of 13 words to initialize and To disable encryption, do Bits 15–0 set up the encryption engine. not write to this register. 16-42 MC9328MX1 Reference Manual MOTOROLA...

  • Page 343: Radio Control Registers, Correlation Time Setup Register, Table 16-28 Correlation Time Setup Register Description

    Reserved—These bits are reserved and should read 0. Bits 31–10 EST_PRELOAD_TIME Set Correlation Time—Holds the preload time value. The EST_PRELOAD_TIME value Bits 9–0 is loaded into the ESTIMATEDCLK counter when the trigger is asserted during correlation in slave mode. MOTOROLA Bluetooth Accelerator (BTA) 16-43...

  • Page 344: Correlation Time Stamp Register, Table 16-29 Correlation Time Stamp Register Description

    RESET 0x0000 Table 16-29. Correlation Time Stamp Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–12 CORR_TIME Get Correlation Time—Indicates the time when the trigger was asserted. Bits 11–0 16-44 MC9328MX1 Reference Manual MOTOROLA...

  • Page 345: Rf Gpo Register, Table 16-30 Rf Gpo Register Description

    GPO Data Out—Holds the data value driven out to BT9 when GPO_EN2 is set to Enabled. Bit 1 GPO_DOUT1 GPO Data Out—Holds the data value driven out to BT6 when GPO_EN1 is set to Enabled. Bit 0 MOTOROLA Bluetooth Accelerator (BTA) 16-45...

  • Page 346: Pwm Received Signal Strength Indicator Register

    MC13180 radios. When read, returns the RSSI digitized by the BTA. The returned value will either be the peak RSSI value or the current RSSI value, depending on the value of the PEAK_HLD bit in the RF Control Register. 16-46 MC9328MX1 Reference Manual MOTOROLA...

  • Page 347: Time A & B Register, Table 16-32 Time A & B Register Description

    Time B—Sets the Timing B of the signals interfacing to the RF module. The timing unit is Bits 15–8 expressed in “µs before the next SYSTICK”. TIME_A Time A—Sets the Timing A of the signals interfacing to the RF module. Bits 7–0 MOTOROLA Bluetooth Accelerator (BTA) 16-47...

  • Page 348: Time C & D Register, Table 16-33 Time C & D Register Description

    Time C—Sets the timing C of the signals The timing unit is expressed in “µs before the next Bits 4–0 interfacing to the RF module. SYSTICK”. See Figure 16-8 on page 16-17 for more details. 16-48 MC9328MX1 Reference Manual MOTOROLA...

  • Page 349: Pwm Tx Register, Table 16-34 Pwm Tx Register Description

    Table 16-34. PWM TX Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–6 PWM_TX Pulse Width Modulation—Sets the PWM for transmit power control. Bits 5–0 Note: This applies to the MC13180 radio only. MOTOROLA Bluetooth Accelerator (BTA) 16-49...

  • Page 350: Rf Control Register, Table 16-35 Rf Control Register Description

    Antenna Diversity Selection—Selects the 0 = Antenna 0 Bit 10 antenna. 1 = Antenna 1 Selection—Selects the operation (either diversity 0 = Oscillator enable operation Bit 9 selection or oscillator enable) of BT7 pin. 1 = Diversity selection 16-50 MC9328MX1 Reference Manual MOTOROLA...

  • Page 351

    DELAY_HOP_STROBE Delay HOP Strobe—Delays the HOP strobe on 000 = No delay Bits 2–0 BT9 in the SiliconWave radio. 001 = 2µs 010 = 4µs 100 = 8µs 111 = 15µs All other settings reserved MOTOROLA Bluetooth Accelerator (BTA) 16-51...

  • Page 352: Rf Status Register, Table 16-36 Rf Status Register Description

    0 = Antenna 0 Bit 10 antenna currently used. 1 = Antenna 1 Selection—Indicates the operation (either 0 = Oscillator enable operation Bit 9 diversity selection or oscillator enable) of BT7 pin. 1 = Diversity selection 16-52 MC9328MX1 Reference Manual MOTOROLA...

  • Page 353

    1 = Generate spike on EOF DELAY_HOP_STROBE Delay HOP Strobe—Delays the HOP strobe on 000 = No delay Bits 2–0 BT9 in the SiliconWave radio. 001 = 2µs 010 = 4µs 100 = 8µs 111 = 15µs MOTOROLA Bluetooth Accelerator (BTA) 16-53...

  • Page 354: Rx Time Register, Table 16-37 Rx Time Register Description

    00000 to 11000, which means that clock that counts from 0 (0x000) to 2499 (x9C3). The the search window start time ranges RX_TIME_START field defines the bits x. from 288µs and 312µs. MS_CLK [11:0] = 1001 xxxx x000. 16-54 MC9328MX1 Reference Manual MOTOROLA...

  • Page 355: Tx Time Register, Table 16-38 Tx Time Register Description

    00000 to 11000, which counts from 0 (0x000) to 2499 (x9C3). The means that the search window TX_TIME_START field defines the bits x. start time ranges from 288 µs MS_CLK [11:0] = 1001 xxxx x000. and 312 µs. MOTOROLA Bluetooth Accelerator (BTA) 16-55...

  • Page 356: Timer Register, Bluetooth Application Timer Register, Table 16-39 Bluetooth Application Timer Register Description

    Preset value written to the Bits 11–0 Bluetooth application timer. The timer is clocked by the 8 MHz application timer clock. An interrupt is issued after the count is reached and automatic reloading is performed. 16-56 MC9328MX1 Reference Manual MOTOROLA...

  • Page 357: Correlator Registers, Threshold Register, Table 16-40 Threshold Register Description (mc13180)

    Bits 31–8 THRESHOLD_II Signal Energy—Sets the clipping level for the access code Default setting is 0.5625 Bits 7–4 correlation. THRESHOLD_I Threshold Value—Sets the threshold value for the access code Default setting is 1.25 Bits 3–0 correlation. MOTOROLA Bluetooth Accelerator (BTA) 16-57...

  • Page 358: Table 16-41 Threshold Register Description (siliconwave), Table 16-42 Signal Energy Levels And Threshold Levels

    0.8125 0.68750 0.8750 0.71875 0.9375 0.75000 1.0000 0.78125 1.0625 0.81250 1.1250 0.84375 1.1875 0.87500 1.2500 0.90625 1.3125 0.93750 1.3750 0.96875 1.4375 Note: Levels vary according to the values written to the THRESHOLD_I and THRESHOLD_II fields. 16-58 MC9328MX1 Reference Manual MOTOROLA...

  • Page 359: Correlation Max Register, Table 16-43 Correlation Max Register Description

    Table 16-43. Correlation Max Register Description Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–9 VALUE Maximum Correlation Value—Contains the maximum correlation value during the correlation Bits 8–0 phase. Note: N/A in MC13180 mode. MOTOROLA Bluetooth Accelerator (BTA) 16-59...

  • Page 360: Synch Word 0 Register, Table 16-44 Synch Word 0 Register Description

    Table 16-44. Synch Word 0 Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 WORD Part of Synchronization Code—Receives bits [15:0] of the 64-bit access code for the correlation. Bits 15–0 16-60 MC9328MX1 Reference Manual MOTOROLA...

  • Page 361: Synch Word 1 Register, Table 16-45 Synch Word 1 Register Description

    Table 16-45. Synch Word 1 Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 WORD Part of Synchronization Code—Receives bits [31:16] of the 64-bit access code for the correlation. Bits 15–0 MOTOROLA Bluetooth Accelerator (BTA) 16-61...

  • Page 362: Synch Word 2 Register, Synch Word 3 Register, Table 16-46 Synch Word 2 Register Description

    Part of Synchronization Code—Receives bits [47:32] of the 64-bit access code for the correlation. Bits 15–0 16.5.6.6 Synch Word 3 Register The write-only Synch Word 3 Register bits are explained in Table 16-47. Addr SYNCH_WORD_3 Synch Word 3 Register 0x0021607C TYPE RESET 0x0000 WORD TYPE RESET 0xDA25 16-62 MC9328MX1 Reference Manual MOTOROLA...

  • Page 363: Bit Buffer Registers, Buffer Word Registers, Table 16-47 Synch Word 3 Register Description

    0x002160FC TYPE RESET 0x0000 WORD TYPE RESET 0x0000 Table 16-48. Buf Word 0 (LW0) Register to Buf Word 31 (LW7) Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 MOTOROLA Bluetooth Accelerator (BTA) 16-63...

  • Page 364: Table 16-49 Bit Buffer Registers Numbers And Addresses

    Register Register Register 0x00216080 0x002160B0 0x002160E0 0x00216084 0x002160B4 0x002160E4 0x00216088 0x002160B8 0x002160E8 0x0021608C 0x002160BC 0x002160EC 0x00216090 0x002160C0 0x002160F0 0x00216094 0x002160C4 0x002160F4 0x00216098 0x002160C8 0x002160F8 0x0021609C 0x002160CC 0x002160FC 0x002160A0 0x002160D0 0x002160A4 0x002160D4 0x002160A8 0x002160D8 0x002160AC 0x002160DC 16-64 MC9328MX1 Reference Manual MOTOROLA...

  • Page 365: Wake-up Registers, Wake-up 1 Register, Table 16-50 Wake-up 1 Register Description

    Reserved—These bits are reserved and should read 0. Bits 31–2 TIME Value for Wake-Up Timer 1—Sets wake-up timer 1 for low-power Recommend using Bits 1–0 operation. The timer is clocked by the 32 kHz clock. values greater than 1. MOTOROLA Bluetooth Accelerator (BTA) 16-65...

  • Page 366: Wake-up 2 Register, Table 16-51 Wake-up 2 Register Description

    2 for low-power operation. specified (WU_COUNT = WAKEUP_2). The timer is clocked by the 32 kHz clock. Writing 0x0000 to this register disables timed wake-up, and only an external event will wake up the BTA. 16-66 MC9328MX1 Reference Manual MOTOROLA...

  • Page 367: Wake-up Delta4 Register, Table 16-52 Wake-up Delta4 Register Description

    Reserved—These bits are reserved and should read 0. Bits 31–10 TIME Delta Value for Wake-Up Timer 4—Sets the wake-up timer delta value that is added to the Bits 9–0 WU_COUNT value after a wake-up event. MOTOROLA Bluetooth Accelerator (BTA) 16-67...

  • Page 368: Wake-up 4 Register, Table 16-53 Wake-up 4 Register Description

    Table 16-53. Wake-Up 4 Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 TIME Value for Wake-Up Timer 4—Contains the time value when the Bluetooth master clock was started. Bits 15–0 16-68 MC9328MX1 Reference Manual MOTOROLA...

  • Page 369: Wakeup Control Register, Table 16-54 Wakeup Control Register Description

    Wake-Up Counter Reset—Resets the wake-up counter in 0 = Do not reset the wake-up counter Bit 3 the wake up module. 1 = Reset the wake-up counter Reserved Reserved—These bits are reserved and should read 0. Bits 2–0 MOTOROLA Bluetooth Accelerator (BTA) 16-69...

  • Page 370: Wake-up Status Register, Table 16-55 Wake-up Status Register Description

    Bluetooth Clock—Indicates the status of the Bluetooth Clock 0 = BT clock running Bit 1 1 = BT clock stopped Power Down Enable—Indicates status of power down enable 0 = Power down disabled Bit 0 function. 1 = Power down enabled 16-70 MC9328MX1 Reference Manual MOTOROLA...

  • Page 371: Wake-up Count Register, Table 16-56 Wake-up Count Register Description

    Table 16-56. Wake-Up Count Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 COUNT Counter Value—Holds the count value used by the comparators in the wake-up units to trigger Bits 15–0 wake-up interrupts. MOTOROLA Bluetooth Accelerator (BTA) 16-71...

  • Page 372: System Register, Clock Control Register, Table 16-57 Clock Control Register Description

    Reserved—These bits are reserved and should read 0. Bits 3–2 BT1_CLK_IN_DIV BT1 Clock In Frequency Divider Select—Selects the frequency 00 = Idle Bits 1–0 division of the BT1 clock in. 01 = 16 10 = 24 11 = 32 16-72 MC9328MX1 Reference Manual MOTOROLA...

  • Page 373: Spi Registers, Spi Word0 Register, Table 16-58 Spi Word0 Register Description (mc13180)

    The start address is written to the SPI Read Address Register before reads are performed or to the SPI Write Address Register after writes are performed. MOTOROLA Bluetooth Accelerator (BTA) 16-73...

  • Page 374: Spi Word1 Register, Table 16-59 Spi Word0 Register Description (siliconwave)

    Table 16-60. SPI Word1 Register Description (MC13180) Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 WORD1 Word of Data—Contains word 1 of the data read from or written to the RF module Bits 15–0 16-74 MC9328MX1 Reference Manual MOTOROLA...

  • Page 375: Spi Word2 Register, Table 16-61 Spi Word1 Register Description (siliconwave)

    Word of Data—Contains word 2 of the data read from or written to the RF module. Bits 15–0 Table 16-63. SPI Word2 Register Description (SiliconWave) Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 MOTOROLA Bluetooth Accelerator (BTA) 16-75...

  • Page 376: Spi Word3 Register, Table 16-64 Spi Word3 Register Description (mc13180)

    Word of Data—Contains word 3 of the data read from or written to the RF module. Bits 15–0 Table 16-65. SPI Word3 Register Description (SiliconWave) Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 BYTE6 Byte 6—Contents vary according to the RF module used. Bits 15–8 16-76 MC9328MX1 Reference Manual MOTOROLA...

  • Page 377: Spi Write Address Register, Table 16-66 Spi Write Address Register Description (mc13180)

    Set to 0. Bit 7 ADDRESS Radio Register Address—Contains the address of the first radio register that the buffered SPI Bits 6–0 Word0 Register entries are written to. The address is automatically post-incremented in the radio register. MOTOROLA Bluetooth Accelerator (BTA) 16-77...

  • Page 378: Spi Read Address Register, Table 16-67 Spi Write Address Register Description (siliconwave)

    ADDRESS (SiliconWave) TYPE RESET 0x0000 Table 16-68. SPI Read Address Register Description (MC13180) Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 Don’t Care Don’t Care—Ignored by the BTA. Bits 15–8 16-78 MC9328MX1 Reference Manual MOTOROLA...

  • Page 379: Spi Control Register, Table 16-69 Spi Read Address Register Description (siliconwave)

    SPI clock. Reading address 0x00216138 returns the SPI Status Register (see section 16.5.10.8). The SPI Control Register bits are explained in Table 16-70. Addr SPI_CONTROL SPI Control Register 0x00216138 TYPE RESET 0x0000 BYTE_ONLY SPI_CLKINV SPI_CLKDIV3 SPI_CLKDIV2 SPI_CLKDIV1 SPI_MODE TYPE RESET 0x0000 MOTOROLA Bluetooth Accelerator (BTA) 16-79...

  • Page 380: Figure 16-11 Spi Clock Dividers Determine Duty Cycle Of Spi Clock

    SPI Mode Selection—Sets SPI mode according to the radio 011 = MC13180 Bits 2–0 used. 100 = SiliconWave All Other Settings Reserved SPI State SPI_EN SPI_CLK Figure 16-11. SPI Clock Dividers Determine Duty Cycle of SPI Clock 16-80 MC9328MX1 Reference Manual MOTOROLA...

  • Page 381: Spi Status Register, Frequency Hopping Registers, Table 16-71 Spi Status Register Description

    Reading address 0x00216140 returns the Hop Frequency Out Register (see section 16.5.11.6). The read-only Hop Frequency Out Register returns the partially computed hopping frequency channel based on the sequence written to the Hopping Frequency Registers. The Register bits are explained in Table 16-72 through Table 16-76. MOTOROLA Bluetooth Accelerator (BTA) 16-81...

  • Page 382: Hop 0 (frequency In) Register, Hop 1 (frequency In) Register

    CLK0 is written but ignored by the Bluetooth core as frequency. it is not required by the standard 16.5.11.2 Hop 1 (Frequency In) Register Addr HOP1 Hop 1 (Frequency In) Register 0x00216144 TYPE RESET 0x0000 CLK_HIGH TYPE RESET 0x0000 16-82 MC9328MX1 Reference Manual MOTOROLA...

  • Page 383: Hop 2 (frequency In) Register, Table 16-73 Hop 1 (frequency In) Register Description

    Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 LAPUAP_LOW Lower Part of the Combined LAP and 4 LSBs of UAP—Contains ADDR [15:0] of the LAP Bits 15–0 bits [15:0] of the LAP. MOTOROLA Bluetooth Accelerator (BTA) 16-83...

  • Page 384: Hop 3 (frequency In) Register, Hop 4 (frequency In) Register

    UAP—Contains bits [23:16] of the LAP and bits 3-0 of the UAP. and ADDR [3:0] of the UAP 16.5.11.5 Hop 4 (Frequency In) Register Addr HOP4 Hop 4 (Frequency In) Register 0x00216150 TYPE RESET 0x0000 STATE TYPE RESET 0x0000 16-84 MC9328MX1 Reference Manual MOTOROLA...

  • Page 385: Hop Frequency Out Register, Table 16-76 Hop 4 (frequency In) Register Description

    Hopping Frequency Registers have been Software is expected to complete the addition written. Software must complete the computation of of F (see the Bluetooth specifications) and the hop frequency channel. also the modulo operation. MOTOROLA Bluetooth Accelerator (BTA) 16-85...

  • Page 386: Interrupt Register, Interrupt Vector Register, Table 16-78 Interrupt Vector Register Description

    See Section 16.5.1, “Sequencer Registers.” Write 1 = EOH interrupt clear. SYSTICK SYSTICK Interrupt—Indicates whether a SYSTICK of the current clock 0 = No SYSTICK Bit 0 has occurred. Write to clear. interrupt 1 = SYSTICK interrupt 16-86 MC9328MX1 Reference Manual MOTOROLA...

  • Page 387: Joint Detect Registers, Synchronization Metric Register, Table 16-79 Synchronization Metric Register Description

    SYNC_METRIC TYPE RESET 0x0000 Table 16-79. Synchronization Metric Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–15 SYNC_METRIC Synchronization Metric—Indicates the peak value of the correlation energy. Bits 14–0 MOTOROLA Bluetooth Accelerator (BTA) 16-87...

  • Page 388: Synchronize Frequency Carrier Register, Bit Reverse Registers, Word Reverse Register

    16.5.14.1 Word Reverse Register The Word Reverse Register is written with the 16-bit word to be bit reversed. When read, the register gives the bit reversed word. The Word Reverse Register bits are explained in Table 16-81. 16-88 MC9328MX1 Reference Manual MOTOROLA...

  • Page 389: Byte Reverse Register, Table 16-81 Word Reverse Register Description

    The Byte Reverse Register (BYTE_REVERSE) is written with the byte to be bit reversed. On reading the register gives the bit reversed word. The Byte Reverse Register register bits are explained in Table 16-82. Addr BYTE_REVERSE Byte Reverse Register 0x0021617C TYPE RESET 0x0000 BYTE_REVERSED TYPE RESET 0x0000 MOTOROLA Bluetooth Accelerator (BTA) 16-89...

  • Page 390: Table 16-82 Byte Reverse Register Description

    Byte to be Bit Reversed—Receives the byte This register is written with the byte to be Bits 7–0 to be bit reversed. bit reversed. Byte Reversed—Receives the bit reversed When read, it gives the bit reversed byte. byte. 16-90 MC9328MX1 Reference Manual MOTOROLA...

  • Page 391: Mma Operation, Introduction, Memory Access

    ARM920T processor. LCDC access to the eSRAM has the highest priority, followed by ARM920T processor access, and finally MMA access. For this reason, data access latency of the MMA to the eSRAM can be as long as the LCDC data burst access. MOTOROLA Multimedia Accelerator (MMA) 17-1...

  • Page 392: Basic Mac Operation, Data Access, Figure 17-1 Mma Data Access

    The MMA resumes operation if there are no other eSRAM access requests pending. Circular buffer operation for the X registers is shown in Figure 17-2 on page 17-3. 17-2 MC9328MX1 Reference Manual MOTOROLA...

  • Page 393: Cache, Figure 17-2 Circular Buffering Operation

    1 to the CACHE CLR bit. This action also registers the base address of the 2K boundary as the valid cache block address. The user must program the MMA_MAC_XBASE register and the MMA_MAC_XINDEX register before clearing the cache. MOTOROLA Multimedia Accelerator (MMA) 17-3...

  • Page 394: Dct/idct, Figure 17-3 Dct/idct Architecture, Figure 17-4 Data Formatting For Dct And Idct

    DCT/iDCT is performed automatically. When the process is complete, an interrupt is generated and the DCT ENA bit is cleared. In this way, a DCT/iDCT can be run for an entire frame of data. 17-4 MC9328MX1 Reference Manual MOTOROLA...

  • Page 395: Table 17-1 Mma Module Register Memory Map, Programming Model

    MMA MAC Y Index Register MMA_MAC_YINDEX 0x00222304 MMA MAC Y Length Register MMA_MAC_YLENGTH 0x00222308 MMA MAC Y Modify Register MMA_MAC_YMODIFY 0x0022230C MMA MAC Y Increment Register MMA_MAC_YINCR 0x00222310 MMA MAC Y Count Register MMA_MAC_YCOUNT 0x00222314 MMA DCT/iDCT Registers MOTOROLA Multimedia Accelerator (MMA) 17-5...

  • Page 396: Mma Mac Control Registers, Mma Mac Module Register, Table 17-2 Mma Mac Module Register Description

    0x0000 Table 17-2. MMA MAC Module Register Description Name Description Settings Software Reset for the MAC—indicates whether the reset sequence 0 = Reset is complete Bit 31 is complete. 1 = Reset is in progress 17-6 MC9328MX1 Reference Manual MOTOROLA...

  • Page 397: Mma Mac Control Register, Table 17-3 Mma Mac Control Register Description

    MMA_MAC_XINDEX register in the XDAC module is incremented incremented by the value in the MMA_MAC_XINCR 1 = MMA_MAC_XINDEX register register for every (MMA_MAC_XCOUNT + 1) iteration. is incremented X INDEX INCR is used with X INDEX LOAD. MOTOROLA Multimedia Accelerator (MMA) 17-7...

  • Page 398

    1 = Y operand sign is alternated Y SIGN INI Y Operand Initial Sign—Determines whether the Y 0 = +(y) Bit 17 operand initial sign of the operation with y. 1 = -(y) 17-8 MC9328MX1 Reference Manual MOTOROLA...

  • Page 399: Mma Mac Multiply Counter Register, Table 17-4 Mma Mac Multiply Counter Register Description

    Reserved—These bits are reserved and should read 0. Bits 31–16 MULT COUNTER Multiply Counter—Determines the number of multiply operations that the MAC module Bits 15–0 performs. For proper operation, this value must be an integer multiple of the (MMA_MAC_ACCU + 1) value. MOTOROLA Multimedia Accelerator (MMA) 17-9...

  • Page 400: Mma Mac Accumulate Counter Register, Mma Mac Interrupt Register

    1 (0x0003 for four accumulate operations). 17.3.1.5 MMA MAC Interrupt Register Addr MMA_MAC_INTR MMA MAC Interrupt Register 0x00222010 TYPE RESET 0x0000 FIFO FIFO FIFO ERROR EMPT HALF FULL TYPE RESET 0x0004 17-10 MC9328MX1 Reference Manual MOTOROLA...

  • Page 401: Mma Mac Interrupt Mask Register, Table 17-6 Mma Mac Interrupt Register Description

    OP ERROR Mask—Masks the OP ERROR Interrupt. 0 = Mask on/enable interrupt Bit 4 1 = Mask off/disable interrupt. OP END Operation End Interrupt Mask—Masks the OP END interrupt. 0 = Mask on/enable interrupt Bit 3 1 = Mask off/disable interrupt MOTOROLA Multimedia Accelerator (MMA) 17-11...

  • Page 402: Mma Mac Fifo Register, Table 17-8 Mma Mac Fifo Register Description

    Addr MMA_MAC_FIFO MMA MAC FIFO Register 0x00222018 FIFO REGISTER TYPE RESET 0x0000 FIFO REGISTER TYPE RESET 0x0000 Table 17-8. MMA MAC FIFO Register Description Name Description FIFO REGISTER FIFO Read Register—Returns FIFO output. Bits 31–0 17-12 MC9328MX1 Reference Manual MOTOROLA...

  • Page 403: Mma Mac Fifo Status Register, Table 17-9 Mma Mac Fifo Status Register Description

    Bit 2 interrupt. FIFO HALF FIFO Half Full Status—Indicates the status of the FIFO HALF See description Bit 1 interrupt. FIFO FULL FIFO Full Status—Indicates the status of the FIFO FULL interrupt. See description Bit 0 MOTOROLA Multimedia Accelerator (MMA) 17-13...

  • Page 404: Mma Mac Burst Count Register, Mma Mac Bit Select Register

    This feature ensures that the MMA does not hold the memory bus for too long. 17.3.1.10 MMA MAC Bit Select Register Addr MMA_MAC_BITSEL MMA MAC Bit Select Register 0x00222024 TYPE RESET 0x0000 BITSEL TYPE RESET 0x0000 17-14 MC9328MX1 Reference Manual MOTOROLA...

  • Page 405: Mma Mac Xy Count Accumulate Register, Mma Mac X Register Control Registers

    The initial access by the XDAC is a cache miss, so the operand is fetched from memory and stored in the cache. Subsequent accesses to the same location cause cache hits, so the data is loaded from the cache instead of from memory. MOTOROLA Multimedia Accelerator (MMA) 17-15...

  • Page 406: Mma Mac X Base Address Register, Mma Mac X Index Register

    MMA_MAC_XINDEX MMA MAC X Index Register 0x00222204 TYPE RESET 0x0000 XINDEX TYPE RESET 0x0000 Table 17-13. MMA MAC X Index Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 17-16 MC9328MX1 Reference Manual MOTOROLA...

  • Page 407: Mma Mac X Length Register, Table 17-14 Mma Mac X Length Register Description

    Writing 0 to this register will disable the wrapping of address. Note: Note: If the current Address_Index is 12 and the LENGTH is 16, MMA_MAC_XMODIFY is 8, then the next Address_Index will be (12+8)% 16 == 4. The physical address is 4 + MMA_MAC_XBASE. MOTOROLA Multimedia Accelerator (MMA) 17-17...

  • Page 408: Mma Mac X Modify Register, Mma Mac X Increment Register

    X Increment—Determines the size of the increment to the X Address Index after each iteration. Bits 15–0 17.3.3.5 MMA MAC X Increment Register Addr MMA_MAC_XINCR MMA MAC X Increment Register 0x00222210 TYPE RESET 0x0000 XINCR TYPE RESET 0x0000 17-18 MC9328MX1 Reference Manual MOTOROLA...

  • Page 409: Mma Mac X Count Register, Mma Mac Y Register Control Registers

    17.3.4 MMA MAC Y Register Control Registers There are six registers that reside in the Y operand Data Access Controller (YDAC). The YDAC does not have a cache, so it always fetches data from memory. MOTOROLA Multimedia Accelerator (MMA) 17-19...

  • Page 410: Mma Mac Y Base Address Register, Mma Mac Y Index Register

    MMA_MAC_YINDEX MMA MAC Y Index Register 0x00222304 TYPE RESET 0x0000 YINDEX TYPE RESET 0x0000 Table 17-19. MMA MAC Y Index Register Description Name Description Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 17-20 MC9328MX1 Reference Manual MOTOROLA...

  • Page 411: Mma Mac Y Length Register, Table 17-20 Mma Mac Y Length Register Description

    Writing 0 to this register will disable the wrapping of address. Note: Note: If the current Address_Index is 12 and the LENGTH is 16, MMA_MAC_YMODIFY is 8, then the next Address_Index will be (12+8)% 16 == 4. The physical address is 4 + MMA_MAC_YBASE. MOTOROLA Multimedia Accelerator (MMA) 17-21...

  • Page 412: Mma Mac Y Modify Register, Mma Mac Y Increment Register

    Y Increment—Determines the size of the increment to the Y Address Index after each iteration. Bits 15–0 17.3.4.5 MMA MAC Y Increment Register Addr MMA_MAC_YINCR MMA MAC Y Increment Register 0x00222310 TYPE RESET 0x0000 YINCR TYPE RESET 0x0000 17-22 MC9328MX1 Reference Manual MOTOROLA...

  • Page 413: Mma Mac Y Count Register, Table 17-22 Mma Mac Y Increment Register Description

    Y INDEX LOAD bit is set) • increment MMA_MAC_YINDEX by the value in MMA_MAC_YINCR (when the Y INDEX INCR bit is set). The value written to this register is the actual value minus 1 (0x0003 for four iterations). MOTOROLA Multimedia Accelerator (MMA) 17-23...

  • Page 414: Mma Dct/idct Registers, Dct/idct Control Register, Table 17-24 Dct/idct Control Register Description

    0 = No effect Bit 5 1 = Resets DCT module DCTBYPASS DCT Bypass—Enables DCT/iDCT input data to be 0 = Perform transform Bit 4 bypassed to the output without being transformed. 1 = Bypass 17-24 MC9328MX1 Reference Manual MOTOROLA...

  • Page 415: Dct/idct Version Register, Table 17-25 Dct/idct Version Register Description

    DCT/iDCT Version Register 0x00222404 VERSION NUMBER TYPE RESET 0x0000 VERSION NUMBER TYPE RESET 0x0000 Table 17-25. DCT/iDCT Version Register Description Name Description VERSION NUMBER Version Number—Contains the version number of the DCT/iDCT block. Bits 31–0 MOTOROLA Multimedia Accelerator (MMA) 17-25...

  • Page 416: Dct/idct Irq Enable Register, Table 17-26 Dct/idct Irq Enable Register Description

    1 = Interrupt enabled DCTCOMP DCT Complete—Enables/Disables interrupt generation when the DCT 0 = Interrupt disabled × Bit 0 block completes a set of 8 8 transforms. 1 = Interrupt enabled 17-26 MC9328MX1 Reference Manual MOTOROLA...

  • Page 417: Dct/idct Irq Status Register, Table 17-27 Dct/idct Irq Status Register Description

    Write a 1 to clear. occurred 1 =Data In interrupt has not occurred DCTCOMP Transform Complete—Indicates whether a transform has 0 = Transform is not complete Bit 0 completed. Write a 1 to clear. 1 = Transform is complete MOTOROLA Multimedia Accelerator (MMA) 17-27...

  • Page 418: Dct/idct Source Data Address, Dct/idct Destination Data Address

    Addr MMA_DCTDESDATA Address 0x00222414 DCT_DES_ADDR TYPE RESET 0x0000 DCT_DES_ADDR TYPE RESET 0x0000 Table 17-29. DCT/iDCT Destination Data Address Register Description Name Description DCT_DES_ADDR DCT Destination Address—Determines the destination address for the transformed data. Bits 31–0 17-28 MC9328MX1 Reference Manual MOTOROLA...

  • Page 419: Dct/idct X-offset Address, Dct/idct Y-offset Address, Table 17-30 Dct/idct X-offset Address Register Description

    [MMA_DCTSRCDATA or MMA_DCTDESDATA] + (X-OFFSET × N) where N = 1, …(X-COUNT – 1) along the X-direction. 17.3.5.8 DCT/iDCT Y-Offset Address Addr MMA_DCTYOFF DCT/iDCT Y-Offset Address 0x0022241C TYPE RESET 0x0000 Y-OFFSET TYPE RESET 0x0000 MOTOROLA Multimedia Accelerator (MMA) 17-29...

  • Page 420: Dct/idct Xy Count, Table 17-31 Dct/idct Y-offset Address Register Description

    Y Count—Controls the number of blocks to be transformed in the Y direction. Bits 14–8 Reserved Reserved—This bit is reserved and should read 0. Bit 7 X-COUNT X Count—Controls the number of blocks to be transformed in the X direction. Bits 6–0 17-30 MC9328MX1 Reference Manual MOTOROLA...

  • Page 421: Dct/idct Skip Address, Table 17-33 Dct/idct Skip Address Register Description

    Reserved Reserved—These bits are reserved and should read 0. Bits 31–16 SKIP_ADDR SKIP_ADDR—Determines the number of bytes to skip in the X direction when accessing Bits 15–0 each successive row in a block of data. MOTOROLA Multimedia Accelerator (MMA) 17-31...

  • Page 422: Dct/idct Data Fifo, Table 17-34 Dct/idct Data Fifo Register Description

    Data—Stores input data to be transformed and the outputs the data after transformation. Writing to Bits 31–0 this register stores input data in the FIFO. Reading this register retrieves the results of the transformation from the FIFO. The FIFO is 32 × 32–bits. 17-32 MC9328MX1 Reference Manual MOTOROLA...

  • Page 423: Spi Block Diagram, Table 18-1 Spi 1 And Spi 2 Signal Multiplexing

    The block diagram shown in Figure 18-1 on page 18-2 is the same for each SPI module, except that the SPI 2 module does not support the SPI_RDY control signal function. MOTOROLA Serial Peripheral Interface Modules (SPI 1 and SPI 2) 18-1...

  • Page 424: Phase And Polarity Configurations, Operation, Figure 18-1 Spi Module Block Diagram

    In Phase 1 operation (PHA=1) and SCLK Polarity active high (POL=1), output data changes on falling edges of the SCLK signal and input data is shifted in on rising edges. The MSB is output when the CPU loads the transmitted data. 18-2 MC9328MX1 Reference Manual MOTOROLA...

  • Page 425: Signals, Pin Configuration For Spi 1 And Spi 2, Figure 18-2 Spi Generic Timing

    The user must ensure that the data direction bits in the GPIO are set to the correct direction for proper operation. See Section 32.5.1, “Data Direction Registers,” on page 32-9 for details. MOTOROLA Serial Peripheral Interface Modules (SPI 1 and SPI 2) 18-3...

  • Page 426: Table 18-2 Spi Pin Configuration

    SPI 1 pins must only be configured if SPI 1 is being used. SPI 2 pins must only be configured if SPI 2 is being used. Only one of the two pins must be set-up for the SPI 2 signal. 18-4 MC9328MX1 Reference Manual MOTOROLA...

  • Page 427: Table 18-3 Spi Module Register Memory Map, Programming Model

    0x0021900C SPI 2 Test Register TESTREG2 0x00219010 SPI 2 Sample Period Control Register PERIODREG2 0x00219014 SPI 2 DMA Control Register DMAREG2 0x00219018 SPI 2 Soft Reset Register RESETREG2 0x0021901C MOTOROLA Serial Peripheral Interface Modules (SPI 1 and SPI 2) 18-5...

  • Page 428: Receive (rx) Data Registers

    Bits 31–16 DATA DATA—Holds the top word of data received into the FIFO. Not valid when the Receive Data Ready Bits 15–0 (RR) bit in the corresponding Interrupt Control/Status Register (INTREG1 or INTREG2) is cleared. 18-6 MC9328MX1 Reference Manual MOTOROLA...

  • Page 429: Transmit (tx) Data Registers

    Bits 9-0 are shifted out and bits 15-10 are ignored. When the SPI module is operating in slave mode, ‘0’s are shifted out when the FIFO is not full. MOTOROLA Serial Peripheral Interface Modules (SPI 1 and SPI 2)

  • Page 430: Control Registers, Table 18-6 Spi 1 Control Register And Spi 2 Control Register Description

    SPI_RDY control signal function, DRCTL must be written with 00 in CONTROLREG2. MODE SPI Mode Select—Selects the mode for the SPI 1 0 = Slave mode Bit 10 module. In CONTROLREG2, MODE is set by the 1 = Master mode hardware. 18-8 MC9328MX1 Reference Manual MOTOROLA...

  • Page 431

    Controls the number of bits in a receive data word (in slave mode and when the SSCTL bit is 0). When the SSCTL bit is 1, this field is “don’t care.” MOTOROLA Serial Peripheral Interface Modules (SPI 1 and SPI 2) 18-9...

  • Page 432: Interrupt Control/status Registers

    TXFIFO Half Interrupt Enable—Enables/Disables the 0 = Disable interrupt Bit 9 TXFIFO Half-Empty Interrupt. 1 = Enable interrupt TEEN TXFIFO Empty Interrupt Enable—Enables/Disables the 0 = Disable interrupt Bit 8 TXFIFO Empty Interrupt. 1 = Enable interrupt 18-10 MC9328MX1 Reference Manual MOTOROLA...

  • Page 433: And Spi 2 Interrupt Control/status Register Description

    1 = The TXFIFO is empty, however data shifting may still be on-going. To be sure no data transaction is on-going, check the XCH bit(s) in the Control Register(s). MOTOROLA Serial Peripheral Interface Modules (SPI 1 and SPI 2) 18-11...

  • Page 434: Test Registers, Table 18-8 Spi 1 Test Register And Spi 2 Test Register Description

    0100 = 4 data words in RXFIFO 0101 = 5 data words in RXFIFO 0110 = 6 data words in RXFIFO 0111 = 7 data words in RXFIFO 1000 = 8 data words in RXFIFO 18-12 MC9328MX1 Reference Manual MOTOROLA...

  • Page 435: Sample Period Control Registers

    Wait—Determines the number of clocks inserted between data 0x0000 = 0 clock Bits 14–0 transactions (when operating in master mode). 0x0001 = 1 clock 0x0002 = 2 clocks … 0x7FFF = 32768 clocks MOTOROLA Serial Peripheral Interface Modules (SPI 1 and SPI 2) 18-13...

  • Page 436: Dma Control Registers, And Spi 2 Dma Control Register Description

    Control Registers. RFDMA RXFIFO Full Status—Indicates when the 0 = There are less than 8 data words in the RXFIFO Bit 5 receive FIFO is full. 1 = There are 8 data words in the RXFIFO 18-14 MC9328MX1 Reference Manual MOTOROLA...

  • Page 437: Soft Reset Registers

    Name Description Settings Reserved Reserved—These bits are reserved and should read 0. Bits 31–1 START Start—Executes soft reset. 0 = No soft reset Bit 0 1 = Soft reset MOTOROLA Serial Peripheral Interface Modules (SPI 1 and SPI 2) 18-15...

  • Page 438

    Serial Peripheral Interface Modules (SPI 1 and SPI 2) 18-16 MC9328MX1 Reference Manual MOTOROLA...

  • Page 439: Table 19-1 Supported Panel Characteristics, Introduction, Features

    16, 256 12, 16 12, 16 4096, 64K • Standard panel interface for common LCD drivers • Panel interface of 16-, 12-, 8-, 4-, 2-, and 1-bit-wide LCD panel data bus for monochrome or color panels MOTOROLA LCD Controller 19-1...

  • Page 440: Lcdc Operation, Lcd Screen Format, Figure 19-1 Lcdc Block Diagram

    19.3 LCDC Operation 19.3.1 LCD Screen Format The number of pixels forming the screen width and screen height of the LCD panel are software programmable. Figure 19-2 shows the relationship between the screen size and memory window. 19-2 MC9328MX1 Reference Manual MOTOROLA...

  • Page 441: Panning, Display Data Mapping, Figure 19-2 Lcd Screen Format

    The updates take effect on the next frame. 19.3.3 Display Data Mapping The LCDC supports 1/2/4 bpp in monochrome mode and 4/8/12/16 bpp in color mode. System memory data mapping in 2/4/8/12/16 bpp modes is shown in Figure 19-4 and in Figure 19-5. MOTOROLA LCD Controller 19-3...

  • Page 442: Figure 19-3 Pixel Location On Display Screen

    In 12 bpp mode, 16 bits of memory are used for each set of 12 bits, leaving 4 bits unused. In 16 bpp mode, all 16 bits are used. Refer to Figure 19-5 and Table 19-7 LCD Screen Figure 19-3. Pixel Location on Display Screen 19-4 MC9328MX1 Reference Manual MOTOROLA...

  • Page 443: Figure 19-4 Display Data Mapping, 1/2/4/8 Bpp Modes

    Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P0 = Red0Green0Blue0 P1 = Red1Green1Blue1 Figure 19-4. Display Data Mapping, 1/2/4/8 bpp Modes MOTOROLA LCD Controller 19-5...

  • Page 444: Table 19-2 Display Mapping In 12 Bpp, Cstn Panel, Little Endian

    Green1 [2] Green1 [1] Green1 [0] Blue1 [4] Blue1 [3] Blue1 [2] Blue1 [1] Blue1 [0] Table 19-3. Display Mapping in 12 bpp, CSTN Panel, Little Endian Byte Address Bit-to-Pixel Mapping – – – – – – – – PO = RGBo P1= RGB 19-6 MC9328MX1 Reference Manual MOTOROLA...

  • Page 445: Black-and-white Operation, Gray-scale Operation, Figure 19-5 Display Data Mapping, 16 Bpp Mode

    A logarithmic scale such as 0, 1/4, 1/2 and 1 might be more pleasing than a linearly spaced scale such as 0, 5/16, 11/16 and 1 for certain graphics. Figure 19-6 illustrates gray-scale pixel generation. The flexible mapping scheme allows the user to optimize the visual effect for a specific panel or application. MOTOROLA LCD Controller 19-7...

  • Page 446: Color Generation, Figure 19-6 Gray-scale Pixel Generation

    For active matrix displays, the 16-bit RGB code from the mapping RAM is output to the panel. For passive color display, the maximum color depth is 12-bit and 16-bit color is not supported. Figure 19-7 and Figure 19-8 on page 19-9 illustrate passive matrix and active matrix color pixel generation. 19-8 MC9328MX1 Reference Manual MOTOROLA...

  • Page 447: Figure 19-7 Passive Matrix Color Pixel Generation, Figure 19-8 Active Matrix Color Pixel Generation

    0 1 0 1 0 1 1 0 1 1 1 0 1 Color Inside LCDC 256 rows 1 0 0 1 1 1 1 0 0 To Panel Figure 19-8. Active Matrix Color Pixel Generation MOTOROLA LCD Controller 19-9...

  • Page 448: Frame Rate Modulation Control (frc), Panel Interface Signals And Timing, Table 19-5 Gray Palette Density

    Note: Overbars indicate repeating decimal numbers. 19.3.8 Panel Interface Signals and Timing The LCDC continuously provides pixel data to the LCD panel via the LCD panel interface. Panel interface signals are illustrated in Figure 19-9. 19-10 MC9328MX1 Reference Manual MOTOROLA...

  • Page 449: Pin Configuration For Lcdc, Figure 19-9 Lcdc Interface Signals, Table 19-6 Pin Configuration

    2. Clear bit 11 of Port D General Purpose Register (GPR_D) SPL_SPR Primary function of 1. Clear bit 10 of Port D GPIO In Use Register (GIUS_D) GPIO Port D [10] 2. Clear bit 10 of Port D General Purpose Register (GPR_D) MOTOROLA LCD Controller 19-11...

  • Page 450: Passive Matrix Panel Interface Signals

    [0,236] [0,m-8] [0,m-4] [0,1] [0,5] [0,9] [0,233] [0,237] [0,m-7] [0,m-3] [0,2] [0,6] [0,10] [0,234] [0,238] [0,m-6] [0,m-2] [0,3] [0,7] [0,11] [0,235] [0,239] [0,m-5] [0,m-1] Figure 19-10. LCDC Interface Timing for 4-bit Data Width Gray-Scale Panels 19-12 MC9328MX1 Reference Manual MOTOROLA...

  • Page 451: Passive Panel Interface Timing

    H_WIDTH (horizontal sync pulse width) defines the width of the FLM pulse, and H_WIDTH must be at least 1. • H_WAIT_2 defines the delay from the end of LP to the beginning of data output. NOTE: All parameters are defined in unit of pixel clock period, unless stated otherwise. MOTOROLA LCD Controller 19-13...

  • Page 452: Bpp Mode Color Stn Panel, Active Matrix Panel Interface Signals

    1. LSCLK latches data into the panel on its negative edge (when positive polarity is selected). In active mode, LSCLK runs continuously. 2. HSYNC causes the panel to start a new line. 3. VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse. 19-14 MC9328MX1 Reference Manual MOTOROLA...

  • Page 453: Table 19-7 Tft Color Channel Assignments

    The actual TFT color channel assignments are shown in Table 19-7. In 4 bpp and 8 bpp, bits LD11, LD6, LD5 and LD0 are fixed at 0. Table 19-7. TFT Color Channel Assignments – – – – 4 bpp – – – – 8 bpp – – – – 12 bpp 16 bpp MOTOROLA LCD Controller 19-15...

  • Page 454: Active Panel Interface Timing, Figure 19-14 Lcdc Interface Timing For Active Matrix Color Panels

    H_WAIT_1 defines the delay from end of OE to the beginning of the HSYNC pulse. • XMAX defines the (total) number of pixels per line. NOTE: All parameters are defined in pixel periods, not LSCLK periods. 19-16 MC9328MX1 Reference Manual MOTOROLA...

  • Page 455: Figure 19-15 Horizontal Sync Pulse Timing In Tft Mode

    (time = one line period) after VSYNC. The HSYNC pulse is output during the V_WAIT_2 delay. End of frame V_WIDTH Beginning of frame (lines) YMAX VSYNC HSYNC V_WAIT_1 V_WAIT_2 Figure 19-16. Vertical Sync Pulse Timing TFT Mode MOTOROLA LCD Controller 19-17...

  • Page 456: Table 19-8 Lcdc Register Memory Map, Programming Model

    Figure 19-17 on page 19-19 provides a quick overview of the fields of all the registers. There are intentional gaps between the addresses for the read-write register section and the status register, and between the status register and the mapping RAM. 19-18 MC9328MX1 Reference Manual MOTOROLA...

  • Page 457: Figure 19-17 Register Memory Mapping Summary

    DMACR 0x00205030 DMA Trigger Mark - TM RMCR 0x00205034 LCDC SELF _REF LCDICR 0x00205038 LCDISR 0x00205040 _ERR _RES 0x00205800 First RAM Location(R [3:0], G [3:0], B [3:0]) 0x00205BFC Last RAM Location(R [3:0], G [3:0], B [3:0]) MOTOROLA LCD Controller 19-19...

  • Page 458: Screen Start Address Register, Size Register, Table 19-9 Screen Start Address Register Description

    Reserved—These bits are reserved and should read 0. Bits 1–0 19.4.2 Size Register The Size Register defines the height and width of the LCD screen. Addr SIZE Size Register 0x00205004 XMAX TYPE RESET 0x0000 YMAX TYPE RESET 0x0000 19-20 MC9328MX1 Reference Manual MOTOROLA...

  • Page 459: Virtual Page Width Register, Table 19-11 Virtual Page Width Register Description

    Virtual Page Width—Defines the virtual page width of the LCD panel. The VPW bits represent the Bits 9–0 number of 32-bit words required to hold the data for one virtual line. VPW is used in calculating the starting address representing the beginning of each displayed line. MOTOROLA LCD Controller 19-21...

  • Page 460: Panel Configuration Register, Table 19-12 Panel Configuration Register Description

    011 = 8 bpp 100 = 12 bpp/16 bpp (16 bits of memory used) 11x = reserved 1x1 = reserved PIXPOL Pixel Polarity—Sets the polarity of the pixels. 0 = Active high Bit 24 1 = Active low 19-22 MC9328MX1 Reference Manual MOTOROLA...

  • Page 461

    When PCD = O, pixel clock frequency is equal number of pixels in an output vector. to LCDC_CLK frequency. For passive matrix color panels (COLOR=1, TFT=0, PBSIZ=11) PCD must be greater than or equal to 2. MOTOROLA LCD Controller 19-23...

  • Page 462: Horizontal Configuration Register, Table 19-13 Horizontal Configuration Register Description

    Wait Between HSYNC and Start of Next Line—Specifies the number of pixel clk periods Bits 7–0 between the end of HSYNC and the beginning of the first data of next line. Total delay time equals (H_WAIT_2 + 3). 19-24 MC9328MX1 Reference Manual MOTOROLA...

  • Page 463: Vertical Configuration Register, Table 19-14 Vertical Configuration Register Description

    OE pulse of the first line in active (TFT=1) mode. The actual delay is V_WAIT_2 ) lines. Set this field to zero for passive non-color mode. The minimum value of this field is 0x01. MOTOROLA LCD Controller 19-25...

  • Page 464: Panning Offset Register, Table 19-15 Panning Offset Register Description

    Effective # of Bits to the left before processing. POS is Bits Per Pixel Panned on Image read by the LCDC once at the beginning of each frame. 19-26 MC9328MX1 Reference Manual MOTOROLA...