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Programming the BCD bits to various values (see Table 11-5, "Chip Select Control Registers
Description") affects two signals on the external bus, LBA (load burst address) and BCLK. The LBA
signal is asserted immediately and remains asserted until the first falling edge of the BCLK signal. The
BCLK signal runs with a 50% duty cycle until a non-sequential internal request is received or an external
ECB signal is recognized.
When programming these bits, ensure that the WSC and DOL fields are coordinated to provide the desired
external bus waveforms. For example, when the BCD bits are programmed to 01, the DOL bits must be
programmed to 0001, 0011, 0101, ... . When the BCD bits are programmed to 10, the DOL must be
programmed to 0010, 0101, 1000, ... .
The BCM bit in the EIM configuration register has priority over the BCD bits. When BCM = 1, the BCLK
runs at maximum frequency.
11.5.5 Burst Clock Start
To allow greater flexibility in achieving the minimum number of wait states on bursted accesses, the user
can determine when they want the BCLK to start toggling. This allows the BCLK to be skewed from the
point of data capture on the system clock by any number of system clock phases. Use caution when setting
these bits in conjunction with the BCD, WSC, and DOL bits. See the external timing diagrams for some
examples of how to use the BCS, BCD, WSC, and DOL bits together.
11.5.6 Page Mode Emulation
Setting the PME bit causes the EIM to perform bursted accesses by emulating page mode operation. The
LBA signal remains asserted for the entire access, the burst clock does not send a signal, and the external
address asserts for each access made. The initial access timing is dictated by the WSC bits and the page
mode access timing is dictated by the DOL bits.
The EIM can take advantage of improved page timing for sequential accesses only. Accesses that are on
the page, however are not sequential in nature, have their timing dictated by the WSC bits. The page size
can be set via the PSZ bits to 4, 8, 16, or 32 words (the word size is determined by the data width of the
external memory, such as the DSZ bits).
11.5.7 Error Conditions
The following conditions cause an error condition to be asserted to the ARM920T processor:
•
Access to a disabled chip select (access to a mapped chip select address space where the CSEN bit
in the corresponding chip select control register is clear)
•
Write access to a write-protected chip select address space (the WP bit in the corresponding chip
select control register is set)
•
User access to a supervisor-protected chip select address space (the SP bit in the corresponding chip
select control register is set)
•
User read or write access to a chip select control register or the EIM configuration register
•
Byte or halfword access to a chip select control register or the EIM configuration register
MOTOROLA
External Interface Module (EIM)
EIM Functionality
11-9
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