Table 29-7 I2Sr Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Integrated portable system processor
Table of Contents

Advertisement

2
I
C Module
2
29.6.4 I
C Status Register
2
The I
C Status Register (I2SR) indicates transaction direction and status.
I2SR
BIT
31
30
29
TYPE
r
r
r
0
0
0
RESET
BIT
15
14
13
TYPE
r
r
r
0
0
0
RESET
Name
Reserved
Reserved—These bits are reserved and should read 0.
Bits 31–8
ICF
Data Transfer—Indicates data transfer condition. ICF is
Bit 7
cleared while one byte of data is transferred.
2
IAAS
I
C Addressed As a Slave—Indicates that the device
Bit 6
slave address matches the address sent on the data line.
2
When the I
C Enable (IIEN) bit in the I2CR Register is set,
an interrupt is generated to the ARM9 core when this
match occurs. The ARM9 core must check the Slave
Read/Write (SRW) bit and set the Transmit/Receive Mode
Select (MTX) bit of the I2CR Register accordingly. Writing
to the I2CR Register clears this bit.
2
IBB
I
C Bus Busy—Indicates the status of the bus. When a
Bit 5
STOP signal is detected, IBB is cleared, and when a
START signal is detected, IBB is set.
IAL
Arbitration Lost—Indicates that this device will not operate as bus master. IAL cleared by writing 0 to
Bit 4
it, and is set by the hardware in the following circumstances:
SDA samples low when the master drives high during an address or data-transmit cycle
SDA samples low when the master drives high during the acknowledge bit of a data-receive
cycle
A START is attempted when the bus is busy
A repeated START is requested in slave mode
A STOP condition is detected when the master did not request it
29-12
2
I
C Status Register
28
27
26
25
r
r
r
r
0
0
0
0
12
11
10
9
r
r
r
r
0
0
0
0
Table 29-7. I2SR Register Description
Description
MC9328MX1 Reference Manual
24
23
22
21
20
r
r
r
r
r
0
0
0
0
0
0x0000
8
7
6
5
4
ICF
IAAS
IBB
IAL
r
r
r
r
rw
0
1
0
0
0
0x0081
0 = Transfer in progress
1 = Transfer complete (set at the falling
edge of the ninth clock of a byte
transfer)
0 = Not addressed
1 = Addressed as a slave (set when the
MC9328MX1 slave address in the
IADR Register matches the calling
address)
0 = Bus is idle
1 = Bus is busy
Addr
0x0021700C
19
18
17
16
r
r
r
r
0
0
0
0
3
2
1
0
SRW
IIF
RXAK
r
r
rw
r
0
0
0
1
Settings
MOTOROLA

Advertisement

Table of Contents
loading

Table of Contents