Uart Receiver Registers - Motorola DragonBall MC9328MX1 Reference Manual

Universal Asynchronous Receiver/Transmitters (UART) Modules

27.7.1 UART Receiver Registers

The read-only UART Receiver Registers contain the received character and its status. After reset, when the
receiver enable bit is set (RXEN = 1), these registers contain random data and the CHARRDY bit is 0 until
the first character is received. The URXDn_1 and URXDn_2 registers are each mapped to 16 word-length
addresses to support the LDM instruction.
URXDn_1
URXDn_2
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
CHAR OVR
ERR
RDY RUN
TYPE r r r
0 0 0
RESET
=
Note: n (0 through 15)
Table 27-12. UART1 Receiver Register n and UART2 Receiver Register n Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
CHARRDY Character Ready—Indicates an invalid read when the
Bit 15 RxFIFO is empty and the software attempts to read the
previously read data.
ERR Error Detect—Indicates whether the character present in
Bit 14 the RX_DATA field has an error (OVRRUN, FRMERR,
BRK or PRERR) status. The ERR bit is updated and valid
for each received character.
27-22
UART1 Receiver Register n
UART2 Receiver Register n
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
FRM PR
BRK
ERR ERR
r r r r
0 0 0 0
Description
MC9328MX1 Reference Manual
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
RX_DATA
r r r r r
0 ? ? ? ?
0x0000
0 = The character in the RX_DATA
field and its associated flags
are invalid.
1 = The character in the RX_DATA
field and its associated flags
are valid and ready to read
0 = An error status was detected
1 = No error status was detected
Addr
0x00206000+4*n
0x00207000+4*n
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
r r r r
? ? ? ?
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