Motorola DragonBall MC9328MX1 Reference Manual page 762

Universal Asynchronous Receiver/Transmitters (UART) Modules
Table 27-14. UART1 Control Register 1 and UART2 Control Register 1 Description (Continued)
Name
ICD Idle Condition Detect—Controls the number of frames
Bits 11–10 RXD is allowed to be idle before an idle condition is
reported.
RRDYEN Receiver Ready Interrupt Enable—Enables/Disables
Bit 9 the RRDY interrupt when the RxFIFO contains data. The
fill level in the RXFIFO at which an interrupt is generated
is controlled by the RXTL bits. When RRDYEN is
negated, the receiver ready interrupt is disabled.
RDMAEN Receive Ready DMA Enable—Enables/Disables the
Bit 8 receive DMA request UART_RX_DMAREQ when the
receiver has data in the RxFIFO. The fill level in the
RxFIFO at which a DMA request is generated is
controlled by the RXFL bits. When negated, the receive
DMA request is disabled.
IREN Infrared Interface Enable—Enables/Disables the IR
Bit 7 interface. See the IR interface description in Section 27.6
for more information.
TXMPTYEN Transmitter Empty Interrupt Enable—Enables/Disables
Bit 6 the transmitter FIFO empty (TXFE) interrupt.
UART_MINT_TX. When negated, the TXFE interrupt is
disabled
RTSDEN RTS Delta Interrupt Enable—Enables/Disables the
Bit 5 RTSD interrupt. The current status of the UARTx_RTS
pin is read in the RTSS bit.
SNDBRK Send BREAK—Forces the transmitter to send a BREAK
Bit 4 character. The transmitter finishes sending the character
in progress (if any) and sends BREAK characters until
SNDBRK is reset. Because the transmitter samples
SNDBRK after every bit is transmitted, it is important that
SNDBRK is asserted high for a sufficient period of time to
generate a valid BREAK. After the BREAK transmission
completes, the UART transmits 2 mark bits. The user can
continue to fill the TxFIFO and any characters remaining
are transmitted when the BREAK is terminated.
TDMAEN Transmitter Ready DMA Enable—Enables/Disables the
Bit 3 transmit DMA request UART_TX_DMAREQ when the
transmitter has one or more slots available in the TxFIFO.
The fill level in the TxFIFO that generates the
UART_TX_DMAREQ is controlled by the TXTL bits.
UARTCLKEN UART Clock Enable—Enables/Disables all of the
Bit 2
internal clocks of the UART module
27-26
Description
.
MC9328MX1 Reference Manual
Settings
00 = Idle for more than 4 frames
01 = Idle for more than 8 frames
10 = Idle for more than 16 frames
11 = Idle for more than 32 frames
0 = Disables the RRDY interrupt
1 = Enables the RRDY interrupt
0 = Disable UART_RX_DMAREQ
DMA request
1 = Enable UART_RX_DMAREQ
DMA request
0 = Disable the IR interface
1 = Enable the IR interface
0 = Disable the transmitter FIFO
empty interrupt
1 = Enable the transmitter FIFO
empty interrupt
0 = Disable RTSD interrupt
1 = Enable RTSD interrupt
0 = Do not send a BREAK
character
1 = Send a BREAK character
(continuous 0s)
0 = Disable transmit DMA request
1 = Enable transmit DMA request
0 = Disable UART clocks
1 = Enable UART clocks
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