Figure 24-2 Memory Bank Interleaving Options; Table 24-8 Settings For Srefr Field - Motorola DragonBall MC9328MX1 Reference Manual

IAM = 0
Linear Address Map
Page n
• • •
Page 1
Page 0
Page n
• • •
Page 1
Page 0
Page n
• • •
Page 1
Page 0
Page n
• • •
Page 1
Page 0
Rows
Each ~Row/64ms
SREFR
Refresh @ 32 kHz
Clock
00
01 1
10 2
11 4
MOTOROLA
Interleaved Address Map
Figure 24-2. Memory Bank Interleaving Options
Table 24-8. Settings for SREFR Field
~Row/64ms
Row Rate
@ 32 kHz
32.768 kHz
µ
2048
31.25 s
µ
4096
15.62 s
µ
8192
7.81 s
SDRAM Memory Controller
IAM = 1
Page n
Page n
Page n
Page n
• • •
• • •
• • •
• • •
Page 1
Page 1
Page 1
Page 1
Page 0
Page 0
Page 0
Page 0
Row Rate
@ @
32.768 kHz
Refresh disabled
µ
2097
30.52 s
µ
4194
15.26 s
µ
8388
7.63 s
Programming Model
Bank 3
Bank 2
Bank 1
Bank 0
Row Rate
~Row/64ms
@
@ 38.4 kHz
38.4 kHz
µ
2457
26.04 s
µ
4915
13.02 s
µ
9830
6.51 s
24-13