Motorola DragonBall MC9328MX1 Reference Manual page 810

Integrated portable system processor
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USB Device Port
Table 28-15. Endpoint n Interrupt Status Registers Description (Continued)
Name
MDEVREQ
Multiple Device Requests—Asserts when a
Bit 3
DEVREQ interrupt is pending and another setup
packet is received. MDEVREQ asserts only for control
endpoints.
EOT
End-of-Transfer—Asserts when the last packet of a
Bit 2
USB data transfer has crossed into, or out of, the UDC
module. The last packet is identified by its length. Any
packet shorter than the maximum packet size for the
associated endpoint is considered to be an
end-of-transfer marker. The EOT interrupt also
asserts (for control endpoints only) when the number
of bytes specified in the wLength field of the setup
packet has been transferred.
DEVREQ
Device Request—Indicates whether there is a device
Bit 1
request on the current endpoint. DEVREQ asserts
only for control endpoints.
EOF
End-of-Frame—Indicates whether there is
Bit 0
end-of-frame activity for this endpoint. EOF monitors
the data flow between the FIFO and the UDC and
indicates when the end of a USB packet is written into
the FIFO or the UDC as the end of a frame.
28-22
Description
MC9328MX1 Reference Manual
Settings
0 = Multiple setup packets are not
pending
1 = Multiple setup packets pending
0 = Last packet of data not sent/received
1 = Last packet of data sent/received
0 = No request pending
1 = Request pending
0 = End-of-frame (USB packet) not
sent/received
1 = End-of-frame (USB packet)
sent/received
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