Channel Burst Length Registers; Table 13-20 Channel Burst Length Registers Description - Motorola DragonBall MC9328MX1 Reference Manual

DMA Controller

13.4.3.6 Channel Burst Length Registers

The Channel Burst Length registers (BLRx) control the burst length of a DMA cycle. For a FIFO channel
setting, the burst length is normally assigned according to the FIFO size of the selected I/O device, or by
the FIFO level at which its DMA_REQ signal is asserted.
For example, when the UART RxD FIFO is 12
bytes of data, BL is 8. When the memory port size also is 8-bit, the DMA burst is 8-byte reads followed by
8-byte writes.
When the memory port size is smaller than the I/O port size, the burst length of the byte writes is doubled.
For example, the I/O port is 32-bit, the memory port is 16-bit, and the burst length is set to 32. In this
configuration, the DMA performs 8 word burst reads and 16 halfword burst writes for I/O to memory
transfer.
BLR0
BLR1
BLR2
BLR3
BLR4
BLR5
BLR6
BLR7
BLR8
BLR9
BLR10
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Table 13-20. Channel Burst Length Registers Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–6
13-26
×
8 and it asserts DMA_REQ when it receives more than 8
Channel 0 Burst Length Register
Channel 1 Burst Length Register
Channel 2 Burst Length Register
Channel 3 Burst Length Register
Channel 4 Burst Length Register
Channel 5 Burst Length Register
Channel 6 Burst Length Register
Channel 7 Burst Length Register
Channel 8 Burst Length Register
Channel 9 Burst Length Register
Channel 10 Burst Length Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
r r r r
0 0 0 0
Description
MC9328MX1 Reference Manual
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
r r r rw rw
0 0 0 0 0
0x0000
Addr
0x00209094
0x002090D4
0x00209114
0x00209154
0x00209194
0x002091D4
0x00209214
0x00209254
0x00209294
0x002092D4
0x00209314
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
BL
rw rw rw rw
0 0 0 0
Settings
MOTOROLA