Card Clock Control; Programming Model; Figure 20-10 System Clock Control Unit; Table 20-4 Multimedia Controller Register Memory Map - Motorola DragonBall MC9328MX1 Reference Manual

From DAT
Control
Signal
Synchronizer
From MEM
System
Clock
The clock controller also ensures that every clock stop occurs when all clocks are low so the clock division
and enable/disable occur without generating a glitch in the process. The stop clock data unit enables the
data state machine to stop the clock when the application is too slow and does not update the FIFO on time
in a multiple block/stream write or read.

20.5.4.1 Card Clock Control

The MMC/SD host controller controls the clocking for the MMC/SD cards. The MMC/SD module can
lower the clock frequency or even turn off the clock to the cards to save energy. The MMC/SD module
provides at least 8 clock cycles after the last MMC/SD bus transaction (command, response, data, CRC)
before shutting off the clock.

20.6 Programming Model

The MMC/SD Host Controller module includes fifteen 32-bit registers that the application configures
before every operation on the multimedia bus. Table 20-4 summarizes these registers and their addresses.
Table 20-4. Multimedia Controller Register Memory Map
MMC/SD Clock Control Register
MMC/SD Clock Rate Register
MMC/SD Command and Data Control Register
MMC/SD Response Time-Out Register
MMC/SD Read Time-Out Register
MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD)
CLK_ON
CLK_OFF
START_CLK
STOP_CLK
Clock
CLK_RATE
Prescaler
CLK
Prescaler
Figure 20-10. System Clock Control Unit
Description
MMC/SD Status Register
Inner
CLK
Control
FSM
External
CLK
Control
CLK_EN
DFF
CLK_DIV
Counter
Name
STR_STP_CLK
STATUS
CLK_RATE
CMD_DAT_CONT
RES_TO
READ_TO
Programming Model
CLK_DIV
Gate CLK_20M
SDHC_CLK
Address
0x00214000
0x00214004
0x00214008
0x0021400C
0x00214010
0x00214014
20-13