Asp Control Register; Table 15-7 Control Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Integrated portable system processor
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15.5.1 ASP Control Register

The Control Register determines the configuration of PADC block.
ASP_ACNTLCR
BIT
31
30
29
TYPE
r
r
r
0
0
0
RESET
BIT
15
14
13
AZE
AUTO
MOD
TYPE
rw
rw
rw
0
0
0
RESET
Name
Reserved
Reserved—These bits are reserved and should read 0.
Bits 31–28
ASWB
Auto Mode Switch Bypass—Controls the switch settings
Bit 27
in Auto XY mode with AZ off. When enabled, switch settings
take the value of SW[7...0], otherwise is determined by
internal logic. This is only for ATE test (debug) purpose.
ACAL
Auto Mode Calibration—Enables/Disables switch settings
Bit 26
for auto-calibration in auto-ZXY mode. Switch settings for X
/ Y are changed from C6 / 39, to CC / 33 respectively.
CLKEN
Clock Enable—Enables/Disables the clock into the Pen
Bit 25
ADC clock generator. This is used to save power when the
Pen ADC is not in use.
Reserved
Reserved—This bit is reserved and should read 0.
Bit 24
SWRST
Software Reset—Resets the entire ASP module. All ASP
Bit 23
registers will be restored to default value upon reset.
Reserved
Reserved—This bit is reserved and should read 0.
Bit 22
U_SEL
U-Channel Resistor Selection—Selects which external
Bit 21
resistor to use for U-channel measurement.
MOTOROLA
Control Register
28
27
26
25
24
ASW
ACA
CLKEN
B
L
r
rw
rw
rw
0
0
0
1
12
11
10
9
SW8 SW7
SW6
SW5
rw
rw
rw
rw
rw
0
0
0
0
Table 15-7. Control Register Description
Description
Analog Signal Processor (ASP)
23
22
21
SWRST
U_SEL AZ_SEL
r
rw
r
rw
0
0
0
0
0x0200
8
7
6
5
SW4
SW3
SW2
rw
rw
rw
0
0
0
0
0x0000
1 = Bypass enable. Switches are
0 = Bypass disable. Switches are
1 = Enable
0 = Disable
0 = Disable clock into the ADC
1 = Enable clock into Pen ADC
0 = No effect
1 = Reset -This automatically
0 = Resistor at UIN and UIP pins
1 = Resistor at R1a and R2a pins
Programming Model
Addr
0x00215010
20
19
18
17
rw
r
r
r
0
0
0
0
4
3
2
1
SW1
PADE BGE
rw
r
r
rw
0
0
0
0
Settings
set by SW[7:0]
set by internal logic
clock generator
clock generator
restores to 0
16
r
0
0
rw
0
15-9

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