Motorola DragonBall MC9328MX1 Reference Manual page 221

Table 11-5. Chip Select Control Registers Description (Continued)
Name
WEN EB [3:0] Negate During Write—Determines
Bits 19–16 when EB [3:0] outputs are negated during a write
cycle. This is useful to meet data hold time
requirements for slow memories.
WEN does not affect the cycle length.
WEN is cleared by a hardware reset.
CSA Chip Select Assert—Determines when chip
Bits 15–12 select is asserted and negated for devices that
require additional address setup time and
additional address/data hold times. CSA affects
only external writes, and is ignored on external
reads.
CSA does not affect the cycle length.
CSA is cleared by a hardware reset.
EBC Enable Byte Control—Indicates the access
Bit 11 types that assert the enable byte outputs (EB
[3:0]).
EBC is set by a hardware reset.
DSZ Data Port Size—Defines the width of the external
Bits 10–8 device's data port as shown in the table, DSZ Bit
Encoding, to the right. At hardware reset, the
value of DSZ is 000 for CS1– CS5. For CS0, DSZ
is mapped based on the value of the
EIM_BOOT_DSZ [2:0] bits. EIM_BOOT_DSZ [2]
maps to DSZ [2], EIM_BOOT_DSZ [1] maps to
DSZ [1] and EIM_BOOT_DSZ [0] maps to DSZ
[0].
Reserved Reserved—This bit is reserved and should read 0.
Bit 7
SP Supervisor Protect—Prevents accesses to the
Bit 6 address range defined by the corresponding chip
select when the access is attempted in the User
mode of ARM9 core operation.
SPI is cleared by a hardware reset.
Reserved Reserved—This bit is reserved and should read 0.
Bit 5
MOTOROLA
Description
External Interface Module (EIM)
Programming Model
Settings
0000 = 0 half clocks before end of access
0001 = 1 half clock before end of access
...
1111 = 15 half clocks before end of access
0000 = 0 clocks before assertion and 0
clocks following negation
0001 = 1 clock before assertion and 1 clock
following negation
...
1111 = 15 clocks before assertion and 15
clocks after negation
0 = Both read and write accesses assert the
EB [3:0] outputs, thus configuring the
access as byte enables
1 = Only write accesses assert the EB [3:0]
outputs, thus configuring the access as
byte write enables; the EB [3:0] outputs
are configured as byte write enables for
accesses to dual x16 or quad x8
memories
000 = 8-bit port, resides on D [31:24] pins
001 = 8-bit port, resides on D [23:16] pins
010 = 8-bit port, resides on D [15:8] pins
011 = 8-bit port, resides on D [7:0] pins
100 = 16-bit port, resides on D [31:16] pins
101 = 16-bit port, resides on D [15:0] pins
11x = 32-bit port
0 = User mode accesses are allowed in the
range of chip select
1 = User mode accesses are prohibited;
attempts to access an address mapped
by this chip select in User mode results
in a TEA to the ARM9 core and no
assertion of the chip select output
11-17