Arm920T Modes And Registers; Table 4-3 Register Availability By Mode - Motorola DragonBall MC9328MX1 Reference Manual

Mnemonic
LDR
LDRH
LDRB
LDRSH
LDMIA
PUSH

4.6.1 ARM920T Modes and Registers

The modes and registers of the ARM920T processor are shown in Table 4-3.
User and Supervisor
System Modes Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13 R13_SVC
R14 R14_SVC
PC
CPSR CPSR
SPSR_SVC
= Mode-specific banked registers
MOTOROLA
Table 4-2. ARM Thumb Instruction Set (Continued)
Operation
Load Word
Load Halfword
Load Byte
Load Signed Halfword
Load Multiple
Push Registers to stack
Table 4-3. Register Availability by Mode
Abort Mode
R0 R0
R1 R1
R2 R2
R3 R3
R4 R4
R5 R5
R6 R6
R7 R7
R8 R8
R9 R9
R10 R10
R11 R11
R12 R12
R13_ABORT
R14_ABORT
PC PC
CPSR
SPSR_ABORT
ARM920T Processor
The ARM Thumb Instruction Set
Mnemonic
STR
STRH
STRB
LDRSB
STMIA
POP
Undefined
Interrupt Mode
Mode
R0 R0
R1 R1
R2 R2
R3 R3
R4 R4
R5 R5
R6 R6
R7 R7
R8 R8
R9 R9
R10 R10
R11 R11
R12 R12
R13_UNDEF R13_IRQ
R14_UNDEF R14_IRQ
PC PC
CPSR CPSR
SPSR_UNDEF SPSR_IRQ
Operation
Store Word
Store Halfword
Store Byte
Load Signed Byte
Store Multiple
Pop Registers from stack
Fast Interrupt
Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
PC
CPSR
SPSR_FIQ
4-9