Table 12-5 Clock Source Control Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Phase-Locked Loop and Clock Controller
CSCR
BIT 31 30 29
CLKO_SEL
TYPE rw rw rw
0 0 0
RESET
BIT 15 14 13
PRESC
TYPE rw r rw
1 0 1
RESET
Table 12-5. Clock Source Control Register Description
Name
CLKO_SEL CLKO Select—Selects the clock signal source
Bits 31–29 that is output on the CLKO pin.
USB_DIV USB Divider—Contains the integer divider value
Bits 28–26 used to generate the CLK48M signal for the USB
modules.
SD_CNT Shut-Down Control—Contains the value that sets
Bits 25–24 the duration of System PLL clock output after 0 is
written to the SPEN bit. The power controller
requests the bus before System PLL shutdown.
Any unmasked interrupt event enables the System
PLL.
Reserved Reserved—This bit is reserved and should read 0.
Bit 23
12-6
Clock Source Control Register
28 27 26 25 24
USB_DIV SD_CNT
rw rw rw rw rw
0 1 1 1 1
12 11 10 9 8
BCLK_DIV
rw rw rw r r
0 1 1 0 0
Description
MC9328MX1 Reference Manual
23 22 21
SPLL_ MPLL_
RESTART RESTART
r rw rw
0 0 0
0x0F00
7 6 5
r r r
0 0 0
0xAC03
000 = PERCLK1
001 = HCLK
010 = CLK48M
011 = CLK16M
100 = PREMCLK
101 = FCLK
000 = System PLL clock divide by 1
001 = System PLL clock divide by 2
.
.
.
111 = System PLL clock divide by 8
00 = System PLL shuts down after next
rising edge of CLK32 is detected and
the current bus cycle is completed. A
minimum of 16 HCLK cycles is
guaranteed from writing "0" to SPEN
bit.
01 = System PLL shuts down after the
second rising edge of CLK32 is
detected and the current bus cycle is
completed.
10 = System PLL shuts down after the third
rising edge of CLK32 is detected and
the current bus cycle is completed.
11 = System PLL shuts down after forth
rising edge of CLK32 is detected and
the current bus cycle is completed.
Addr
0x0021B000
20 19 18 17
CLK16 OSC System
_SEL _EN _SEL
r r rw rw
0 0 0 0
4 3 2 1
SPEN MPEN
r r r rw
0 0 0 1
Settings
MOTOROLA
16
rw
0
0
rw
1